vgsp: m96 - gr_pte_kind: set the Turing v2 PTE KIND on the window-0 shadow pool

UVM's Turing PTE maker sets KIND=GENERIC_MEMORY (0x06) in PTE bits 63:56
because PITCH no longer exists on Turing (uvm_turing_mmu.c:32-34,106;
NV_MMU_PTE_KIND_GENERIC_MEMORY=0x06, NV_MMU_VER2_PTE_KIND=63:56). Our
shadow PTEs encode kind=0. The SM I-fetch refuses the kind-0 PTE with
MMU_NACK while the FE tolerates it, so gr_pte_kind (default 0) selects the
KIND for the window-0 pool. Also log the VASPDB root DMA at
SET_PAGE_DIRECTORY time (settles whether the SC PDB the server programs is
our chunk).

3 files changed, 43 insertions, 2 deletions

diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index 51d6685..28bf6f9 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -9257,9 +9257,23 @@ static void gsp_phys_rmcall_pdb_build(void)
 				u64 va = GSP_PHYS_RMCALL_VA_GR_SHADOW0_BASE +
 					 (u64)s * GSP_PHYS_PAGE_SIZE;
 				u32 idx = (u32)((va >> 12) & 0x1ffu);
+				u64 pte = gsp_phys_rmcall_pte(
+					(u64)gsp_phys_chunk_page_dma(w0, s));
+				u32 kind =
+					(u32)gsp_phys_rmcall_gr_pte_kind_value();
 
-				put_unaligned_le64(gsp_phys_rmcall_pte(
-						(u64)gsp_phys_chunk_page_dma(w0, s)),
+				/*
+				 * m96: on Turing the v2 PTE KIND field (63:56)
+				 * has no PITCH entry (UVM turing sets
+				 * GENERIC_MEMORY 0x06; "PITCH no longer
+				 * exists"); a kind=0 PTE is what the SM
+				 * I-fetch refuses with MMU_NACK while the
+				 * FE tolerates it. gr_pte_kind selects the
+				 * kind for the shadow pool.
+				 */
+				if (kind)
+					pte |= (u64)kind << 56;
+				put_unaligned_le64(pte,
 					(u8 *)gsp_phys_chunk_page_va(pt, 0) +
 					(size_t)idx * 8);
 			}
@@ -13421,6 +13435,12 @@ static int gsp_phys_rmcall_stage3(void __iomem *bar0)
 	memset(&pdb, 0, sizeof(pdb));
 	pdb.phys_address = cpu_to_le64((u64)gsp_phys_chunk_page_dma(
 		&boot_stage.rmcall_chunks[GSP_PHYS_RMCALL_BUF_VASPDB], 0));
+	pr_info("vgsp-boot: rm-call: PDB root dma=0x%llx num_entries=%u flags=0x%x\n",
+		(u64)gsp_phys_chunk_page_dma(
+			&boot_stage.rmcall_chunks[GSP_PHYS_RMCALL_BUF_VASPDB], 0),
+		GSP_PHYS_RMCALL_PDB_NUM_ENTRIES,
+		GSP_PHYS_RMCALL_PDB_FLAG_APERTURE_SYSMEM_NONCOH |
+			GSP_PHYS_RMCALL_PDB_FLAG_ALL_CHANNELS);
 	pdb.num_entries = cpu_to_le32(GSP_PHYS_RMCALL_PDB_NUM_ENTRIES);
 	pdb.flags = cpu_to_le32(GSP_PHYS_RMCALL_PDB_FLAG_APERTURE_SYSMEM_NONCOH |
 				GSP_PHYS_RMCALL_PDB_FLAG_ALL_CHANNELS);
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c
index 3b2feb4..37eff49 100644
--- a/kernel/gsp_phys_gpu.c
+++ b/kernel/gsp_phys_gpu.c
@@ -994,6 +994,24 @@ int gsp_phys_rmcall_gr_ptr_guest_value(void)
 EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_ptr_guest_value);
 
 /*
+ * m96: KIND (PTE bits 63:56) for the window-0 shadow pool PTEs. On Turing
+ * the v2 PTE has no PITCH kind; UVM sets GENERIC_MEMORY (0x06). A kind=0
+ * PTE is a candidate for the SM I-fetch MMU_NACK while the FE tolerates it.
+ * Default 0 = keep the historical kind-0 encoding.
+ */
+static int gsp_phys_rmcall_gr_pte_kind_param;
+module_param_named(gsp_phys_rmcall_gr_pte_kind,
+		   gsp_phys_rmcall_gr_pte_kind_param, int, 0644);
+MODULE_PARM_DESC(gsp_phys_rmcall_gr_pte_kind,
+		 "KIND (63:56) for window-0 shadow PTEs; 6 = GENERIC_MEMORY (default 0)");
+
+int gsp_phys_rmcall_gr_pte_kind_value(void)
+{
+	return gsp_phys_rmcall_gr_pte_kind_param;
+}
+EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_pte_kind_value);
+
+/*
  * m95: program each GPC's MMU_CTRL from the hub's PFB MMU_CTRL (the real RM's
  * grInitGPCMmuPRIRegs matching-fields copy) before a forwarded launch. The
  * GPC-side walker refuses the SM I-fetch with MMU_NACK while hub-side reads
diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h
index 9bd5df3..7df30cb 100644
--- a/kernel/gsp_phys_gpu.h
+++ b/kernel/gsp_phys_gpu.h
@@ -343,6 +343,9 @@ int gsp_phys_rmcall_gr_ptr_guest_value(void);
 /* m95: program GPC MMU_CTRL from PFB MMU_CTRL before a forwarded launch. */
 int gsp_phys_rmcall_gr_gpc_mmu_init_value(void);
 
+/* m96: KIND (63:56) for window-0 shadow PTEs (0 = historical kind 0). */
+int gsp_phys_rmcall_gr_pte_kind_value(void);
+
 /* m72: append the vendor local-memory context block to the GR prelude so
  * SKEDCHECK05 LOCAL_MEMORY_TOTAL_SIZE passes (default 0); base VA and
  * per-TPC size are overridable for A/B runs. */