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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 10:44:20 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 10:44:20 -0400 |
| commit | 2520bdb490398c1190d53fbd700ecba178fe8bb9 (patch) | |
| tree | 64e41678e6174624182c69fb8134dc16e796dd8e /kernel/gsp_phys_gpu.c | |
| parent | bfbe85f50f5243e601d98fe40b43e364c3e8901f (diff) | |
| download | open-iov-2520bdb490398c1190d53fbd700ecba178fe8bb9.tar.gz open-iov-2520bdb490398c1190d53fbd700ecba178fe8bb9.zip | |
vgsp: m78 - lane-enable skip mask + best-effort lane tail (#1063 no longer aborts it)
gsp_phys_rmcall_gr_lane_skip: bit0 skips #1059 CILP mode, bit1 skips #1061
timeslice, bit2 skips #1063 device-sched. Used to bisect which lane-enable
control arms the forwarded QMD enqueue and which one leaves the scheduling
state that ends in the dispatch-time context save. Also makes the m76 lane
tail independent of #1063 (always refused 0x1f by the server).
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index a394425..a71ab97 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -796,6 +796,25 @@ unsigned int gsp_phys_rmcall_gr_lmem_tpc_size_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lmem_tpc_size_value); /* + * m78 lane-enable skip mask (gsp_phys_rmcall_gr_lane_skip; default 0). Bit 0 + * skips R2 #1059 GR_SET_CTXSW_PREEMPTION_MODE (CILP), bit 1 skips #1061 + * SET_TIMESLICE, bit 2 skips #1063 device-sched. Used to bisect which + * lane-enable control arms the enqueue and which one leaves the scheduling + * state that ends in the dispatch-time context save. + */ +static int gsp_phys_rmcall_gr_lane_skip_param; +module_param_named(gsp_phys_rmcall_gr_lane_skip, + gsp_phys_rmcall_gr_lane_skip_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_lane_skip, + "Skip lane-enable controls: 1=#1059 CILP, 2=#1061 timeslice, 4=#1063 device-sched (default 0)"); + +int gsp_phys_rmcall_gr_lane_skip_value(void) +{ + return gsp_phys_rmcall_gr_lane_skip_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lane_skip_value); + +/* * m76 lane tail (gsp_phys_rmcall_gr_lane_tail; default 0). When set, the * mode-35 lane enable also sends the R2 capture's tail after #1063: TSG * PREEMPT (bWait=1, #1073), device-sched disable (#1075) and the |