vgsp: m78 - lane-enable skip mask + best-effort lane tail (#1063 no longer aborts it)

gsp_phys_rmcall_gr_lane_skip: bit0 skips #1059 CILP mode, bit1 skips #1061
timeslice, bit2 skips #1063 device-sched. Used to bisect which lane-enable
control arms the forwarded QMD enqueue and which one leaves the scheduling
state that ends in the dispatch-time context save. Also makes the m76 lane
tail independent of #1063 (always refused 0x1f by the server).

3 files changed, 75 insertions, 27 deletions

diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index b8de6c3..241fe04 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -13168,6 +13168,7 @@ static int gsp_phys_rmcall_user_lane_lane_enable(void __iomem *bar0)
 	struct gsp_phys_rmcall_preemption_params pp;
 	struct gsp_phys_rmcall_timeslice_params ts;
 	struct gsp_phys_rmcall_device_sched_params ds;
+	u32 skip = (u32)gsp_phys_rmcall_gr_lane_skip_value();
 	u32 rpc_result = 0, status = 0;
 	int ret;
 
@@ -13176,39 +13177,63 @@ static int gsp_phys_rmcall_user_lane_lane_enable(void __iomem *bar0)
 	pp.h_channel_group = cpu_to_le32(boot_stage.rmcall_tsg);
 	pp.cilp_ctxsw_preempt_mode =
 		cpu_to_le32(GSP_PHYS_RMCALL_PREEMPT_MODE_CILP);
-	ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_subdevice,
-			GSP_PHYS_RMCALL_CTRL_GR_SET_CTXSW_PREEMPTION_MODE,
-			&pp, sizeof(pp), 16, NULL, 0, &rpc_result, &status,
-			"GR_SET_CTXSW_PREEMPTION_MODE (mode 35 lane enable, R2 #1059)");
-	pr_info("vgsp-boot: rm-call: mode 35 lane enable #1059 GR_SET_CTXSW_PREEMPTION_MODE: flags=0x%x hChannelGroup=0x%x cilp=%u status=0x%x rpc_result=0x%x ret=%d\n",
-		le32_to_cpu(pp.flags), le32_to_cpu(pp.h_channel_group),
-		le32_to_cpu(pp.cilp_ctxsw_preempt_mode), status, rpc_result, ret);
-	if (ret)
-		return ret;
+	if (skip & 1u) {
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1059 GR_SET_CTXSW_PREEMPTION_MODE SKIPPED by gsp_phys_rmcall_gr_lane_skip=0x%x\n",
+			skip);
+	} else {
+		ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_subdevice,
+				GSP_PHYS_RMCALL_CTRL_GR_SET_CTXSW_PREEMPTION_MODE,
+				&pp, sizeof(pp), 16, NULL, 0, &rpc_result,
+				&status,
+				"GR_SET_CTXSW_PREEMPTION_MODE (mode 35 lane enable, R2 #1059)");
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1059 GR_SET_CTXSW_PREEMPTION_MODE: flags=0x%x hChannelGroup=0x%x cilp=%u status=0x%x rpc_result=0x%x ret=%d\n",
+			le32_to_cpu(pp.flags),
+			le32_to_cpu(pp.h_channel_group),
+			le32_to_cpu(pp.cilp_ctxsw_preempt_mode), status,
+			rpc_result, ret);
+		if (ret)
+			return ret;
+	}
 
 	memset(&ts, 0, sizeof(ts));
 	ts.timeslice = cpu_to_le32(GSP_PHYS_RMCALL_LANE_TIMESLICE);
-	ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_tsg,
-			GSP_PHYS_RMCALL_CTRL_SET_TIMESLICE,
-			&ts, sizeof(ts), 16, NULL, 0, &rpc_result, &status,
-			"SET_TIMESLICE (mode 35 lane enable, R2 #1061)");
-	pr_info("vgsp-boot: rm-call: mode 35 lane enable #1061 SET_TIMESLICE: timeslice=0x%x hTsg=0x%x status=0x%x rpc_result=0x%x ret=%d\n",
-		le32_to_cpu(ts.timeslice), boot_stage.rmcall_tsg,
-		status, rpc_result, ret);
-	if (ret)
-		return ret;
+	if (skip & 2u) {
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1061 SET_TIMESLICE SKIPPED by gsp_phys_rmcall_gr_lane_skip=0x%x\n",
+			skip);
+	} else {
+		ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_tsg,
+				GSP_PHYS_RMCALL_CTRL_SET_TIMESLICE,
+				&ts, sizeof(ts), 16, NULL, 0, &rpc_result,
+				&status,
+				"SET_TIMESLICE (mode 35 lane enable, R2 #1061)");
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1061 SET_TIMESLICE: timeslice=0x%x hTsg=0x%x status=0x%x rpc_result=0x%x ret=%d\n",
+			le32_to_cpu(ts.timeslice), boot_stage.rmcall_tsg,
+			status, rpc_result, ret);
+		if (ret)
+			return ret;
+	}
 
 	memset(&ds, 0, sizeof(ds));
 	ds.enable = cpu_to_le32(1);
-	ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_device,
-			GSP_PHYS_RMCALL_CTRL_DEVICE_SCHED,
-			&ds, sizeof(ds), 16, NULL, 0, &rpc_result, &status,
-			"NV01 device sched (mode 35 lane enable, R2 #1063)");
-	pr_info("vgsp-boot: rm-call: mode 35 lane enable #1063 device sched: enable=%u hDevice=0x%x status=0x%x rpc_result=0x%x ret=%d\n",
-		le32_to_cpu(ds.enable), boot_stage.rmcall_device,
-		status, rpc_result, ret);
-	if (ret)
-		return ret;
+	if (skip & 4u) {
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1063 device sched SKIPPED by gsp_phys_rmcall_gr_lane_skip=0x%x\n",
+			skip);
+	} else {
+		ret = gsp_phys_rmcall_control(bar0, boot_stage.rmcall_device,
+				GSP_PHYS_RMCALL_CTRL_DEVICE_SCHED,
+				&ds, sizeof(ds), 16, NULL, 0, &rpc_result,
+				&status,
+				"NV01 device sched (mode 35 lane enable, R2 #1063)");
+		pr_info("vgsp-boot: rm-call: mode 35 lane enable #1063 device sched: enable=%u hDevice=0x%x status=0x%x rpc_result=0x%x ret=%d\n",
+			le32_to_cpu(ds.enable), boot_stage.rmcall_device,
+			status, rpc_result, ret);
+	}
+	/*
+	 * #1063 is best-effort by design (the server has always refused it
+	 * with 0x1f and the lane still enqueues); do not abort the tail on
+	 * its failure.
+	 */
+	ret = 0;
 
 	/*
 	 * R2 #1073/#1075/#1077 lane tail (gsp_phys_rmcall_gr_lane_tail;
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c
index a394425..a71ab97 100644
--- a/kernel/gsp_phys_gpu.c
+++ b/kernel/gsp_phys_gpu.c
@@ -796,6 +796,25 @@ unsigned int gsp_phys_rmcall_gr_lmem_tpc_size_value(void)
 EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lmem_tpc_size_value);
 
 /*
+ * m78 lane-enable skip mask (gsp_phys_rmcall_gr_lane_skip; default 0). Bit 0
+ * skips R2 #1059 GR_SET_CTXSW_PREEMPTION_MODE (CILP), bit 1 skips #1061
+ * SET_TIMESLICE, bit 2 skips #1063 device-sched. Used to bisect which
+ * lane-enable control arms the enqueue and which one leaves the scheduling
+ * state that ends in the dispatch-time context save.
+ */
+static int gsp_phys_rmcall_gr_lane_skip_param;
+module_param_named(gsp_phys_rmcall_gr_lane_skip,
+		   gsp_phys_rmcall_gr_lane_skip_param, int, 0644);
+MODULE_PARM_DESC(gsp_phys_rmcall_gr_lane_skip,
+		 "Skip lane-enable controls: 1=#1059 CILP, 2=#1061 timeslice, 4=#1063 device-sched (default 0)");
+
+int gsp_phys_rmcall_gr_lane_skip_value(void)
+{
+	return gsp_phys_rmcall_gr_lane_skip_param;
+}
+EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lane_skip_value);
+
+/*
  * m76 lane tail (gsp_phys_rmcall_gr_lane_tail; default 0). When set, the
  * mode-35 lane enable also sends the R2 capture's tail after #1063: TSG
  * PREEMPT (bWait=1, #1073), device-sched disable (#1075) and the
diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h
index 3a590ea..216c96e 100644
--- a/kernel/gsp_phys_gpu.h
+++ b/kernel/gsp_phys_gpu.h
@@ -358,6 +358,10 @@ int gsp_phys_rmcall_gr_r1_first_value(void);
  * enable (TSG preempt bWait, device-sched off, perf boost; default 0). */
 int gsp_phys_rmcall_gr_lane_tail_value(void);
 
+/* m78: skip lane-enable controls by bit (1=#1059 CILP, 2=#1061 timeslice,
+ * 4=#1063 device-sched); default 0 = send all. */
+int gsp_phys_rmcall_gr_lane_skip_value(void);
+
 /*
  * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0).
  * 0 = FERMI_VASPACE_A is allocated IS_EXTERNALLY_OWNED (historical ladder