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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-01 13:11:30 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-01 13:11:30 -0400 |
| commit | 4254b221f393e5262083e5d7158110b934a52e57 (patch) | |
| tree | 4fe1ce2042ab11761485cecd30623000df721029 /docs/03-architecture/08-physical-gpu-integration.md | |
| parent | 0f6451f9823e520d1a285b0912589053ad1fc26e (diff) | |
| download | open-iov-4254b221f393e5262083e5d7158110b934a52e57.tar.gz open-iov-4254b221f393e5262083e5d7158110b934a52e57.zip | |
gsp-phys: queue the pre-boot GSP_SET_SYSTEM_INFO and SET_REGISTRY async RPCs
The real-GSP boot path staged the message queue but never queued the two
fire-and-forget init RPCs the production client places in it before the
booter starts. GSP-RM therefore created its GPU object without any system
information and aborted RM init (live GSP_INIT_DONE rpc_result=0x59), with
the resource-manager's object-database lookups asserting from the first
journal record.
Submit function 72 (GSP_SET_SYSTEM_INFO, 928-byte v17_00 payload carrying
the BAR physical bases, domain/bus/slot, PCI IDs, the BAR0 config-mirror
offset, link/FLR capabilities and upstream-port flags read from the
pci_dev) and function 73 (SET_REGISTRY, header-only empty table, which the
server explicitly accepts) through the existing submit-only queue producer
after all stage-3d preconditions and before the GSP falcon reset/Booter
Load kick. The wire layouts are re-declared in the module with per-field
static asserts against the reference ABI; payloads are heap-allocated, so
no new stack frames are introduced.
Diffstat (limited to 'docs/03-architecture/08-physical-gpu-integration.md')
| -rw-r--r-- | docs/03-architecture/08-physical-gpu-integration.md | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/docs/03-architecture/08-physical-gpu-integration.md b/docs/03-architecture/08-physical-gpu-integration.md index c0db8ec..9949227 100644 --- a/docs/03-architecture/08-physical-gpu-integration.md +++ b/docs/03-architecture/08-physical-gpu-integration.md @@ -196,7 +196,12 @@ first server event**: FWSEC raised WPR2 with a zero FRTS error code (`RISCV_STATUS=0x00000035`) with `FALCON_OS=0`, and a host-driven boot sets only the booter-load handoff bit (bit 24) in secure scratch14. Stage 4 has begun: the staged command/status queues linked and the first real GSP-RM -message arrived (event 0x1002, run-CPU-sequencer, `rpc_result=0`). The server +message arrived (event 0x1002, run-CPU-sequencer, `rpc_result=0`). Before the +Booter Load kick the module also queues the two pre-boot asynchronous init +RPCs the production client sends in the same spot: `GSP_SET_SYSTEM_INFO` (72, +the host/GPU address and PCI environment description GSP-RM consumes before it +creates its GPU object) and `SET_REGISTRY` (73; a header-only empty table, +which the server explicitly accepts). The server waits for the host to execute the sequencer command buffer carried in that event before it raises `GSP_INIT_DONE` (0x1001). **A plain release is not yet possible:** the Booter Unload gate requires all four secure scratch14 handoff |