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#ifndef _NV_VGPU_IRQ_H_
#define _NV_VGPU_IRQ_H_
#include "nvidia-vgpu-vfio.h"
#define NV_VGPU_MAX_MSI_VECTORS 32
struct nv_vgpu_msi_irq {
int virq;
u32 vector;
bool enabled;
struct eventfd_ctx *trigger;
struct irq_domain *domain;
struct msi_msg msg;
};
struct nv_vgpu_irq_ctx {
struct nv_vgpu_device *vgpu;
struct mutex lock;
struct nv_vgpu_msi_irq msis[NV_VGPU_MAX_MSI_VECTORS];
int msi_count;
bool msi_enabled;
bool msix_enabled;
};
int nv_vgpu_irq_init(struct nv_vgpu_device *vgpu);
void nv_vgpu_irq_cleanup(struct nv_vgpu_device *vgpu);
int nv_vgpu_irq_enable(struct nv_vgpu_device *vgpu, int irq_idx);
int nv_vgpu_irq_disable(struct nv_vgpu_device *vgpu, int irq_idx);
int nv_vgpu_irq_setup_msi(struct nv_vgpu_device *vgpu, int num_vectors);
int nv_vgpu_irq_setup_msix(struct nv_vgpu_device *vgpu, int num_vectors);
void nv_vgpu_irq_teardown_msi(struct nv_vgpu_device *vgpu);
void nv_vgpu_irq_teardown_msix(struct nv_vgpu_device *vgpu);
int nv_vgpu_irq_set_trigger(struct nv_vgpu_device *vgpu, int irq_idx, int fd);
int nv_vgpu_irq_get_virq(struct nv_vgpu_device *vgpu, int irq_idx);
static inline struct nv_vgpu_irq_ctx *vgpu_to_irq_ctx(struct nv_vgpu_device *vgpu)
{
return (struct nv_vgpu_irq_ctx *)vgpu->irq_ctx;
}
#endif
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