1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
|
/*
* GSP RPC Integration Layer Header
* Bridges the firmware-decompiled RPC client with existing gsp_comm.c
*/
#ifndef _NV_VGPU_GSP_RPC_INTEGRATION_H_
#define _NV_VGPU_GSP_RPC_INTEGRATION_H_
#include "nvidia-vgpu-vfio.h"
#include "gsp_comm.h"
/* Initialize the RPC integration layer */
int nv_vgpu_gsp_rpc_integration_init(struct nv_vgpu_device *vgpu,
struct nv_vgpu_gsp_comm_ctx *comm_ctx);
/* Cleanup the RPC integration layer */
void nv_vgpu_gsp_rpc_integration_cleanup(struct nv_vgpu_device *vgpu);
/* ============================================================
* Enhanced RPC Operations (using firmware-decompiled addresses)
* ============================================================ */
/* Memory allocation with full firmware parameter support */
int nv_vgpu_gsp_rpc_alloc_fw(struct nv_vgpu_device *vgpu,
u64 size, u64 alignment, u32 mem_type,
u32 flags, u64 addr_hint, u32 pid,
u64 *gpu_va, u64 *handle, u64 *actual_size);
/* Memory free */
int nv_vgpu_gsp_rpc_free_fw(struct nv_vgpu_device *vgpu, u64 handle);
/* Memory mapping with full firmware parameter support */
int nv_vgpu_gsp_rpc_map_fw(struct nv_vgpu_device *vgpu,
u64 handle, u64 gpu_va, u64 size,
u32 prot, u32 flags, u64 offset,
u64 *mapped_va);
/* Memory unmapping */
int nv_vgpu_gsp_rpc_unmap_fw(struct nv_vgpu_device *vgpu,
u64 handle, u64 gpu_va, u64 size);
/* Page pinning for DMA */
int nv_vgpu_gsp_rpc_pin_fw(struct nv_vgpu_device *vgpu,
u64 handle, u64 offset, u64 size,
u32 flags, u64 *dma_addr, u32 *num_pages);
/* Page unpinning */
int nv_vgpu_gsp_rpc_unpin_fw(struct nv_vgpu_device *vgpu,
u64 handle, u64 offset, u64 size);
/* Work scheduling */
int nv_vgpu_gsp_rpc_schedule_fw(struct nv_vgpu_device *vgpu,
u64 work_handle, u64 callback, u64 arg,
u32 priority, u32 flags);
/* Yield current work */
int nv_vgpu_gsp_rpc_yield_fw(struct nv_vgpu_device *vgpu);
/* BAR trap emulation */
int nv_vgpu_gsp_rpc_bar_trap_fw(struct nv_vgpu_device *vgpu,
u64 bar_addr, u32 access_type, u32 size,
u64 value, u32 bar_num, u64 *ret_value);
/* Migration - save state */
int nv_vgpu_gsp_rpc_migrate_save_fw(struct nv_vgpu_device *vgpu,
u64 src_gpu_id, u64 dst_gpu_id,
u64 memory_bitmap, u64 page_table_ptr,
u64 *checkpoint);
/* Migration - restore state */
int nv_vgpu_gsp_rpc_migrate_restore_fw(struct nv_vgpu_device *vgpu,
u64 src_gpu_id, u64 dst_gpu_id,
u64 memory_bitmap, u64 page_table_ptr,
u64 checkpoint);
/* ============================================================
* WPR Management (from firmware strings: VPR_WPR_WRITE_MUTEX*)
* ============================================================ */
int nv_vgpu_gsp_wpr_write_mutex_acquire(struct nv_vgpu_device *vgpu, u32 wpr_id);
int nv_vgpu_gsp_wpr_write_mutex_release(struct nv_vgpu_device *vgpu, u32 wpr_id);
int nv_vgpu_gsp_wpr_scratch_mutex_acquire(struct nv_vgpu_device *vgpu, u32 wpr_id);
int nv_vgpu_gsp_wpr_scratch_mutex_release(struct nv_vgpu_device *vgpu, u32 wpr_id);
/* ============================================================
* Firmware Address Accessors (for debugging/validation)
* ============================================================ */
u64 nv_vgpu_gsp_get_primary_dispatcher(void); /* 0x057a1ac0 */
u64 nv_vgpu_gsp_get_secondary_dispatcher(void); /* 0x04ed39dc */
u64 nv_vgpu_gsp_get_alloc_main(void); /* 0x057e94ec */
u64 nv_vgpu_gsp_get_schedule_main(void); /* 0x051efbf4 */
u64 nv_vgpu_gsp_get_bar_trap_handler_jt(void); /* 0x057675b7 */
u64 nv_vgpu_gsp_get_bar_trap_handler_primary(void); /* 0x04cb8189 */
u64 nv_vgpu_gsp_get_entry_point(void); /* 0x04009000 */
#endif /* _NV_VGPU_GSP_RPC_INTEGRATION_H_ */
|
