debug/risc-v-gsp-rm-vm/firmware/uproc_demo/linker.ld


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/* risc-v-gsp-rm-debugger uproc demo firmware - RISC-V 64 bare-metal test target.
 *
 * Mimics the shape of a GSP-side micro-service: a global control block with a
 * magic, a handler table and counters; a mailbox-driven RPC dispatcher; a
 * multi-stage state machine handler; and an intentional trap handler so
 * risc-v-gsp-rm-debugger can demonstrate breakpoint/hook/watchpoint/trap workflows.
 *
 * Build: make -C firmware/uproc_demo
 */
OUTPUT_ARCH(riscv)
ENTRY(_start)

MEMORY
{
    RAM (rwxa) : ORIGIN = 0x80000000, LENGTH = 32M
}

SECTIONS
{
    . = 0x80000000;

    .text : ALIGN(4) {
        KEEP(*(.text.start))
        *(.text .text.*)
    } > RAM

    .rodata : ALIGN(8) {
        *(.rodata .rodata.*)
    } > RAM

    .data : ALIGN(8) {
        *(.data .data.*)
    } > RAM

    /* The control block gets its own section so its address is predictable. */
    .gsp_data : ALIGN(64) {
        KEEP(*(.gsp_data))
    } > RAM

    .bss : ALIGN(8) {
        *(.bss .bss.*)
        *(COMMON)
    } > RAM

    . = ALIGN(16);
    . += 0x4000;                /* 16 KiB stack */
    _stack_top = .;

    /DISCARD/ : {
        *(.comment)
        *(.note .note.*)
        *(.riscv.attributes)
    }
}