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# 34 — Blackwell sources and known-public parameters (planned / uncertain)
> **Status: planned, uncertain, do not implement.** Phase 3 (U10/U17) is
> gated behind the Phase 2 exit and a legal/source review
> (`handoff-simulator.md` §5, Phase 3). This document is a bibliography and
> a confidence-labelled parameter register only. It is **not** a model spec
> and must not be used to seed runnable configuration until Phase 3 entry.
>
> **Rules applied here:**
> * every number has a source and a confidence level;
> * values that are not public are written as **open questions** — never
> invented, interpolated or copied from a sibling architecture;
> * first-party NVIDIA publications outrank aggregators; where only an
> aggregator exists the row is labelled accordingly;
>
> **Confidence legend:** **A** = first-party NVIDIA publication (whitepaper,
> newsroom, datasheet, product page); **B** = first-party claim corroborated
> by at least one independent secondary source; **C** = secondary source only
> (aggregator/press, single-source or unverifiable against NVIDIA);
> **U** = unknown / not found — an explicit open question.
## 1. Bibliography
| # | Source | Type / URL |
|---|---|---|
| [RBW] | NVIDIA, *NVIDIA RTX Blackwell GPU Architecture* whitepaper (Jan 2025, v1.x) | First-party whitepaper, consumer GB20x. https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf |
| [B200-N] | NVIDIA Newsroom, *NVIDIA Blackwell Platform Arrives to Power a New Era of Computing* (GTC, Mar 2024) | First-party press release, B100/B200/GB200. https://nvidianews.nvidia.com/news/nvidia-blackwell-platform-arrives-to-power-a-new-era-of-computing |
| [GB200] | NVIDIA, *GB200 NVL72* product page | First-party product/spec page. https://www.nvidia.com/en-us/data-center/gb200-nvl72/ |
| [GB300] | NVIDIA, *GB300 NVL72* product page | First-party product/spec page. https://www.nvidia.com/en-us/data-center/gb300-nvl72/ |
| [SPARK] | NVIDIA, *NVIDIA DGX Spark* product page (Specifications section) | First-party product page, GB10. https://www.nvidia.com/en-us/products/workstations/dgx-spark/ |
| [SPARK-DS] | NVIDIA, *DGX Spark* datasheet (GTC 2025 spring) | First-party datasheet, GB10. https://nvdam.widen.net/s/tlzm8smqjx/workstation-datasheet-dgx-spark-gtc25-spring-nvidia-us-3716899-web |
| [CUDA-CC] | NVIDIA, *CUDA C Programming Guide* — compute capability 10.x / 12.x | First-party ISA/feature statement. https://docs.nvidia.com/cuda/cuda-c-programming-guide/ |
| [OCP-MX] | Open Compute Project, *OCP Microscaling Formats (MX) Specification v1.0* (2024) | Industry spec defining MXFP4/MXFP6. https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf |
| [MX-PAPER] | Rouhani et al., *Microscaling Data Formats for Deep Learning*, arXiv:2310.10537 (2023) | Published format analysis. |
| [WIKI-BW] | Wikipedia, *Blackwell (microarchitecture)* (retrieved 2026-10-03), citing TechPowerUp GPU database and AnandTech | Secondary aggregation; provenance for per-die core counts. https://en.wikipedia.org/wiki/Blackwell_(microarchitecture) |
## 2. Datacenter Blackwell (GB100 / B100 / B200 / GB200)
| Parameter | Value | Confidence | Source | Notes |
|---|---|---|---|---|
| Die | GB100, TSMC 4NP, reticle-limit size | A | [B200-N], [WIKI-BW] | |
| Transistors per die | 104 B | C | [WIKI-BW] (citing AnandTech) | NVIDIA does not headline a per-die count. |
| Package (B100/B200) | two GB100 dies, 208 B transistors total | A | [B200-N] | |
| Die-to-die link | 10 TB/s (NV-HBI) | A | [B200-N] | B200 acts as one unified GPU with cache coherency. |
| NVLink 5 per GPU | 1.8 TB/s bidirectional | A | [B200-N] | NVL72 supports up to 576 GPUs. |
| NVLink-C2C (GB200 → Grace CPU) | 900 GB/s | A | [B200-N] | "ultra-low-power NVLink chip-to-chip interconnect". |
| NVLink switch total (NVL72) | 130 TB/s | A | [GB300] (identical fabric class) | Cited on the GB300 page; GB200 NVL72 is the same 72-GPU fabric. |
| CUDA cores per die | 18,432 | C | [WIKI-BW] (TechPowerUp) | Not published by NVIDIA. |
| Tensor cores per die | 576 | C | [WIKI-BW] (TechPowerUp) | 4/die? No — per-die count not first-party; treat as unconfirmed. |
| L2 per die | 60 MB | C | [WIKI-BW] (TechPowerUp) | |
| Memory interface | 8,192-bit HBM3e per package | C | [WIKI-BW] | |
| B200 memory | 192 GB HBM3e, ~8 TB/s | B/C | widely reported; **not captured from a first-party page in this survey** | open question §5.1 |
| B100 memory | 192 GB HBM3e (variant differences open) | C | [WIKI-BW] | B100/B200 memory split varies by SKU; verify. |
| Compute capability | 10.x | A | [CUDA-CC] | |
| Low-precision formats | MXFP6, MXFP4 (OCP microscaling), FP8, INT8/INT4, binary | A | [B200-N] (Transformer Engine), [OCP-MX], [MX-PAPER] | 5th-gen tensor core with micro-tensor scaling. |
| FP4 performance | 20 PFLOPS (GB200 dual-GPU, excluding 2× sparsity claim) | A | [GB200] (as cited by [WIKI-BW]) | Per-GPU and per-die numbers need the technical brief; see §5.1. |
| Products | B100/B200 SXM, GB200 Grace-Blackwell superchip | A | [B200-N] | |
## 3. Consumer Blackwell (GB202 / GB203 / GB205, RTX 50 series)
All rows in this section are **[A]** from the RTX Blackwell whitepaper
unless noted; this is the **best-documented Blackwell part** and the natural
first Phase-3 target on the consumer side.
| Parameter | GB202 full | RTX 5090 | Source |
|---|---|---|---|
| GPCs / TPCs / SMs | 12 / 96 / 192 | 11 / 85 / 170 | [RBW] §GB202, Table 3 |
| CUDA cores / SM | 128 | 128 | [RBW] |
| CUDA cores / GPU | 24,576 | 21,760 | [RBW] |
| Tensor cores / SM / GPU | 4 (5th gen) / 768 | 4 (5th gen) / 680 | [RBW] Table 3 |
| RT cores | 192 (4th gen) | 170 (4th gen) | [RBW] |
| Register file / SM | 256 KB | 256 KB | [RBW] §SM |
| L1/shared per SM | 128 KB | 128 KB | [RBW] §SM |
| L2 | 128 MB | 96 MB | [RBW] §GB202 |
| Memory | 512-bit GDDR7 (16 × 32-bit MCs) | 32 GB GDDR7, 28 Gbps, 1,792 GB/s | [RBW] Table 3 |
| Boost clock | — | 2,407 MHz | [RBW] Table 3 |
| FP32 (non-tensor) | — | 104.8 TFLOPS | [RBW] Table 3 |
| FP16/BF16/INT32 (non-tensor) | — | 104.8 / 104.8 / 104.8 TFLOPS | [RBW] Table 3 (INT32 fully unified per SM) |
| FP4 tensor | — | 1,676 / 3,352 TFLOPS (non-sparse / sparse) | [RBW] Table 3 |
| FP8 tensor (FP16 acc) | — | 838 / 1,676 TFLOPS | [RBW] |
| FP16 tensor (FP16 acc) | — | 419 / 838 TFLOPS | [RBW] |
| FP16 tensor (FP32 acc) / BF16 | — | 209.5 / 419 TFLOPS | [RBW] |
| TF32 tensor | — | 104.8 / 209.5 TFLOPS | [RBW] |
| INT8 tensor | — | 838 / 1,676 TOPS | [RBW] |
| FP64 | — | 1/64 of FP32 rate, 384 FP64 cores (2/SM) on the full die | [RBW] §GB202 note | `[derived]` ≈ 1.64 TFLOPS for the full chip. |
| Transistors / die size | 92.2 B / 750 mm² | 92.2 B / 750 mm² | [RBW] Table 3 |
| TGP | — | 575 W | [RBW] Table 3 |
| SM changes | INT32 fully unified with FP32 (2× many integer ops; unified cores are either FP32 or INT32 per cycle); one 4th-gen RT core + four 5th-gen tensor cores per SM | | [RBW] §SM |
## 4. GB10 (Grace Blackwell superchip; DGX Spark class) and GB300
### 4.1 GB10
| Parameter | Value | Confidence | Source |
|---|---|---|---|
| CPU | 20-core Arm: 10 × Cortex-X925 + 10 × Cortex-A725 | A | [SPARK] |
| GPU | Blackwell architecture, 5th-gen tensor cores, 4th-gen RT cores | A | [SPARK] |
| Tensor performance | up to 1 PFLOP FP4 (theoretical, sparsity) | A | [SPARK], [SPARK-DS] |
| System memory | 64 GB (OEM) or 128 GB LPDDR5X, coherent unified | A | [SPARK], [SPARK-DS] |
| Memory interface / bandwidth | 256-bit / 273 GB/s | A | [SPARK], [SPARK-DS] |
| NVLink-C2C | "5× the bandwidth of PCIe Gen 5" (exact GB/s not stated) | A (ratio only) | [SPARK-DS] |
| Networking | ConnectX-7 200 Gb/s; up to 4 systems connected | A | [SPARK] |
| TDP | 140 W (GB10 chip, incl. CPU+GPU) | A | [SPARK] |
| SMs / CUDA cores | 48 SMs / 6,144 CUDA cores | C | [WIKI-BW] (TechPowerUp) |
| Tensor / RT cores | 384 / 48 | C | [WIKI-BW] |
| L1 / L2 | 6 MB / 50 MB | C | [WIKI-BW] |
| Compute capability | 12.x (consumer Blackwell family; confirm GB10 SKU) | U | — | open; see §5.2 |
### 4.2 GB300 / Blackwell Ultra
| Parameter | Value | Confidence | Source |
|---|---|---|---|
| Product | GB300 NVL72: 72 Blackwell Ultra GPUs + 36 Grace CPUs | A | [GB300] |
| FP4 dense uplift | 1.5× dense FP4 FLOPS vs Blackwell (GB200-class) | A | [GB300] |
| Attention performance | 2× higher attention vs Blackwell | A | [GB300] |
| NVLink fabric | 130 TB/s per rack | A | [GB300] |
| GPU memory (rack) | 20 TB HBM3e class ("Fast Memory 37 TB" total incl. CPU) | A | [GB300] table |
| HBM bandwidth (rack) | up to 576 TB/s aggregate | A | [GB300] table |
| CPU memory | 17 TB LPDDR5X, 14 TB/s | A | [GB300] |
| CPU cores | 2,592 Arm Neoverse V2 cores | A | [GB300] |
| Rack compute | FP4 1,440 / 1,080 PFLOPS (sparse / without sparsity); FP8-FP6 720 PFLOPS; INT8 24 POPS; FP16/BF16 360 PFLOPS; TF32 180 PFLOPS; FP32 6 PFLOPS; FP64 100 TFLOPS | A | [GB300] table |
| Per-GPU derived | 288 GB HBM3e, ~8 TB/s HBM, 20 PFLOPS FP4 sparse / 15 PFLOPS dense | B | `[derived]` from [GB300]: 20 TB ÷ 72 ≈ 278–288 GB (nominal 288 GB), 576 TB/s ÷ 72 = 8 TB/s, 1,440 ÷ 72 = 20 PFLOPS | mark derived; NVIDIA has separately quoted 288 GB per Blackwell Ultra GPU. |
| GPU clocks, SM counts, cache sizes | — | U | — | open; see §5.3 |
## 5. Open questions (explicit; never fill by invention)
### 5.1 GB100 / B200
1. Per-die SM count, CUDA/tensor core counts and per-SM composition are not
in a first-party public source found in this survey ([WIKI-BW] only).
2. HBM3e capacity/bandwidth per SKU (B100 vs B200, 192 GB vs other) needs
the NVIDIA Blackwell technical brief or product brief.
3. L2 organization/coherence across the two dies beyond "cache coherent"
([B200-N]) is unpublished.
4. NV-HBI latency/bandwidth characteristics beyond the 10 TB/s peak.
5. No per-instruction latency table exists for Blackwell comparable to
[AMP]/[T4]. A microbenchmark campaign (own or literature) is required
before any C1 claim.
### 5.2 GB10
6. Exact NVLink-C2C bandwidth in GB/s (only the "5× PCIe Gen 5" ratio is
first-party).
7. Whether GB10's compute capability is 12.0 or 12.x for the relevant SKU.
8. SM/core/cache counts are secondary-source only.
9. LPDDR5X timing and real achievable bandwidth (273 GB/s is the
first-party theoretical interface rate).
### 5.3 GB300 / Blackwell Ultra
10. Per-GPU clocks, SM counts, cache sizes and tensor shape/issue details.
11. Whether per-GPU HBM is exactly 288 GB on every SKU (the rack arithmetic
is approximate).
12. NVLink-C2C generation/bandwidth in GB300 (assume same class as GB200
only as a hypothesis, not a model input).
13. FP4/MXFP4 numerical semantics for simulation (block scaling, exponent
sharing) beyond the OCP spec.
### 5.4 Cross-cutting
14. A public **Hot Chips** presentation with GB100/GB202 microarchitecture
details was **not found** in this survey pass. If one exists (or is
released later), add it here with the exact deck title/URL — this is the
single highest-value missing source.
15. Blackwell memory-latency, sectoring, cp.async-successor semantics and
SM issue details are unpublished; Phase 3 must either measure locally
(supervised, hardware-permitting) or ship explicit uncertainty bands.
16. Blackwell datacenter firmware/boot material is out of scope here and
remains gated by the RM 610 no-fly zone (docs/23) — no 610 artifact may
be fetched or analysed for Phase 3 without the approval token.
## 6. What a Phase-3 smoke parameter set may and may not contain
* **May** use §3 rows (all first-party) as the consumer starting point, with
per-row uncertainty labels stored in the simulator session metadata.
* **May** use §2/§4 first-party *aggregate* claims as sanity bands.
* **May not** use any [C] row as a calibration target; [C] rows are leads to
verify, not values to fit.
* **May not** interpolate GB100 from GB202 or from Hopper; die topology,
clock domains and cache hierarchy are different designs.
* Any physical Blackwell capture is supervised-only and never an agent task
(RUNBOOK P4/P7); any firmware/BSP input obeys docs/23.
* Exit evidence for Phase 3 is defined in WP3.1–WP3.3: source dossier (this
document), an explicit uncertainty report, and a device profile — not an
accuracy claim.
## 7. Bibliography maintenance
Add to §1 whenever any of these appear: NVIDIA Blackwell technical brief
(datacenter), NVIDIA GB10/C2C technical brief, Hot Chips/ISSCC decks,
peer-reviewed Blackwell microbenchmarking papers, official CUDA PTX ISA
additions for `sm_100`/`sm_120` (e.g. tcgen05/5th-gen tensor instructions),
and OCP MX follow-ups. Keep [C] rows attached to their aggregator and
re-verify before promotion.
|
