From 2302fc09080bad51c73f293294e19fd4db464eb0 Mon Sep 17 00:00:00 2001 From: Open-IOV Date: Wed, 23 Sep 2026 05:44:08 -0400 Subject: Open-IOV: initial public release Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with real GPU functionality - CUDA first, 3D and video to follow - on unmodified hosts, without a proprietary vGPU license and without patching any driver, firmware or hypervisor. Core principle: emulate the interface, pass through the work. kernel/ open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device (PCI config space, BAR shadows, MSI-X), GSP boot emulation, GSP-RM message-queue/RPC emulation, memory model (GPU-VA to guest-PA discovery) and the semaphore-completion service that advances guest UVM progress. userspace/ libiov.so management API and examples. tools/ guest diagnostics, firmware analysis wrappers, RM probes. scripts/ stack manager, VM harness, build/load/test automation. config/ hardware/version profiles (the portability surface). docs/ documentation tree - start at docs/README.md. wiki/ long-form firmware and protocol deep dives. Status: initialization works end to end for a stock 570.144 Linux guest on Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery, object creation and the early CUDA/UVM start-up path. GPU work forwarding - the step that makes CUDA kernels execute on real hardware - is the active work item; see docs/04-implementation/01-known-knowns-and-unknowns.md. License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md. --- wiki/Address-Reference.md | 206 +++ wiki/BAR-Emulation-Specification.md | 321 ++++ wiki/Error-Codes.md | 198 +++ wiki/GPU_Driver_Internals.md | 1084 ++++++++++++ wiki/GPU_Firmware.md | 484 ++++++ wiki/GPU_SBOM.md | 258 +++ wiki/GSP-570.144W-Firmware-Analysis.md | 305 ++++ wiki/GSP-RPC-Emulation.md | 227 +++ wiki/Glossary.md | 163 ++ wiki/Migration-Protocol.md | 395 +++++ wiki/README.md | 21 + wiki/RPC-Message-Format.md | 316 ++++ wiki/Virtual_IO_Internals.md | 1736 ++++++++++++++++++++ wiki/WPR-Management.md | 288 ++++ wiki/open-iov.org/api.php?action=rsd | 1 + wiki/open-iov.org/favicon.ico.html | 245 +++ .../images/0/0b/Intel_GVT-g_Capabilities.png | Bin 0 -> 178799 bytes .../0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png | Bin 0 -> 46427 bytes .../1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png | Bin 0 -> 23772 bytes .../images/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png | Bin 0 -> 61809 bytes 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+| RPC Jump Table | 0x059BE7F4 | 4.9KB | 12 RPC type table | +| RPC Type Table | 0x059BFEB0 | — | Actual handler addresses | + +## Primary Dispatcher Sub-Commands (Jump Table at 0x057A3AD8) +| Subcmd | Target | Decompiled | +|--------|--------|------------| +| 0 | 0x057A1DB4 | ✅ | +| 1 | 0x057A1C18 | ✅ | +| 2 | 0x057A39FC | ✅ | +| 3 | 0x057A1BCC | ✅ | +| 4 | 0x057A1EF4 | ✅ | +| 5 | 0x057A1E94 | ✅ | +| 6 | 0x057A3A28 | ✅ | +| 7 | 0x057A3A60 | ✅ | +| 8 | 0x057A1C6C | ✅ | +| 9 | 0x057A3A48 | ✅ | +| 10 | 0x057A1F6C | ✅ | +| 11 | 0x057A3AC4 | ✅ | +| 12 | 0x057A1E10 | ✅ | +| 13 | 0x057A3A90 | ✅ | +| 14 | 0x057A39BC | ✅ | +| 15 | 0x057A3AAC | ✅ | +| 16 | 0x057A3A78 | ✅ | +| 17 | 0x057A1CCC | ✅ | +| 18 | 0x057A39E0 | ✅ | +| 19 | 0x057A1FA8 | ✅ | +| 20 | 0x057A2094 | ✅ | +| 21 | 0x057A2074 | ✅ | +| 22 | 0x057A2044 | ✅ | +| 23 | 0x057A20D4 | ✅ | +| 24 | 0x057A20B4 | ✅ | +| 25 | 0x057A1FC8 | ✅ | +| 26 | 0x057A2008 | ✅ | +| 27 | 0x057A1FE8 | ✅ | +| 28 | 0x057A2024 | ✅ | +| 29 | 0x057A219C | ✅ | +| 30 | 0x057A20FC | ✅ | +| 31 | 0x057A214C | ✅ | + +## Migration Jump Tables +### Table 1: 0x04179ED8 (MIGRATE branch at 0x057A1BDC) +| Index | Target | Decompiled | +|-------|--------|------------| +| 0 | 0x057A2344 | ✅ | +| 1 | 0x057A2320 | ✅ | +| 2 | 0x057A230C | ✅ | +| 3 | 0x057A22F8 | ✅ | +| 4 | 0x057A2388 | ✅ | +| 5 | 0x057A23D8 | ✅ | +| 6 | 0x057A23AC | ✅ | +| 7 | 0x057A2478 | ✅ | +| 8 | 0x057A2428 | ✅ | +| 9 | 0x057A2454 | ✅ | +| 10 | 0x057A2404 | ✅ | +| 11 | 0x057A2364 | ✅ | +| 12 | 0x057A1F3C | (dup) | +| 13 | 0x057A299C | — | +| 14 | 0x057A1F3C | (dup) | +| 15 | 0x057A1F3C | (dup) | + +### Table 2: 0x04179FBC (MIGRATE branch at 0x057A1D5C) +| Index | Target | Decompiled | +|-------|--------|------------| +| 0 | 0x057A257C | ✅ | +| 1 | 0x057A25E4 | ✅ | +| 2 | 0x057A24EC | ✅ | +| 3 | 0x057A2608 | ✅ | +| 4 | 0x057A2534 | ✅ | +| 5 | 0x057A25C0 | ✅ | +| 6 | 0x057A24A4 | ✅ | +| 7 | 0x057A259C | ✅ | +| 8 | 0x057A2510 | ✅ | +| 9 | 0x057A2558 | ✅ | +| 10 | 0x057A24C8 | ✅ | +| 11 | 0x057A262C | ✅ | +| 12 | 0x057A345C | ✅ | +| 13 | 0x057A36D8 | ✅ | +| 14 | 0x057A35D8 | ✅ | +| 15 | 0x057A3658 | ✅ | + +## RPC Handlers (from Jump Table at 0x059BFEB0) +| RPC Type | Name | Handler A | Handler B | +|----------|------|-----------|-----------| +| 0x01 | ALLOC | — | — | +| 0x02 | FREE | — | — | +| 0x03 | MAP | 0x05766AB7 | 0x05778A37 | +| 0x04 | UNMAP | 0x057669B7 | 0x05779937 | +| 0x05 | PIN | 0x057664B7 | 0x0577A3B7 | +| 0x06 | UNPIN | 0x057682B7 | 0x05779FB7 | +| 0x07 | SCHEDULE | 0x05767F37 | 0x0575AEB7 | +| 0x08 | YIELD | 0x0575AE37 | 0x05767337 | +| 0x09 | NOTIFY | 0x0577C8B7 | 0x05767837 | +| 0x0A | BAR_TRAP | 0x057675B7 | — | +| 0x0B | MIGRATE | — | — | +| 0x0C | DEBUG | — | — | + +## Specialized Main Handlers +| Function | Address | Size | +|----------|---------|------| +| `rpc_alloc_main` | 0x057E94EC | 40 KB | +| `rpc_schedule_main` | 0x051EFBF4 | 1.8 KB | +| `rpc_bar_trap_handler` | 0x04CB8188 | 40 KB | +| `rpc_pin_handler` | 0x04ED34B8 | — | + +## WPR Handlers +| Handler | Address | Size | +|---------|---------|------| +| WPR Handler 1 | 0x04F00B0C | 62 KB | +| WPR Handler 2 | 0x04F00C78 | 62 KB | + +## Memory & Global State +| Symbol | Address | Description | +|--------|---------|-------------| +| Global Error Flag | 0x04296048 | `cRam0000000004296048` | +| Error Status Reg | 0x0429B750+0x111300 | Error register | +| Stack Canary | 0x041DC350 | Frame guard value | +| Allocator Arena | 0x429B000 | Base | +| Allocator Entry | 0x429B450 | `UNK_ram_058A1A9C` | +| Cache Manager | 0x429B428 | `UNK_ram_05895BF4` | + +## String References + +### BAR Strings +| String | Address | +|--------|---------| +| BAR1 | 0x0406570E, 0x04085DE0 | +| Bar1Rest | 0x040656DA | +| ForceBarAccess | 0x040656F2 | +| Bar1Aperture | 0x04065722 | +| Bar1Size | (referenced) | + +### WPR Strings +| String | Address | +|--------|---------| +| WPR_WRITE_COMPLETE | 0x5E478F8 | +| WPR_READ_COMPLETE | 0x5E478E0 | +| WPR_WRITE_TIMEOUT | 0x5E47898 | +| WPR_READ_TIMEOUT | 0x5E47880 | +| NV_WPR_WRITE_COMPLETE | 0x5E478C8 | +| NV_WPR_READ_COMPLETE | 0x5E478B0 | +| NV_WPR_WRITE_TIMEOUT | 0x5E47868 | +| NV_WPR_READ_TIMEOUT | 0x5E47850 | + +### VBIOS Signatures +| Signature | Value | Meaning | +|-----------|-------|---------| +| VBIOS Standard | 0xAA55 | VBIOS header | +| WPR Enable | 0x57464F4E ("WFON") | WPR on | +| WPR Version | 0x5746564E ("WFVN") | WPR version | + +## Key Function Pointers (Indirect Calls) +| Address | Function | Purpose | +|---------|----------|---------| +| 0x05AB7DA0 | Logger | String logging | +| 0x05AC4B7C | Stack unwind | Frame recovery | +| 0x058A1A9C | Allocator | Memory alloc | +| 0x05895BF4 | Cache flush | Cache management | +| 0x0588F9C4 | DMA copy | Memory copy | +| 0x05AEC86C | Memory read | Read from addr | +| 0x05AE1430 | Size query | Region size | +| 0x05AF4D30 | Page fault | Page fault handler | +| 0x05B10C3C | Page map | Page mapping | +| 0x05AE9A2C | Crypto/verify | Integrity check | +| 0x05AED674 | WPR check | WPR validation | +| 0x05AED430 | WPR emulate | WPR emulation | +| 0x05CB30CC | Config read | Config access | +| 0x05CB25E0 | BAR config | BAR configuration | +| 0x05CB23D8 | BAR map | BAR mapping | + +## Decompiled Output Files +All files in: `$OPEN_IOV_ROOT/firmware/570-GSP/decompiled/` + +| Category | Files | +|----------|-------| +| Core | entry_ram_04009000.c, FUN_ram_057a1ac0_ram_057a1ac0.c | +| Sub-commands | FUN_ram_057a1bcc_ram_057a1bcc.c ... FUN_ram_057a214c_ram_057a214c.c (32) | +| Dispatchers | FUN_ram_04cc58f8_ram_04cc58f8.c, FUN_ram_04ed39dc_ram_04ed39dc.c, FUN_ram_05723ef4_ram_05723ef4.c | +| RPC Jump Table | FUN_ram_059be7f4_ram_059be7f4.c | +| BAR | FUN_ram_04cb8188_ram_04cb8188.c | +| WPR | FUN_ram_04f00b0c_ram_04f00b0c.c, FUN_ram_04f00c78_ram_04f00c78.c | +| ALLOC | FUN_ram_057e94ec_ram_057e94ec.c, FUN_ram_04d00a18_ram_04d00a18.c, FUN_ram_054a7de0_ram_054a7de0.c | +| SCHEDULE | FUN_ram_051efbf4_ram_051efbf4.c | +| RPC Handlers | FUN_ram_057664b7_ram_057664b7.c ... FUN_ram_0577c8b7_ram_0577c8b7.c (15) | +| Migration | FUN_ram_057a22f8_ram_057a22f8.c ... FUN_ram_057a3658_ram_057a3658.c (28) | + +## Migration Sub-Command Descriptors (Sample) +| Handler | Returned ID | Phase | +|---------|-------------|-------| +| 0x057A22F8 | 0x10 | Prepare | +| 0x057A2344 | 0x14 | Prepare | +| Others | TBD | Transfer/Commit | \ No newline at end of file diff --git a/wiki/BAR-Emulation-Specification.md b/wiki/BAR-Emulation-Specification.md new file mode 100644 index 0000000..b8a46c3 --- /dev/null +++ b/wiki/BAR-Emulation-Specification.md @@ -0,0 +1,321 @@ +# BAR Emulation Specification (GSP 570.144W) + +## Overview +The GSP firmware implements BAR (Base Address Register) emulation for virtual GPU (vGPU) through the **BAR_TRAP** RPC (type 0x0A). The main handler at **0x04CB8188** (40 KB) manages BAR1 aperture, forced access, and memory backing. + +## Key Addresses + +| Component | Address | Description | +|-----------|---------|-------------| +| BAR Trap Handler | 0x04CB8188 | Main emulation logic (40 KB) | +| RPC Jump Table Entry | 0x057675B7 | BAR_TRAP in secondary dispatcher | +| String: BAR1 | 0x0406570E, 0x04085DE0 | BAR1 identifier | +| String: Bar1Rest | 0x040656DA | BAR1 restore state | +| String: ForceBarAccess | 0x040656F2 | Forced access control | +| String: Bar1Aperture | 0x04065722 | Aperture configuration | +| Memory Allocator | 0x429B450 | Arena for BAR backing store | +| Cache Management | 0x429B428 | Flush/invalidate | + +## Handler State Machine + +### Main Loop (0x04CB8188) +The handler runs a continuous event loop processing BAR trap requests: + +```c +while (true) { + // Wait for trap event (bitmask in unaff_s5) + event = wait_for_bar_event(); + + switch (event & 0x3F) { + case 0x01: // BAR1 write access + handle_bar1_write(); + break; + case 0x02: // BAR1 read access + handle_bar1_read(); + break; + case 0x08: // Aperture configuration + handle_aperture_config(); + break; + case 0x10: // ForceBarAccess + handle_force_access(); + break; + case 0x20: // Bar1Rest (restore) + handle_bar1_restore(); + break; + default: + return ERROR_UNKNOWN_EVENT; + } +} +``` + +### Event Bitmask +| Bit | Event | Description | +|-----|-------|-------------| +| 0 | BAR1_WRITE | Guest VF wrote to BAR1 | +| 1 | BAR1_READ | Guest VF read from BAR1 | +| 3 | APERTURE | Aperture size/offset change | +| 4 | FORCE_ACCESS | ForceBarAccess triggered | +| 5 | BAR1_REST | Restore BAR1 state | + +## Memory Management + +### Allocator Arena (0x429B450) +```c +// Allocate backing store for BAR emulation +void *bar_alloc(size_t size) { + // Calls UNK_ram_058A1A9C(0x429B450, size) + // Returns pointer in 0x429B000 region +} + +// Free backing store +void bar_free(void *ptr) { + // Calls UNK_ram_05895BF4(0x429B428, ptr) +} +``` + +### Allocation Sizes +- **Standard BAR1 page**: 0x1000 (4 KB) +- **Aperture buffer**: 0x40000 (256 KB) max +- **Force access buffer**: 0x1000 (4 KB) + +### Cache Coherency +```c +// Flush cache for DMA +void bar_cache_flush(void *addr, size_t size) { + UNK_ram_05895BF4(0x429B428, addr); + UNK_ram_05895BF4(0x429B428, addr + size); +} +``` + +## BAR1 Emulation Logic + +### Write Path (Event 0x01) +```c +int handle_bar1_write(bar_trap_t *trap) { + // 1. Validate offset within aperture + if (trap->offset >= bar1_aperture_size) + return ERROR_OVERFLOW; + + // 2. Check ForceBarAccess flag + if (force_bar_access && !(trap->flags & FORCE_ALLOWED)) + return ERROR_PERMISSION; + + // 3. Translate to backing store + uint8_t *backing = bar1_backing + trap->offset; + + // 4. Perform write (1/2/4/8 bytes) + switch (trap->size) { + case 1: *backing = trap->value; break; + case 2: *(uint16_t*)backing = trap->value; break; + case 4: *(uint32_t*)backing = trap->value; break; + case 8: *(uint64_t*)backing = trap->value; break; + } + + // 5. Flush to device if needed + if (device_needs_flush) + bar_cache_flush(backing, trap->size); + + return OK; +} +``` + +### Read Path (Event 0x02) +```c +int handle_bar1_read(bar_trap_t *trap) { + if (trap->offset >= bar1_aperture_size) + return ERROR_OVERFLOW; + + uint8_t *backing = bar1_backing + trap->offset; + + switch (trap->size) { + case 1: *trap->out_value = *backing; break; + case 2: *trap->out_value = *(uint16_t*)backing; break; + case 4: *trap->out_value = *(uint32_t*)backing; break; + case 8: *trap->out_value = *(uint64_t*)backing; break; + } + + return OK; +} +``` + +### Aperture Configuration (Event 0x08) +```c +int handle_aperture_config(bar_config_t *cfg) { + // Validate new aperture + if (cfg->size > MAX_APERTURE_SIZE) // 0x40000 + return ERROR_INVALID; + + if (cfg->offset & 0xFFF) // Must be 4KB aligned + return ERROR_ALIGNMENT; + + // Reallocate backing store if size changed + if (cfg->size != bar1_aperture_size) { + void *new_backing = bar_alloc(cfg->size); + if (!new_backing) return ERROR_NOMEM; + + // Copy existing data + memcpy(new_backing, bar1_backing, + min(cfg->size, bar1_aperture_size)); + + bar_free(bar1_backing); + bar1_backing = new_backing; + bar1_aperture_size = cfg->size; + } + + bar1_aperture_offset = cfg->offset; + return OK; +} +``` + +### ForceBarAccess (Event 0x10) +```c +int handle_force_access(force_access_t *fa) { + // ForceBarAccess allows hypervisor to bypass VF permissions + // Used for live migration, checkpoint/restore + + force_bar_access = fa->enable; + force_access_vf = fa->vf_id; + force_access_range = fa->range; + + // Allocate shadow buffer for forced operations + if (fa->enable) { + force_buffer = bar_alloc(0x1000); + if (!force_buffer) return ERROR_NOMEM; + } else { + bar_free(force_buffer); + force_buffer = NULL; + } + + return OK; +} +``` + +### Bar1Rest - State Restore (Event 0x20) +```c +int handle_bar1_restore(restore_state_t *rs) { + // Restore BAR1 state from checkpoint + // Used during VF live migration + + bar1_aperture_offset = rs->aperture_offset; + bar1_aperture_size = rs->aperture_size; + force_bar_access = rs->force_access; + + // Restore backing store from serialized data + if (rs->backing_size > 0) { + void *new_backing = bar_alloc(rs->backing_size); + if (!new_backing) return ERROR_NOMEM; + + memcpy(new_backing, rs->backing_data, rs->backing_size); + bar_free(bar1_backing); + bar1_backing = new_backing; + } + + return OK; +} +``` + +## vGPU-IO Integration + +### Kernel BAR Trap Registration +```c +struct gsp_bar_ops { + int (*bar_trap)(struct gsp_device *gsp, + struct bar_trap_msg *msg); + int (*configure_aperture)(struct gsp_device *gsp, + uint32_t vf_id, + uint64_t offset, uint64_t size); + int (*force_access)(struct gsp_device *gsp, + uint32_t vf_id, bool enable); + int (*save_state)(struct gsp_device *gsp, + uint32_t vf_id, void *buf, size_t *size); + int (*restore_state)(struct gsp_device *gsp, + uint32_t vf_id, void *buf, size_t size); +}; + +static const struct gsp_bar_ops gsp_bar_ops = { + .bar_trap = gsp_bar_trap_handler, + .configure_aperture = gsp_bar_config_aperture, + .force_access = gsp_bar_force_access, + .save_state = gsp_bar_save_state, + .restore_state = gsp_bar_restore_state, +}; +``` + +### VF BAR Configuration +```c +int gsp_vf_bar_init(struct gsp_vf *vf) { + struct bar_config cfg = { + .vf_id = vf->id, + .bar = 1, // BAR1 + .aperture_offset = vf->bar1_offset, + .aperture_size = vf->bar1_size, + .flags = BAR_FLAG_COHERENT, + }; + + return gsp_rpc_send(vf->gsp, RPC_BAR_TRAP, + BAR_SUBCMD_CONFIG, &cfg, sizeof(cfg)); +} +``` + +### Live Migration Support +```c +// Save BAR state for migration +int gsp_vf_bar_save(struct gsp_vf *vf, void *buf, size_t *size) { + struct bar_save_msg msg = { + .vf_id = vf->id, + .bar = 1, + }; + + return gsp_rpc_send(vf->gsp, RPC_BAR_TRAP, + BAR_SUBCMD_SAVE, &msg, sizeof(msg), + buf, size); +} + +// Restore BAR state on destination +int gsp_vf_bar_restore(struct gsp_vf *vf, void *buf, size_t size) { + struct bar_restore_msg msg = { + .vf_id = vf->id, + .bar = 1, + .data = buf, + .data_size = size, + }; + + return gsp_rpc_send(vf->gsp, RPC_BAR_TRAP, + BAR_SUBCMD_RESTORE, &msg, sizeof(msg)); +} +``` + +## Error Handling + +| Error | Code | Recovery | +|-------|------|----------| +| OOM (0x51) | Allocator exhausted | Shrink aperture, retry | +| Timeout (0x1E) | Cache flush timeout | Reset BAR, reinitialize | +| Invalid (0x1F) | Bad aperture config | Validate alignment/size | +| Permission (0xFFFF) | ForceAccess violation | Check VF permissions | +| Overflow (0x25) | Offset beyond aperture | Bounds check in VF driver | + +## Debugging + +### Key Registers to Monitor +``` +0x04296048 : Global error flag (cRam0000000004296048) +0x0429B750 : Error status (0x111300 offset) +0x429B428 : Cache management base +0x429B450 : Allocator arena base +``` + +### Log Strings +Search for these in GSP logs: +- `BAR1` - BAR1 access +- `Bar1Rest` - State restore +- `ForceBarAccess` - Forced access +- `Bar1Aperture` - Aperture changes +- `Bar1Size` - Size queries + +--- + +## Reference +- Handler: `FUN_ram_04cb8188_ram_04cb8188.c` (40 KB) +- RPC Type: 0x0A (BAR_TRAP) +- Jump Table Entry: 0x057675B7 \ No newline at end of file diff --git a/wiki/Error-Codes.md b/wiki/Error-Codes.md new file mode 100644 index 0000000..c61da06 --- /dev/null +++ b/wiki/Error-Codes.md @@ -0,0 +1,198 @@ +# GSP Error Codes + +## Standard POSIX Errors (Negative Return Values) + +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0 | 0x00000000 | OK | Success | +| -1 | 0xFFFFFFFF | EPERM | Operation not permitted | +| -2 | 0xFFFFFFFE | ENOENT | No such file/entry | +| -3 | 0xFFFFFFFD | EINVAL | Invalid argument | +| -6 | 0xFFFFFFFA | ENODEV | No such device | +| -12 | 0xFFFFFFF4 | ENOMEM | Out of memory | +| -16 | 0xFFFFFFEE | EBUSY | Device/resource busy | +| -22 | 0xFFFFFFEA | EINVAL | Invalid argument | +| -28 | 0xFFFFFFE4 | ENOSPC | No space left on device | +| -37 | 0xFFFFFFDB | ENOLCK | No locks available | +| -56 | 0xFFFFFFC8 | EBADMSG | Bad message | +| -84 | 0xFFFFFFAC | EOVERFLOW | Value too large | +| -90 | 0xFFFFA6 | ENOSTR | Not a stream | +| -91 | 0xFFFFA5 | ENODATA | No data available | +| -94 | 0xFFFFA2 | ENOSR | Out of streams resources | +| -97 | 0xFFFFFF9F | EPROTO | Protocol error | +| -111 | 0xFFFFFF91 | ETIMEDOUT | Connection timed out | + +## GSP-Specific Error Codes (Observed in Firmware) + +### Memory Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x1E | 0x0000001E | ETIME | WPR/RPC timeout | +| 0x1F | 0x0000001F | EDEV | Device error | +| 0x25 | 0x00000025 | EOVERFLOW | Region/offset overflow | +| 0x37 | 0x00000037 | EINVAL | Invalid alignment/size | +| 0x51 | 0x00000051 | ENOMEM | Allocator exhausted | +| 0x56 | 0x00000056 | EBUSY | Resource busy | +| 0xFFFF | 0xFFFFFFFF | EPERM | Permission denied | + +### RPC Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x1D | 0x0000001D | EFAULT | Bad address in RPC | +| 0x1E | 0x0000001E | ETIMEDOUT | RPC timeout | +| 0x1F | 0x0000001F | EPROTO | Protocol violation | +| 0x20 | 0x00000020 | EBADRPC | Invalid RPC type | +| 0x21 | 0x00000021 | EBADSEQ | Sequence mismatch | +| 0x22 | 0x00000022 | EBADSIZE | Payload size error | + +### BAR Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x30 | 0x00000030 | EBARINVAL | Invalid BAR index | +| 0x31 | 0x00000031 | EBARPERM | BAR access denied | +| 0x32 | 0x00000032 | EBARSIZE | Aperture size error | +| 0x33 | 0x00000033 | EBARALIGN | Alignment error | +| 0x34 | 0x00000034 | EBARRANGE | Offset out of range | +| 0x35 | 0x00000035 | EBARBUSY | BAR busy | + +### WPR Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x40 | 0x00000040 | EWPRINVAL | Invalid WPR region | +| 0x41 | 0x00000041 | EWPRPERM | WPR permission denied | +| 0x42 | 0x00000042 | EWPROVERLAP | Overlapping WPR regions | +| 0x43 | 0x00000043 | EWPRBUSY | WPR operation in progress | +| 0x44 | 0x00000044 | EWPRTIMEOUT | WPR timeout | + +### Migration Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x50 | 0x00000050 | EMIGINVAL | Invalid migration phase | +| 0x51 | 0x00000051 | EMIGNOMEM | Migration buffer OOM | +| 0x52 | 0x00000052 | EMIGBUSY | Migration in progress | +| 0x53 | 0x00000053 | EMIGPHASE | Phase mismatch | +| 0x54 | 0x00000054 | EMIGVERIFY | Verification failed | +| 0x55 | 0x00000055 | EMIGCOMMIT | Commit failed | +| 0x56 | 0x00000056 | EMIGABORT | Migration aborted | + +### Scheduler Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x60 | 0x00000060 | ESCHINVAL | Invalid schedule params | +| 0x61 | 0x00000061 | ESCHPRIO | Priority error | +| 0x62 | 0x00000062 | ESCHYIELD | Yield failed | +| 0x63 | 0x00000063 | ESCHPREEMPT | Preemption error | + +### Notification Errors +| Code | Hex | Name | Description | +|------|-----|------|-------------| +| 0x70 | 0x00000070 | ENOTIFYINVAL | Invalid notification | +| 0x71 | 0x00000071 | ENOTIFYBUSY | Notification queue full | +| 0x72 | 0x00000072 | ENOTIFYDROP | Notification dropped | + +## Error Code Mapping (Kernel Driver) + +```c +static int gsp_errno_to_errno(int gsp_err) { + switch (gsp_err) { + case 0: return 0; + case -1: return -EPERM; + case -2: return -ENOENT; + case -3: return -EINVAL; + case -6: return -ENODEV; + case -12: return -ENOMEM; + case -16: return -EBUSY; + case -22: return -EINVAL; + case -28: return -ENOSPC; + case -37: return -ENOLCK; + case -56: return -EBADMSG; + case -84: return -EOVERFLOW; + case -90: return -ENOSTR; + case -91: return -ENODATA; + case -94: return -ENOSR; + case -97: return -EPROTO; + case -111: return -ETIMEDOUT; + + // GSP-specific + case 0x1E: return -ETIMEDOUT; + case 0x1F: return -EIO; + case 0x25: return -EOVERFLOW; + case 0x37: return -EINVAL; + case 0x51: return -ENOMEM; + case 0x56: return -EBUSY; + case 0xFFFF: return -EPERM; + + // BAR + case 0x30: return -EINVAL; + case 0x31: return -EPERM; + case 0x32: return -EINVAL; + case 0x33: return -EINVAL; + case 0x34: return -ERANGE; + case 0x35: return -EBUSY; + + // WPR + case 0x40: return -EINVAL; + case 0x41: return -EPERM; + case 0x42: return -EEXIST; + case 0x43: return -EBUSY; + case 0x44: return -ETIMEDOUT; + + // Migration + case 0x50: return -EINVAL; + case 0x51: return -ENOMEM; + case 0x52: return -EBUSY; + case 0x53: return -EINVAL; + case 0x54: return -EIO; + case 0x55: return -EIO; + case 0x56: return -ECANCELED; + + // Scheduler + case 0x60: return -EINVAL; + case 0x61: return -EINVAL; + case 0x62: return -EAGAIN; + case 0x63: return -EAGAIN; + + // Notification + case 0x70: return -EINVAL; + case 0x71: return -EAGAIN; + case 0x72: return -ENOBUFS; + + default: return -EIO; + } +} +``` + +## Debugging Error Codes + +### GSP Log Format +``` +GSP_ERROR: rpc_type=0x0A seq=0x1234 err=0x31 (EBARPERM) vf=2 addr=0x7F000000 +``` + +### Common Error Scenarios + +| Scenario | Error Code | Resolution | +|----------|------------|------------| +| VF writes to unmapped BAR | 0x31 (EBARPERM) | Check VF BAR config | +| Migration verify fails | 0x54 (EMIGVERIFY) | Check memory integrity | +| WPR timeout on page fault | 0x44 (EWPRTIMEOUT) | Increase timeout | +| RPC sequence mismatch | 0x21 (EBADSEQ) | Reset RPC client | +| Allocator exhausted | 0x51 (ENOMEM) | Free unused VF memory | +| BAR aperture too small | 0x32 (EBARSIZE) | Increase aperture | + +### Error Injection (Testing) +```c +// Inject errors for testing +#define GSP_INJECT_ERROR(rpc_type, err_code) \ + gsp_test_inject_error(gsp, rpc_type, err_code) + +void gsp_test_inject_error(struct gsp_device *gsp, + uint32_t rpc_type, int err_code) { + struct inject_payload p = { + .rpc_type = rpc_type, + .error_code = err_code, + .enable = 1, + }; + gsp_rpc_send_sync(gsp->rpc, RPC_DEBUG, &p, sizeof(p), NULL, NULL); +} +``` \ No newline at end of file diff --git a/wiki/GPU_Driver_Internals.md b/wiki/GPU_Driver_Internals.md new file mode 100644 index 0000000..4c18fca --- /dev/null +++ b/wiki/GPU_Driver_Internals.md @@ -0,0 +1,1084 @@ +::: {#mw-page-base .noprint} +::: + +::: {#mw-head-base .noprint} +::: + +::: {#content .mw-body role="main"} +[]{#top} + +::: {#siteNotice} +::: + +::: mw-indicators +::: + +# GPU Driver Internals {#firstHeading .firstHeading} + +::: {#bodyContent .vector-body} +::: {#siteSub .noprint} +From Open-IOV +::: + +::: {#contentSub} +::: {.mw-revision .warningbox} +::: {#mw-revision-info} +Revision as of 17:53, 19 June 2023 by +[Arthur](./index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html "User:Arthur (page does not exist)"){.new +.mw-userlink} +[([talk](./index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html "User talk:Arthur (page does not exist)"){.new +.mw-usertoollinks-talk} \| +[contribs](index.php/Special:Contributions/Arthur.html "Special:Contributions/Arthur"){.mw-usertoollinks-contribs})]{.mw-usertoollinks} +[([[[→‎References (Talks & Reading +Material)](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#References_(Talks_&_Reading_Material))]{.autocomment}]{dir="auto"})]{.comment} +::: + +::: {#mw-revision-nav} +([diff](https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23791 "GPU Driver Internals")) +[← Older +revision](https://open-iov.org/index.php?title=GPU_Driver_Internals&direction=prev&oldid=23791 "GPU Driver Internals") +\| Latest revision (diff) \| Newer revision → (diff) +::: +::: +::: + +::: {#contentSub2} +::: + +::: {#jump-to-nav} +::: + +[Jump to +navigation](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#mw-head){.mw-jump-link} +[Jump to +search](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#searchInput){.mw-jump-link} + +::: {#mw-content-text .mw-body-content .mw-content-ltr lang="en" dir="ltr"} +::: mw-parser-output +This page will detail the internals of various GPU drivers for use with +I/O Virtualization. + +> An absence of critical technical documentation has historically slowed +> growth and adoption of developer ecosystems for GPU virtualization. +> +> This +> [CC-BY-4.0](https://creativecommons.org/licenses/by/4.0/){.external +> .text rel="nofollow"} licensed content can either be used with +> attribution, or used as inspiration for new documentation, created by +> GPU vendors for public commercial distribution as developer +> documentation. +> +> Where possible, this documentation will clearly label dates and +> versions of observed-but-not-guaranteed behaviour vs. +> vendor-documented stable interfaces/behaviour with guarantees of +> forward or backward compatibility. + +::: {#toc .toc role="navigation" aria-labelledby="mw-toc-heading"} +::: {.toctitle lang="en" dir="ltr"} +## Contents {#mw-toc-heading} + +[]{.toctogglespan} +::: + +- [[1]{.tocnumber} [Article + Structure]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Article_Structure) + - [[1.1]{.tocnumber} [High Level + Architecture]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#High_Level_Architecture) + - [[1.2]{.tocnumber} + [Initialization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Initialization) + - [[1.3]{.tocnumber} + [Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Scheduling) + - [[1.3.1]{.tocnumber} [In-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#In-VM_Scheduling) + - [[1.3.2]{.tocnumber} [Between-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Between-VM_Scheduling) + - [[1.3.3]{.tocnumber} [Firmware Scheduling (if + applicable)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Firmware_Scheduling_(if_applicable)) + - [[1.4]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Memory_Management) + - [[1.5]{.tocnumber} [Display Surface + Virtualization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Display_Surface_Virtualization) + - [[1.5.1]{.tocnumber} [Graphics Buffer + Sharing]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Graphics_Buffer_Sharing) +- [[2]{.tocnumber} [Vendor + Neutral]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Vendor_Neutral) + - [[2.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Knowledge_Resources_Used) + - [[2.2]{.tocnumber} [Display Surface + Virtualization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Display_Surface_Virtualization_2) + - [[2.2.1]{.tocnumber} [Graphics Buffer + Sharing]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Graphics_Buffer_Sharing_2) + - [[2.2.1.1]{.tocnumber} [Display Flow in + Linux]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Display_Flow_in_Linux) + - [[2.2.1.2]{.tocnumber} [SR-IOV and + Mdev]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#SR-IOV_and_Mdev) + - [[2.2.1.3]{.tocnumber} [VFs in QEMU Hypervisor + (VirtIO-GPU)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#VFs_in_QEMU_Hypervisor_(VirtIO-GPU)) + - [[2.2.1.4]{.tocnumber} + [Transport]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Transport) + - [[2.2.1.4.1]{.tocnumber} [QEMU Host-Side + u-dma-buf]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#QEMU_Host-Side_u-dma-buf) + - [[2.2.1.4.2]{.tocnumber} [QEMU Host-Side + Modules]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#QEMU_Host-Side_Modules) + - [[2.2.1.5]{.tocnumber} [Windows + VFs]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Windows_VFs) + - [[2.2.1.6]{.tocnumber} [Windows Driver + Stack]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Windows_Driver_Stack) + - [[2.2.1.7]{.tocnumber} [DVServer + KMD]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#DVServer_KMD) + - [[2.2.1.8]{.tocnumber} [Android + VFs]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Android_VFs) +- [[3]{.tocnumber} + [i915]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#i915) + - [[3.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Knowledge_Resources_Used_2) + - [[3.2]{.tocnumber} [High Level + Architecture]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#High_Level_Architecture_2) + - [[3.2.1]{.tocnumber} [i915 + Clients]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#i915_Clients) + - [[3.3]{.tocnumber} + [Initialization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Initialization_2) + - [[3.4]{.tocnumber} + [Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Scheduling_2) + - [[3.4.1]{.tocnumber} [In-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#In-VM_Scheduling_2) + - [[3.4.2]{.tocnumber} [Guest kernel + (i915.ko)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Guest_kernel_(i915.ko)) + - [[3.4.2.1]{.tocnumber} + [vExeclist]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#vExeclist) + - [[3.4.2.2]{.tocnumber} + [vGuC]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#vGuC) + - [[3.4.3]{.tocnumber} [Between-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Between-VM_Scheduling_2) + - [[3.4.3.1]{.tocnumber} [Host kernel + (i915.ko)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Host_kernel_(i915.ko)) + - [[3.4.3.1.1]{.tocnumber} + [Execlist]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Execlist) + - [[3.4.3.1.2]{.tocnumber} + [GuC]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#GuC) + - [[3.4.3.2]{.tocnumber} [Device Firmware + (GuC)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Device_Firmware_(GuC)) + - [[3.5]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Memory_Management_2) + - [[3.5.1]{.tocnumber} [Translation + Tables]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Translation_Tables) + - [[3.5.1.1]{.tocnumber} [GTT (Graphics Translation + Table)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#GTT_(Graphics_Translation_Table)) + - [[3.5.1.2]{.tocnumber} [GGTT (Global Graphics + Translation + Table)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#GGTT_(Global_Graphics_Translation_Table)) + - [[3.5.1.3]{.tocnumber} [PPGTT (Per Process Graphics + Translation + Table)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#PPGTT_(Per_Process_Graphics_Translation_Table)) + - [[3.5.1.4]{.tocnumber} [Aliasing + PPGTT]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Aliasing_PPGTT) + - [[3.5.1.5]{.tocnumber} [Real + PPGTT]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Real_PPGTT) + - [[3.6]{.tocnumber} [Display Surface + Virtualization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Display_Surface_Virtualization_3) + - [[3.6.1]{.tocnumber} + [VirtIO-GPU]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#VirtIO-GPU) + - [[3.6.2]{.tocnumber} [IDD (Indirect Display + Driver)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#IDD_(Indirect_Display_Driver)) + - [[3.6.3]{.tocnumber} [Graphics Buffer + Sharing]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Graphics_Buffer_Sharing_3) +- [[4]{.tocnumber} + [OpenRM]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#OpenRM) + - [[4.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Knowledge_Resources_Used_3) + - [[4.2]{.tocnumber} [High Level + Architecture]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#High_Level_Architecture_3) + - [[4.2.1]{.tocnumber} [RM + Clients]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#RM_Clients) + - [[4.2.2]{.tocnumber} [RM + Server]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#RM_Server) + - [[4.2.3]{.tocnumber} [RM + API]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#RM_API) + - [[4.2.4]{.tocnumber} [RM + Core]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#RM_Core) + - [[4.3]{.tocnumber} + [Initialization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Initialization_3) + - [[4.4]{.tocnumber} + [Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Scheduling_3) + - [[4.4.1]{.tocnumber} [Command + Submission]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Command_Submission) + - [[4.4.1.1]{.tocnumber} + [Runlist]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Runlist) + - [[4.4.2]{.tocnumber} [In-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#In-VM_Scheduling_3) + - [[4.4.2.1]{.tocnumber} [Guest kernel + (nvidia.ko)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Guest_kernel_(nvidia.ko)) + - [[4.4.3]{.tocnumber} [Between-VM + Scheduling]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Between-VM_Scheduling_3) + - [[4.4.3.1]{.tocnumber} [Host kernel + (nvidia.ko)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Host_kernel_(nvidia.ko)) + - [[4.4.3.2]{.tocnumber} [Host usermode (nvidia-vgpu-mgr / + libnvidia-vgpu.so)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Host_usermode_(nvidia-vgpu-mgr_/_libnvidia-vgpu.so)) + - [[4.4.3.3]{.tocnumber} + [nvidia-vgpu-mgr]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#nvidia-vgpu-mgr) + - [[4.4.3.3.1]{.tocnumber} + [vmiop]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#vmiop) + - [[4.4.3.4]{.tocnumber} [Device Firmware + (GSP)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Device_Firmware_(GSP)) + - [[4.5]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Memory_Management_3) + - [[4.5.1]{.tocnumber} [Programming the + MMU]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Programming_the_MMU) + - [[4.5.1.1]{.tocnumber} + [AMAPLibrary]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#AMAPLibrary) + - [[4.5.1.2]{.tocnumber} [Architecture + HALs]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Architecture_HALs) + - [[4.5.1.3]{.tocnumber} [DMA from Falcon / NvRISC-V to + Frame Buffer Interface + (FBIF)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#DMA_from_Falcon_/_NvRISC-V_to_Frame_Buffer_Interface_(FBIF)) + - [[4.5.2]{.tocnumber} [Translation + Tables]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Translation_Tables_2) + - [[4.5.2.1]{.tocnumber} + [vmiop_gva]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#vmiop_gva) + - [[4.6]{.tocnumber} [Display Surface + Virtualization]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#Display_Surface_Virtualization_4) +- [[5]{.tocnumber} + [amdgpu]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#amdgpu) +- [[6]{.tocnumber} [References (Talks & Reading + Material)]{.toctext}](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html#References_(Talks_&_Reading_Material)) +::: + +## [Article Structure]{#Article_Structure .mw-headline} + +This article will aim to provide information about the following details +of GPU drivers: + +### [High Level Architecture]{#High_Level_Architecture .mw-headline} + +This section will detail high level architectures of each driver. + +### [Initialization]{#Initialization .mw-headline} + +This section will cover how the GPU\'s embedded components, the GPU +driver, and virtualization functions are initialized. + +### [Scheduling]{#Scheduling .mw-headline} + +This section will detail how the device schedules instructions for +execution. + +This will attempt to provide a comprehensive view of scheduling from +virtualized processes down to execution within the device. + +#### [In-VM Scheduling]{#In-VM_Scheduling .mw-headline} + +The In-VM Scheduling section will detail how instructions scheduled +within the virtual machine\'s GPU device driver. + +#### [Between-VM Scheduling]{#Between-VM_Scheduling .mw-headline} + +The Between-VM Scheduling section will detail how the host kernel module +and/or virtual GPU helper functions handle scheduling / context swaps +between virtual machines on a computer system. + +#### []{#Firmware_Scheduling_.28if_applicable.29}[Firmware Scheduling (if applicable)]{#Firmware_Scheduling_(if_applicable) .mw-headline} + +The Firmware Scheduling section will cover the GPU\'s internal +scheduling model if a deferred execution pathway is used (like i915\'s +GuC or OpenRM\'s GSP). + +In the case an intermediate scheduling microcontroller is not used this +section may be less applicable (ie: vExeclist scheduling under Intel +vGPUs). + +### [Memory Management]{#Memory_Management .mw-headline} + +The Memory Management section will cover how the GPU driver manages +memory for virtual GPUs and host processes. + +This will aim detail paging abstractions used for global memory +translation, and per-process memory translation. + +### [Display Surface Virtualization]{#Display_Surface_Virtualization .mw-headline} + +The Display Surface Virtualization section will detail how virtual +displays are provided to guests and/or graphics rendering buffers (pixel +surfaces) are shared from guest to host if such functions are provided +via the driver. + +#### [Graphics Buffer Sharing]{#Graphics_Buffer_Sharing .mw-headline} + +This section will cover methods provided by the GPU driver suitable for +high performance graphics sharing. + +## [Vendor Neutral]{#Vendor_Neutral .mw-headline} + +This section will detail functions in common between GPU drivers. + +Also see [Display Virtualization for Windows +OS](https://github.com/intel/Display-Virtualization-for-Windows-OS){.external +.text rel="nofollow"}. + +### [Knowledge Resources Used]{#Knowledge_Resources_Used .mw-headline} + +This section is supported by significant contributions to documentation +and open source by **Satyeshwar Singh**. + +### [Display Surface Virtualization]{#Display_Surface_Virtualization_2 .mw-headline} + +The Display Surface Virtualization section will detail how virtual +displays are provided to guests and/or graphics rendering buffers (pixel +surfaces) are shared from guest to host if such functions are provided +via the driver. + +#### [Graphics Buffer Sharing]{#Graphics_Buffer_Sharing_2 .mw-headline} + +This section will deal with graphics buffer sharing for vendor neutral +GPUs. + +##### [Display Flow in Linux]{#Display_Flow_in_Linux .mw-headline} + +Userspace applications provide their buffers to compositor. + +Compositor asks Mesa to create a framebuffer. + +Framebuffer is allocated through vendor driver. + +Vendor driver flips the framebuffer on the screen. + +##### [SR-IOV and Mdev]{#SR-IOV_and_Mdev .mw-headline} + +SR-IOV VFs don\'t have access to the display controller (only PF does). + +Known issue is displaying a VF\'s framebuffer on the screen. + +##### []{#VFs_in_QEMU_Hypervisor_.28VirtIO-GPU.29}[VFs in QEMU Hypervisor (VirtIO-GPU)]{#VFs_in_QEMU_Hypervisor_(VirtIO-GPU) .mw-headline} + +SR-IOV and Mdev VFs run in QEMU Hypervisor. + +QEMU has full access to all pages in VF\'s address space. + +VirtIO-GPU allows for allocating buffers (not API remoting in this +case). + +Mesa\'s KMSRO allocates framebuffer via virtio-gpu. + +Mesa\'s KMSRO asks vendor driver to import framebuffer (no specific +compositor dependancy). + +##### [Transport]{#Transport .mw-headline} + +A Scatter Gather List (SGL) of physical pages is constructed by +VirtIO-GPU of VF. + +###### [QEMU Host-Side u-dma-buf]{#QEMU_Host-Side_u-dma-buf .mw-headline} + +Host QEMU uses u-dma-buf driver to reconstruct a virtual memory pointer +from the SGL shared by VF. + +u-dma-buf driver allocates contiguous memory blocks in kernel as DMA +buffers. + +###### [QEMU Host-Side Modules]{#QEMU_Host-Side_Modules .mw-headline} + +Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI. + +QEMU UI has several toolkits to support like GTK, SDL, etc. with GTK. +being the default. + +GTK uses EGL and passes it the DMABUF as a texture. + +##### [Windows VFs]{#Windows_VFs .mw-headline} + +Windows OS doesn\'t support DMABUF capability so we can\'t allocate +buffers from VirtIO-GPU and share them with the Windows Kernel Mode +Driver (KMD). + +Windows OS is different in the way that the FB is allocated via the OS +rather than the miniport driver. + +Modified version of RedHat virtio-gpu-do (short for Display Only) driver +used. + +##### [Windows Driver Stack]{#Windows_Driver_Stack .mw-headline} + +OS (DWM) allocates frame buffers and asks GPU to write to them through +Miniport. + +DVServer UMD (IDD) asks the OS for the FB copy. + +DVServer UMD (IDD) passes the virtual memory address to DVServer KMD. + +##### [DVServer KMD]{#DVServer_KMD .mw-headline} + +DVServer KMD finds the SGL (Scatter Gather List) of physical pages for +this virtual memory address. + +This SGL is passed via virt-queue from the VF to the host QEMU. + +##### [Android VFs]{#Android_VFs .mw-headline} + +Android uses Linux kernel underneath. VirtIO-GPU is present in +Android\'s kernel. + +KMSRO patch to allocate framebuffer via VirtIO-GPU also ported over to +Android. + +Need modifications in the minigbm lib of Android to connect with KMSRO +part. + +Rest of stack looks identical to Linux VF/PF. + +## [i915]{#i915 .mw-headline} + +### [Knowledge Resources Used]{#Knowledge_Resources_Used_2 .mw-headline} + +This section is supported by significant contributions to documentation +and open source by **Zhi Wang**, **Ben Widawsky**, and **Igor +Bogdanov**. + +See references 2, 3, 4, 5, 6, 7, 8, and 9 in the [References (Talks & +Reading +Material)](index.php/GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} section. + +### [High Level Architecture]{#High_Level_Architecture_2 .mw-headline} + +#### [i915 Clients]{#i915_Clients .mw-headline} + +Processes which make use of the Intel i915 driver receive an i915 Client +ID. + +### [Initialization]{#Initialization_2 .mw-headline} + +During initialization of the i915 driver the GuC binary blob is +offloaded into the Graphics Translation Table (GTT). This allows the GuC +to read GTT-loaded binary blob from shared framebuffer memory so that it +may boot. + +### [Scheduling]{#Scheduling_2 .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 0: i915 vGPU +Scheduling](images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/300px-Figure_0-_i915_vGPU_Scheduling.png){.thumbimage +decoding="async" width="300" height="227" +srcset="images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/450px-Figure_0-_i915_vGPU_Scheduling.png 1.5x, images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/600px-Figure_0-_i915_vGPU_Scheduling.png 2x"}](index.php/File:Figure_0-_i915_vGPU_Scheduling.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_0-_i915_vGPU_Scheduling.png.html "Enlarge"){.internal} +::: + +**Figure 0:** i915 vGPU high-level Scheduling. See slides from: +[\[9\]](index.php/GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +There are several abstractions for GPU virtual machine scheduling. Those +are as follows: + +- Guest kernel (i915.ko) +- Host kernel (i915.ko) +- Device Firmware (GuC) + +##### [In-VM Scheduling]{#In-VM_Scheduling_2 .mw-headline} + +##### []{#Guest_kernel_.28i915.ko.29}[Guest kernel (i915.ko)]{#Guest_kernel_(i915.ko) .mw-headline} + +###### [vExeclist]{#vExeclist .mw-headline} + +The vExeclist is a method to submit commands directly to the GPU without +the use of an intermediate microcontroller. + +###### [vGuC]{#vGuC .mw-headline} + +vGuC is a command submission interface used to process commands to the +Intel [Graphics Microcontroller +(GuC)](index.php/GPU_Firmware.html#GuC){.external .text rel="nofollow"}. + +#### [Between-VM Scheduling]{#Between-VM_Scheduling_2 .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 1: i915 vGPU Scheduling Requests & +Events](images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/300px-I915_Scheduling_Events_and_Requests.png){.thumbimage +decoding="async" width="300" height="232" +srcset="images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/450px-I915_Scheduling_Events_and_Requests.png 1.5x, images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/600px-I915_Scheduling_Events_and_Requests.png 2x"}](index.php/File:I915_Scheduling_Events_and_Requests.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:I915_Scheduling_Events_and_Requests.png.html "Enlarge"){.internal} +::: + +**Figure 1:** i915 vGPU Scheduling Requests & Events. See slides from: +[\[9\]](index.php/GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +##### []{#Host_kernel_.28i915.ko.29}[Host kernel (i915.ko)]{#Host_kernel_(i915.ko) .mw-headline} + +Submitting commands to the GPU under i915 can take several paths. One +pathway makes use of direct command submission without an intermediate +micro-controller whereas the other uses an intermediate +micro-controller. The intermediate micro-controller approach increases +the amount of binary-blob code used and abstracts the kernel module from +the device\'s internal scheduling model. + +###### [Execlist]{#Execlist .mw-headline} + +Execlist executes commands synchronously on the device without an +intermediate microcontroller. This is the preferred method of executing +commands by some driver developers because of it\'s stability and +transparency under current i915 development. + +###### [GuC]{#GuC .mw-headline} + +GuC provides an execution pathway with an intermediate microcontroller +providing a scheduling abstraction for Intel\'s preferred internal +scheduling model. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 2: Intel vGPU Scheduler request +flow.](images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/300px-Figure_2-_Intel_vGPU_Scheduler.png){.thumbimage +decoding="async" width="300" height="233" +srcset="images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/450px-Figure_2-_Intel_vGPU_Scheduler.png 1.5x, images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/600px-Figure_2-_Intel_vGPU_Scheduler.png 2x"}](index.php/File:Figure_2-_Intel_vGPU_Scheduler.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_2-_Intel_vGPU_Scheduler.png.html "Enlarge"){.internal} +::: + +**Figure 2:** i915 vGPU Scheduler request flow. See slides from: +[\[9\]](index.php/GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +##### []{#Device_Firmware_.28GuC.29}[Device Firmware (GuC)]{#Device_Firmware_(GuC) .mw-headline} + +### [Memory Management]{#Memory_Management_2 .mw-headline} + +##### [Translation Tables]{#Translation_Tables .mw-headline} + +###### []{#GTT_.28Graphics_Translation_Table.29}[GTT (Graphics Translation Table)]{#GTT_(Graphics_Translation_Table) .mw-headline} + +GPU Memory on-device is a part of a GTT or Graphics Translation Table. +This table stores information globally for all graphics processes within +the system. Some processes access the Global Graphics Translation Table +(GGTT) such as +[DRI](https://en.wikipedia.org/wiki/Direct_Rendering_Infrastructure "wikipedia:Direct Rendering Infrastructure"){.extiw} +while other\'s receive a Per Process Graphics Translation Table (PPGTT) +buffer based on their i915 Client ID. + +###### []{#GGTT_.28Global_Graphics_Translation_Table.29}[GGTT (Global Graphics Translation Table)]{#GGTT_(Global_Graphics_Translation_Table) .mw-headline} + +###### []{#PPGTT_.28Per_Process_Graphics_Translation_Table.29}[PPGTT (Per Process Graphics Translation Table)]{#PPGTT_(Per_Process_Graphics_Translation_Table) .mw-headline} + +Process-specific memory buffers are stored inside a Per Process Graphics +Translation Table or PPGTT. This is a [GPU +MMU](index.php/Virtual_IO_Internals.html#VRAM_Isolation_(GPU_GMMU)){.external +.text rel="nofollow"} translated subregion or IOVA of global GPU memory +specific to a GPU process\'s client ID. + +###### [Aliasing PPGTT]{#Aliasing_PPGTT .mw-headline} + +Aliasing PPGTT (Per Process Graphics Translation Table) refers to +partially separated GPU resources (process context). + +###### [Real PPGTT]{#Real_PPGTT .mw-headline} + +Real PPGTT (Per Process Graphics Translation Table) refers to fully +separated GPU resources (process context). + +### [Display Surface Virtualization]{#Display_Surface_Virtualization_3 .mw-headline} + +The Intel vGPU makes use of two modes for Display Surface +Virtualization. + +- VirtIO-GPU (Linux) +- Indirect Display Driver (Windows) + +#### [VirtIO-GPU]{#VirtIO-GPU .mw-headline} + +#### []{#IDD_.28Indirect_Display_Driver.29}[IDD (Indirect Display Driver)]{#IDD_(Indirect_Display_Driver) .mw-headline} + +The IDD ([Indirect Display +Driver](https://learn.microsoft.com/en-us/windows-hardware/drivers/display/indirect-display-driver-model-overview){.external +.text rel="nofollow"}) provides virtual display functions with arbitrary +resolutions to any rendering device virtual or physical. + +Intel\'s IDD can be found in their [Display Virtualization for Windows +OS](https://github.com/intel/Display-Virtualization-for-Windows-OS/){.external +.text rel="nofollow"} repository. + +#### [Graphics Buffer Sharing]{#Graphics_Buffer_Sharing_3 .mw-headline} + +Intel\'s i915 driver provides functionality to directly map display +memory from a [guest vGPU Virtual Function (either SR-IOV or VFIO-Mdev) +into the host GPU\'s Physical +Function](index.php/Merged_Drivers.html){.external .text rel="nofollow"} +without slow memory copies or graphics compression. For users running +GPU virtualization on their local device this results in a significant +performance uplift compared to traditional graphics sharing +functionality built for remote access use-cases such as VDI. + +Intel\'s [0copy display virtualization +tools](https://github.com/intel/Display-Virtualization-for-Windows-OS){.external +.text rel="nofollow"} are simple to implement as sharing does not rely +upon an added [IVSHMEM (Inter-VM Shared Memory +device)](https://www.qemu.org/docs/master/system/devices/ivshmem.html){.external +.text rel="nofollow"} - rather the host directly maps the guest\'s +display memory via [udmabuf](https://lwn.net/Articles/758903/){.external +.text rel="nofollow"} as the buffer sharing functions are provided +within the i915 open source driver. + +## [OpenRM]{#OpenRM .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 3: GPU BAR to Timeshared Syhededuling via Channel +IO](images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/300px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png){.thumbimage +decoding="async" width="300" height="226" +srcset="images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/450px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png 1.5x, images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/600px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png 2x"}](index.php/File:Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png.html "Enlarge"){.internal} +::: + +**Figure 3:** GPU BAR to Timeshared Scheduling via Channel IO. +::: +::: +::: + +### [Knowledge Resources Used]{#Knowledge_Resources_Used_3 .mw-headline} + +This section is supported by significant contributions to documentation +and open source by **Andy Currid**, **Neo Jia**, **John Fanelli**, and +**Neha Joshi**. + +### [High Level Architecture]{#High_Level_Architecture_3 .mw-headline} + +The Open Resource Manager (RM driver) makes use of a highly object +oriented paradigm comprised of multiple \"engines\" which act as +micro-services for servicing driver requests. + +The Open Resource Manager driver (also known as +[OpenRM](index.php/OpenRM.html){.external .text rel="nofollow"}) refers +to Nvidia\'s +[open-kernel-modules](https://github.com/NVIDIA/open-gpu-kernel-modules){.external +.text rel="nofollow"}. + +Broadly speaking the OpenRM driver consists of two parts. + +- The Platform RM (OpenRM) +- The Firmware RM (GSP RM / RM Core) + +The Platform RM is loaded into the Linux Kernel as nvidia.ko. This +module communicates with the GSP RM for via [Remote Procedure Calls +(RPCs)](https://en.wikipedia.org/wiki/Remote_procedure_call "wikipedia:Remote procedure call"){.extiw} +to communicate with engines from the RM Core. + +##### [RM Clients]{#RM_Clients .mw-headline} + +Processes (local, remote, or virtualized) which make use of the RM +driver receive an RM Client ID. + +#### [RM Server]{#RM_Server .mw-headline} + +The RM Server (or Resource Server) tracks RM Clients as well as the +hardware and software resources they control, allocate, and free. + +#### [RM API]{#RM_API .mw-headline} + +API to control the Resource Manager Server. + +#### [RM Core]{#RM_Core .mw-headline} + +Core functions of the RM driver controlling resource locking, mapping, +unmapping, control calls, constructors, and deconstructors. Under OpenRM +the RM Core runs within the GPU System Processor (GSP micro-controller) +while in pre-open source versions of the Resource Manager the RM Core +ran within the nvidia.ko kernel module + +### [Initialization]{#Initialization_3 .mw-headline} + +During bring up of the hardware several binary blobs are loaded from +embedded [Boot +ROM](https://en.wikipedia.org/wiki/Boot_ROM "wikipedia:Boot ROM"){.extiw} +memory to bootstrap embedded controller bring up from which point +additional software is loaded from onboard +[SPI](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface "wikipedia:Serial Peripheral Interface"){.extiw} +flash memory. + +Software loaded from SPI flash is necessary for the full initialization +of the Falcon/NvRISC processor as well as a cached version of the +software necessary to run the GPU System Processor (GSP). + +Once the platform is posted it is ready to communicate with the host +platform\'s RM driver. The OpenRM driver offloads a binary blob +containing the RM Core to the [GPU System Processor +(GSP)](index.php/GPU_Firmware.html#GSP){.external .text rel="nofollow"} +which is likely to contain a more recent version than the cached version +contained in on-board SPI flash. + +### [Scheduling]{#Scheduling_3 .mw-headline} + +There are several abstractions for GPU virtual machine scheduling. Those +are as follows: + +- Guest kernel (nvidia.ko) +- Host kernel (nvidia.ko) +- Host usermode (gpu-mgr / libnvidiavgpu.so) +- Device Firmware (GSP) + +#### [Command Submission]{#Command_Submission .mw-headline} + +##### [Runlist]{#Runlist .mw-headline} + +#### [In-VM Scheduling]{#In-VM_Scheduling_3 .mw-headline} + +Virtual machines contain their own GPU scheduling within the Nvidia +kernel module in the guest OS. + +##### []{#Guest_kernel_.28nvidia.ko.29}[Guest kernel (nvidia.ko)]{#Guest_kernel_(nvidia.ko) .mw-headline} + +Within a virtual machine running the Nvidia driver messages to the GPU +are first sent to the guest nvidia.ko kernel module. + +The guest then determines whether a vRPC (virtual Remote Procedure Call) +or a pRPC (physical Remote Procedure Call) should be sent. Both pRPCs +and vRPCs are sent through the host RM driver (Resource Manager). + +> *Note: Unclear on execution pathway for pRPCs vs vRPCs. pRPCs may go +> directly to device.* + +#### [Between-VM Scheduling]{#Between-VM_Scheduling_3 .mw-headline} + +In addition to scheduling which occurs within the virtual machine the +Resource Manager driver also schedules messages to the GPU between +GPU-accelerated virtual machines and host processes. + +##### []{#Host_kernel_.28nvidia.ko.29}[Host kernel (nvidia.ko)]{#Host_kernel_(nvidia.ko) .mw-headline} + +Messages sent by the guest (via vRPC or pRPC) are received by the host +Nvidia.ko driver. + +Nvidia.ko contains a virtual GPU state machine which contains status +information for the virtual GPU. + +Nvidia.ko also contains a virtual GPU kernel scheduler which interacts +with virtual GPU objects. + +Nvidia.ko also contains an RM Call scheduler which schedules calls on an +RM class. + +The Nividia.ko kernel module exits to userspace to execute the +nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin). + +##### []{#Host_usermode_.28nvidia-vgpu-mgr_.2F_libnvidia-vgpu.so.29}[Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)]{#Host_usermode_(nvidia-vgpu-mgr_/_libnvidia-vgpu.so) .mw-headline} + +After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and +it\'s library libnvidia-vgpu.so) are executed to schedule VM-exits +described below. + +##### [nvidia-vgpu-mgr]{#nvidia-vgpu-mgr .mw-headline} + +The nvidia-vgpu-mgr is a process which provides the spawning of virtual +GPU stubs and population with capability information. + +This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and +nvidia-vgpu-vfio.ko components. + +This process and the libnvidia-vgpu.so contain, and execute the VMIOP. + +This process (and the VMIOP) schedules RPCs sent by the guest, receives +VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, +map, unmap to the [RM +Core](index.php/GPU_Driver_Internals.html#RM_Core){.external .text +rel="nofollow"}. + +###### [vmiop]{#vmiop .mw-headline} + +VMIOP (Virtual Machine Input Output Plugin) handles presenting +virtualized functionality into the guest. + +The Virtual Machine Input Output Plugin software handles virtual +displays, compute API offload, and most importantly [BAR (Base Address +Register) +quirks](index.php/Virtual_I/O_Internals.html#VFIO_Quirks_(region_traps)){.external +.text rel="nofollow"}. + +The VMIOP is an [SDK (Software Development +Kit)](https://en.wikipedia.org/wiki/Software_development_kit "wikipedia:Software development kit"){.extiw} +provided in binary format split between the libnvidiavgpu.so and +nvidia-vgpu-mgr which provides userland helper functions for GPU +virtualization. + +Messages to the VMIOP are scheduled by Linux kernel +[niceness](https://www.learnlinux.org.za/courses/build/internals/ch07s02.html){.external +.text rel="nofollow"} (scheduling abstraction). + +##### []{#Device_Firmware_.28GSP.29}[Device Firmware (GSP)]{#Device_Firmware_(GSP) .mw-headline} + +Messages received by the host RM driver (Resource Manager) are then +scheduled by the RM Core contained within the GSP (GPU System +Processor). The GSP handles the device\'s internal scheduling model. + +### [Memory Management]{#Memory_Management_3 .mw-headline} + +Managing virtual machine memory is very important to the security of +virtualization. + +This section will cover the method by which secure memory \"enclaves\" +or [IO Virtual Addresses +(IOVAs)](https://terenceli.github.io/%E6%8A%80%E6%9C%AF/2019/08/04/iommu-introduction){.external +.text rel="nofollow"} may be provisioned and separation enforced by +hardware constructs within the GPU. + +##### [Programming the MMU]{#Programming_the_MMU .mw-headline} + +In order to hardware enforce separation between memory allocated to +Virtual Machines (VMs) virtualization software must program the GPU\'s +MMU (GMMU controller) to create IO Virtual Addresses (IOVAs). + +In order to create such configurations several abstractions are used to +translate high level representations of virtualization programmed via +the vmiop and gpu-mgr into practical, architecture specific +instructions. + +###### [AMAPLibrary]{#AMAPLibrary .mw-headline} + +The AMAPLibrary acts as a device abstraction framework for GPU driver +software to program using high level representations of MMU +configuration. + +The AMAPLibrary translates high level representations of GPU +virtualization into graphics architecture-specific logic contained +within architecture HALs (Hardware Abstraction Layers). + +###### [Architecture HALs]{#Architecture_HALs .mw-headline} + +GPU [Hardware Abstraction Layers +(HALs)](https://archive.ll.mit.edu/HPEC/agendas/proc07/Day3/10_Hensley_Abstract.pdf){.external +.text rel="nofollow"} contain logic specific to graphics architectures, +for instance the precise method by which the GPU driver may interact +with the Falcon to provision MMU protected memory. + +###### []{#DMA_from_Falcon_.2F_NvRISC-V_to_Frame_Buffer_Interface_.28FBIF.29}[DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)]{#DMA_from_Falcon_/_NvRISC-V_to_Frame_Buffer_Interface_(FBIF) .mw-headline} + +The Falcon (FAst Logic CONtroller) / NvRISC-V embedded controller emits +DMAs to the Frame Buffer Interface (FBIF) in order to interact with the +device\'s GMMU controller. + +User programs and VMs have their memory translated through the GMMU. + +Once created memory translations within a virtual machine\'s IO Virtual +Address (IOVA) will be protected by the device\'s GMMU controller. + +##### [Translation Tables]{#Translation_Tables_2 .mw-headline} + +###### [vmiop_gva]{#vmiop_gva .mw-headline} + +### [Display Surface Virtualization]{#Display_Surface_Virtualization_4 .mw-headline} + +## [amdgpu]{#amdgpu .mw-headline} + +## []{#References_.28Talks_.26_Reading_Material.29}[References (Talks & Reading Material)]{#References_(Talks_&_Reading_Material) .mw-headline} + +1. [Intel Graphics Programmer\'s Reference Manuals + (PRM)](https://01.org/linuxgraphics/documentation/hardware-specification-prms){.external + .text rel="nofollow"} +2. [i915: Hardware Contexts (and some bits about + batchbuffers)](https://bwidawsk.net/blog/2013/1/i915-hardware-contexts-and-some-bits-about-batchbuffers/){.external + .text rel="nofollow"} +3. [i915: The Global GTT Part + 1](https://bwidawsk.net/blog/2014/6/the-global-gtt-part-1/){.external + .text rel="nofollow"} +4. [i915: Aliasing PPGTT Part + 2](https://bwidawsk.net/blog/2014/6/aliasing-ppgtt-part-2/){.external + .text rel="nofollow"} +5. [i915: True PPGTT Part + 3](https://bwidawsk.net/blog/2014/7/true-ppgtt-part-3/){.external + .text rel="nofollow"} +6. [i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit + address space, GPU \"mirroring\", and yeah, something about relocs + too)](https://bwidawsk.net/blog/2014/7/future-ppgtt-part-4-dynamic-page-table-allocations-64-bit-address-space-gpu-mirroring-and-yeah-something-about-relocs-too/){.external + .text rel="nofollow"} +7. [i915: Security of the Intel Graphics Stack - Part 1 - + Introduction](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external + .text rel="nofollow"} +8. [i915: Security of the Intel Graphics Stack - Part 2 - FW \<-\> + GuC](https://igor-blue.github.io/2021/02/24/graphics-part2.html){.external + .text rel="nofollow"} +9. [i915: An Introduction to Intel GVT-g (with new + architecture)](https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf){.external + .text rel="nofollow"} +10. [lwn.net: Add udmabuf misc + device](https://lwn.net/Articles/758903/){.external .text + rel="nofollow"} +11. [Nvidia RISC-v + Story](https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf){.external + .text rel="nofollow"} +12. [IOMMU + Introduction](https://terenceli.github.io/%E6%8A%80%E6%9C%AF/2019/08/04/iommu-introduction){.external + .text rel="nofollow"} +13. [Hardware and Compute Abstraction Layers For Accelerated Computing + Using Graphics Hardware and Conventional + CPUs](https://archive.ll.mit.edu/HPEC/agendas/proc07/Day3/10_Hensley_Abstract.pdf){.external + .text rel="nofollow"} +14. [nVidia GPU Introduction + (envytools)](https://envytools.readthedocs.io/en/latest/hw/intro.html){.external + .text rel="nofollow"} +15. [Delivering High Performance Remote Graphics With Nvidia GRID + Virtual + GPU](https://on-demand.gputechconf.com/gtc/2014/presentations/S4725-hi-perf-graphics-nvidia-grid-virtual-gpus.pdf){.external + .text rel="nofollow"} +16. [NVIDIA Multi-Instance + GPU](https://nehajoshi.dev/post/nvidia_mig_feature/){.external .text + rel="nofollow"} +17. [i915: Kaby Lake Intel Graphics Programmer\'s Reference Manual + \[Volume 5: Memory + Views\]](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf){.external + .text rel="nofollow"} +18. [Lifecycle of a Triangle - Nvidia\'s logical + pipeline](https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline){.external + .text rel="nofollow"} +19. [Nvidia Parallel Thread Execution + (PTX)](https://docs.nvidia.com/cuda/parallel-thread-execution/){.external + .text rel="nofollow"} +20. [i915/GEM + Crashcourse](https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html){.external + .text rel="nofollow"} +21. [drm: Add GEM (\"graphics execution manager\") to i915 + driver.](https://lwn.net/Articles/292583/){.external .text + rel="nofollow"} +::: + +::: printfooter +Retrieved from +\"[https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23791](index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html){dir="ltr"}\" +::: +::: + +::: {#catlinks .catlinks .catlinks-allhidden mw="interface"} +::: +::: +::: + +::: {#mw-navigation} +## Navigation menu + +::: {#mw-head} +### Personal tools {#p-personal-label .vector-menu-heading} + +::: vector-menu-content +- [[Log + in](https://open-iov.org/index.php?title=Special:UserLogin&returnto=GPU+Driver+Internals&returntoquery=oldid%3D23791 "You are encouraged to log in; however, it is not mandatory [o]"){accesskey="o"}]{#pt-login} +::: + +::: {#left-navigation} +### Namespaces {#p-namespaces-label .vector-menu-heading} + +::: vector-menu-content +- [[Page](index.php/GPU_Driver_Internals.html "View the content page [c]"){accesskey="c"}]{#ca-nstab-main} +- [[Discussion](https://open-iov.org/index.php?title=Talk:GPU_Driver_Internals&action=edit&redlink=1 "Discussion about the content page (page does not exist) [t]"){rel="discussion" + accesskey="t"}]{#ca-talk} +::: + +### Variants [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-variants-label .vector-menu-heading} + +::: vector-menu-content +::: +::: + +::: {#right-navigation} +### Views {#p-views-label .vector-menu-heading} + +::: vector-menu-content +- [[Read](index.php/GPU_Driver_Internals.html)]{#ca-view} +- [[View + source](index.php%3Ftitle=GPU_Driver_Internals&action=edit.html "This page is protected. + You can view its source [e]"){accesskey="e"}]{#ca-viewsource} +- [[View + history](index.php%3Ftitle=GPU_Driver_Internals&action=history.html "Past revisions of this page [h]"){accesskey="h"}]{#ca-history} +::: + +### More [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-cactions-label .vector-menu-heading} + +::: vector-menu-content +::: + +::: {#p-search .vector-search-box role="search"} +
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This page will attempt to document embedded GPU +firmware and support for IO virtualization through various firmware +functions. + +> An absence of critical technical documentation has historically slowed +> growth and adoption of developer ecosystems for GPU virtualization. +> +> This +> [CC-BY-4.0](https://creativecommons.org/licenses/by/4.0/){.external +> .text rel="nofollow"} licensed content can either be used with +> attribution, or used as inspiration for new documentation, created by +> GPU vendors for public commercial distribution as developer +> documentation. +> +> Where possible, this documentation will clearly label dates and +> versions of observed-but-not-guaranteed behaviour vs. +> vendor-documented stable interfaces/behaviour with guarantees of +> forward or backward compatibility. + +::: {#toc .toc role="navigation" aria-labelledby="mw-toc-heading"} +::: {.toctitle lang="en" dir="ltr"} +## Contents {#mw-toc-heading} + +[]{.toctogglespan} +::: + +- [[1]{.tocnumber} + [Intel]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Intel) + - [[1.1]{.tocnumber} [Firmware + Images]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Firmware_Images) + - [[1.1.1]{.tocnumber} [Intel Firmware Support Package + (FSP)]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Intel_Firmware_Support_Package_(FSP)) + - [[1.1.1.1]{.tocnumber} [FSP + Configuration]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#FSP_Configuration) + - [[1.1.1.1.1]{.tocnumber} [Editing FSP + Configuration]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Editing_FSP_Configuration) + - [[1.1.1.2]{.tocnumber} [FSP Binary + Format]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#FSP_Binary_Format) + - [[1.1.2]{.tocnumber} [Known Firmware Package + Variations]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Known_Firmware_Package_Variations) + - [[1.2]{.tocnumber} [Embedded + Controllers]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Embedded_Controllers) + - [[1.2.1]{.tocnumber} + [GuC]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GuC) + - [[1.2.1.1]{.tocnumber} [Hardware + Architecture]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Hardware_Architecture) + - [[1.2.1.2]{.tocnumber} [Software + Architecture]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Software_Architecture) + - [[1.2.1.2.1]{.tocnumber} [GuC Blob Checksum & Code + Signing]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GuC_Blob_Checksum_&_Code_Signing) +- [[2]{.tocnumber} + [Nvidia]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Nvidia) + - [[2.1]{.tocnumber} [Firmware + Images]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Firmware_Images_2) + - [[2.2]{.tocnumber} [Embedded + Controllers]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Embedded_Controllers_2) + - [[2.2.1]{.tocnumber} [Falcon / + NV-RISCV]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#Falcon_/_NV-RISCV) + - [[2.2.2]{.tocnumber} + [GSP]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GSP) + - [[2.2.2.1]{.tocnumber} [GSP Initialization & + Offload]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#GSP_Initialization_&_Offload) + - [[2.2.3]{.tocnumber} + [CMU]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#CMU) +- [[3]{.tocnumber} + [AMD]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#AMD) +- [[4]{.tocnumber} [References (Talks & Reading + Material)]{.toctext}](index.php%3Ftitle=GPU_Firmware&oldid=23779.html#References_(Talks_&_Reading_Material)) +::: + +## [Intel]{#Intel .mw-headline} + +### [Firmware Images]{#Firmware_Images .mw-headline} + +This section will cover firmware images used in Intel GPUs. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 1: The FSP Binary Layout from Intel® Firmware Support Package +External Architecture +Specification.](images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/300px-Screen_Shot_2022-11-18_at_4.14.32_PM.png){.thumbimage +decoding="async" width="300" height="261" +srcset="images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/450px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 1.5x, images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/600px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 2x"}](index.php/File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html "Enlarge"){.internal} +::: + +Figure 1: The FSP Binary Layout from Intel® Firmware Support Package +External Architecture Specification. +[Source](https://cdrdv2.intel.com/v1/dl/getContent/736809){.external +.text rel="nofollow"} +::: +::: +::: + +#### []{#Intel_Firmware_Support_Package_.28FSP.29}[Intel Firmware Support Package (FSP)]{#Intel_Firmware_Support_Package_(FSP) .mw-headline} + +Much like CPUs Intel\'s GPUs also contain a Firmware Support Package +(FSP). + +The Coreboot project provides public domain information on the FSP +[here](https://doc.coreboot.org/soc/intel/fsp/index.html){.external +.text rel="nofollow"}. + +##### [FSP Configuration]{#FSP_Configuration .mw-headline} + +In the context of GPUs the FSP configures several functions of the +device. + +Those functions are as follows: + + ---------------------------------------------------------------------------------- ------------------------------ + FSP Parameter Possible Values + GFSP Status 0x00 + FIVR SSC Value \*.\*% + FIVR RFI Value \*.\*MHz + GT Subsystem Vendor ID 0x8086 + GT Subsystem Device ID 0x\*\* + HDA Subsystem Vendor ID 0x0000 + HDA Subsystem Device ID 0x0000 + P2SB Enable Yes/No + LMEBAR Max + GTMMADDR Prefetch Capability Prefetch Enabled + [Display Present](index.php/Merged_Drivers.html){.external .text rel="nofollow"} Enabled/Disabled + I2C For Third Party Devices Enabled/Disabled + I2C Device Address 1 0x0000 + I2C Device Address 2 0x0000 + I2C Bus Speed Standard mode (0 to 100Kbps) + ---------------------------------------------------------------------------------- ------------------------------ + + : GPU Firmware Support Package + +###### [Editing FSP Configuration]{#Editing_FSP_Configuration .mw-headline} + +The FSP configuration editor can be downloaded +[here](https://github.com/tianocore/edk2/tree/master/IntelFsp2Pkg/Tools/ConfigEditor){.external +.text rel="nofollow"} and it\'s user manual is available +[here](https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManuals/ConfigEditorUserManual.md){.external +.text rel="nofollow"}. + +##### [FSP Binary Format]{#FSP_Binary_Format .mw-headline} + +The FSP\'s binary layout is detailed within the [Intel® FSP External +Architecture Specification +v2.4](https://cdrdv2.intel.com/v1/dl/getContent/736809){.external .text +rel="nofollow"} on page 14. + +#### [Known Firmware Package Variations]{#Known_Firmware_Package_Variations .mw-headline} + +Some firmware packages may include an \*\*End of Manufacturing Flash +Protection Mode\*\* status of Protected or Unprotected. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 2: Firmware status information for an Intel DG2 +device.](images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/300px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png){.thumbimage +decoding="async" width="300" height="613" +srcset="images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/450px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 1.5x, images/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 2x"}](index.php/File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html "Enlarge"){.internal} +::: + +Figure 2: Firmware status information for an Intel DG2 device. +::: +::: +::: + +Similar [SPI Write +Protection](https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/){.external +.text rel="nofollow"} functionality is made available through Intel CPUs +under [System Management Mode +(SMM)](https://en.wikipedia.org/wiki/System_Management_Mode "wikipedia:System Management Mode"){.extiw}. + +### [Embedded Controllers]{#Embedded_Controllers .mw-headline} + +This section will cover firmware images as they apply to various +embedded controllers within the Intel GPU. + +#### [GuC]{#GuC .mw-headline} + +The Graphics micro (µ) Controller (GuC) is an embedded controller +contained within Intel\'s embedded and discrete graphics (DG\*) series +GPUs. + +##### [Hardware Architecture]{#Hardware_Architecture .mw-headline} + +*The following section is supported by +[igor-blue.github.io](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external +.text rel="nofollow"} (see reference +[1](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"}, +[2](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"}):* + +*\"The GuC - an embedded +[i486](https://www.wikiwand.com/en/I486){.external .text rel="nofollow"} +core that supports graphics scheduling, power management and firmware +attestation.\"* + +##### [Software Architecture]{#Software_Architecture .mw-headline} + +*The following section is supported by +[igor-blue.github.io](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external +.text rel="nofollow"} (see reference +[1](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"}, +[2](index.php/GPU_Firmware.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"}):* + +*\"The μOS kernel runs in 32-bit protected mode, with no paging and +old-style segments model (CS, DS, etc'). All code run in ring0. The OS +handles HW/SW exceptions and crashes, and supplies debugging and logging +services.\"* + +*\"It runs a single process - which initializes the system and then +waits for interrupts/events in a loop.\"* + +###### []{#GuC_Blob_Checksum_.26_Code_Signing}[GuC Blob Checksum & Code Signing]{#GuC_Blob_Checksum_&_Code_Signing .mw-headline} + +*\"The bootrom verifies the firmware with a digital signature using a +SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it +to SRAM and starts executing.\"* + +## [Nvidia]{#Nvidia .mw-headline} + +### [Firmware Images]{#Firmware_Images_2 .mw-headline} + +This section will cover firmware images used in Nvidia GPUs. + +### [Embedded Controllers]{#Embedded_Controllers_2 .mw-headline} + +This section will cover firmware images as they apply to various +embedded controllers within the Nvidia GPU. + +#### []{#Falcon_.2F_NV-RISCV}[Falcon / NV-RISCV]{#Falcon_/_NV-RISCV .mw-headline} + +The Fast Logic CONtroller (Falcon) and Nvidia RISC-V +([NV-RISCV](https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf){.external +.text rel="nofollow"}) processors run the NvOS. + +#### [GSP]{#GSP .mw-headline} + +The GPU System Processor (GSP) is an embedded controller used for +offload of the RM Core. + +The GSP runs [Library Operating System +(LibOS)](https://lwn.net/Articles/637658/){.external .text +rel="nofollow"}. + +##### []{#GSP_Initialization_.26_Offload}[GSP Initialization & Offload]{#GSP_Initialization_&_Offload .mw-headline} + +The [GSP is initialized multiple +times](index.php/GPU_Driver_Internals.html#Initialization_3){.external +.text rel="nofollow"} during the system\'s bring up and runtime. + +GSP offload may occur during: + +- Hardware bring up when a cached version of the RM Core is loaded + from SPI flash + +```{=html} + +``` +- During host driver bring up when the RM Core is offloaded by the + [OpenRM driver](index.php/OpenRM.html){.external .text + rel="nofollow"}. +- During guest driver bring up when the RM Core is offloaded. + + -------------------------------------------------------------------------------- ---------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Load Source Payload Notes + [SPI Flash](https://wiki.segger.com/SPI_Flash){.external .text rel="nofollow"} Cached RM Core Used as a fallback in case of no rm offload. + OpenRM RM Core This is the RM Core which was traditionally contained in the proprietary RM driver. + VGX Guest Guest RM Core Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via [gspHeapSize](https://github.com/NVIDIA/open-gpu-kernel-modules/blob/758b4ee8189c5198504cb1c3c5bc29027a9118a3/src/common/sdk/nvidia/inc/ctrl/ctrla081.h#L102){.external .text rel="nofollow"}?). + -------------------------------------------------------------------------------- ---------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + : Possible GSP Offloads + +#### [CMU]{#CMU .mw-headline} + +## [AMD]{#AMD .mw-headline} + +## []{#References_.28Talks_.26_Reading_Material.29}[References (Talks & Reading Material)]{#References_(Talks_&_Reading_Material) .mw-headline} + +1. [Security of the Intel Graphics Stack - Part 1 - + Introduction](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external + .text rel="nofollow"} +2. [Security of the Intel Graphics Stack - Part 2 - FW \<-\> + GuC](https://igor-blue.github.io/2021/02/24/graphics-part2.html){.external + .text rel="nofollow"} +3. [Firmware Security Realizations Part 3: SPI Write + Protections](https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/){.external + .text rel="nofollow"} +4. [Intel® FSP: Firmware Solutions for the Internet of + Things](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/fsp-firmware-solutions-iot-video.html){.external + .text rel="nofollow"} +::: + +::: printfooter +Retrieved from +\"[https://open-iov.org/index.php?title=GPU_Firmware&oldid=23779](index.php%3Ftitle=GPU_Firmware&oldid=23779.html){dir="ltr"}\" +::: +::: + +::: {#catlinks .catlinks .catlinks-allhidden mw="interface"} +::: +::: +::: + +::: {#mw-navigation} +## Navigation menu + +::: {#mw-head} +### Personal tools {#p-personal-label .vector-menu-heading} + +::: vector-menu-content +- [[Log + in](https://open-iov.org/index.php?title=Special:UserLogin&returnto=GPU+Firmware&returntoquery=oldid%3D23779 "You are encouraged to log in; however, it is not mandatory [o]"){accesskey="o"}]{#pt-login} +::: + +::: {#left-navigation} +### Namespaces {#p-namespaces-label .vector-menu-heading} + +::: vector-menu-content +- [[Page](index.php/GPU_Firmware.html "View the content page [c]"){accesskey="c"}]{#ca-nstab-main} +- [[Discussion](https://open-iov.org/index.php?title=Talk:GPU_Firmware&action=edit&redlink=1 "Discussion about the content page (page does not exist) [t]"){rel="discussion" + accesskey="t"}]{#ca-talk} +::: + +### Variants [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-variants-label .vector-menu-heading} + +::: vector-menu-content +::: +::: + +::: {#right-navigation} +### Views {#p-views-label .vector-menu-heading} + +::: vector-menu-content +- [[Read](index.php/GPU_Firmware.html)]{#ca-view} +- [[View + source](index.php%3Ftitle=GPU_Firmware&action=edit.html "This page is protected. + You can view its source [e]"){accesskey="e"}]{#ca-viewsource} +- [[View + history](index.php%3Ftitle=GPU_Firmware&action=history.html "Past revisions of this page [h]"){accesskey="h"}]{#ca-history} +::: + +### More [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-cactions-label .vector-menu-heading} + +::: vector-menu-content +::: + +::: {#p-search .vector-search-box role="search"} +
+ +### Search + +::: {#simpleSearch search-loc="header-navigation"} +::: + +
+::: +::: +::: + +::: {#mw-panel} +::: {#p-logo role="banner"} +[](images/archive/c/c3/20221214193624!I915_Scheduling_Events_and_Requests.png.html "Visit the main page"){.mw-wiki-logo} +::: + +### Navigation {#p-navigation-label .vector-menu-heading} + +::: vector-menu-content +- [[Main + page](images/archive/c/c3/20221214193624!I915_Scheduling_Events_and_Requests.png.html "Visit the main page [z]"){accesskey="z"}]{#n-mainpage-description} +- [[Recent + changes](https://open-iov.org/index.php/Special:RecentChanges "A list of recent changes in the wiki [r]"){accesskey="r"}]{#n-recentchanges} +- [[Random + page](index.php/Special:Random.html "Load a random page [x]"){accesskey="x"}]{#n-randompage} +- [[Help about + MediaWiki](https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents)]{#n-help-mediawiki} +::: + +### Tools {#p-tb-label .vector-menu-heading} + +::: vector-menu-content +- [[What links + here](index.php/Special:WhatLinksHere/GPU_Firmware.html "A list of all wiki pages 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policy")]{#footer-places-privacy} +- [[About + Open-IOV](index.php/Open-IOV:About.html "Open-IOV:About")]{#footer-places-about} +- [[Disclaimers](https://open-iov.org/index.php/Open-IOV:General_disclaimer "Open-IOV:General disclaimer")]{#footer-places-disclaimer} + +```{=html} + +``` +- [[![Powered by + MediaWiki](resources/assets/poweredby_mediawiki_88x31.png){srcset="resources/assets/poweredby_mediawiki_132x47.png 1.5x, resources/assets/poweredby_mediawiki_176x62.png 2x" + width="88" height="31" + loading="lazy"}](https://www.mediawiki.org/)]{#footer-poweredbyico} diff --git a/wiki/GPU_SBOM.md b/wiki/GPU_SBOM.md new file mode 100644 index 0000000..b03a4d0 --- /dev/null +++ b/wiki/GPU_SBOM.md @@ -0,0 +1,258 @@ +::: {#mw-page-base .noprint} +::: + +::: {#mw-head-base .noprint} +::: + +::: {#content .mw-body role="main"} +[]{#top} + +::: {#siteNotice} +::: + +::: mw-indicators +::: + +# GPU Software Bill Of Materials (SBOM) {#firstHeading .firstHeading} + +::: {#bodyContent .vector-body} +::: {#siteSub .noprint} +From Open-IOV +::: + +::: {#contentSub} +::: {.mw-revision .warningbox} +::: {#mw-revision-info} +Revision as of 14:58, 13 June 2023 by +[Arthur](./index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html "User:Arthur (page does not exist)"){.new +.mw-userlink} +[([talk](./index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html "User talk:Arthur (page does not exist)"){.new +.mw-usertoollinks-talk} \| +[contribs](index.php/Special:Contributions/Arthur.html "Special:Contributions/Arthur"){.mw-usertoollinks-contribs})]{.mw-usertoollinks} +[(Updated Nvidia VGX vGPU version to 15.2 in GPU SBOM.)]{.comment} +::: + +::: {#mw-revision-nav} +([diff](https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23786 "GPU Software Bill Of Materials (SBOM)")) +[← Older +revision](https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&direction=prev&oldid=23786 "GPU Software Bill Of Materials (SBOM)") +\| Latest revision (diff) \| Newer revision → (diff) +::: +::: +::: + +::: {#contentSub2} +::: + +::: {#jump-to-nav} +::: + +[Jump to +navigation](index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23786.html#mw-head){.mw-jump-link} +[Jump to +search](index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23786.html#searchInput){.mw-jump-link} + +::: {#mw-content-text .mw-body-content .mw-content-ltr lang="en" dir="ltr"} +::: mw-parser-output +This page will keep a running list of components used to achieve GPU +Virtualization. + +> An absence of critical technical documentation has historically slowed +> growth and adoption of developer ecosystems for GPU virtualization. +> +> This +> [CC-BY-4.0](https://creativecommons.org/licenses/by/4.0/){.external +> .text rel="nofollow"} licensed content can either be used with +> attribution, or used as inspiration for new documentation, created by +> GPU vendors for public commercial distribution as developer +> documentation. +> +> Where possible, this documentation will clearly label dates and +> versions of observed-but-not-guaranteed behaviour vs. +> vendor-documented stable interfaces/behaviour with guarantees of +> forward or backward compatibility. + + ------------- ----------------------------------------------------------------------------------------------------------------------------------------------- ------------- ----------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Vendor Component Description Version OSS or Blob Filesize Vendor Docs Release Date Interfaces / APIs Notes + Microsoft Indirect Display Driver (IDD) Driver [OSS](https://github.com/Microsoft/Windows-driver-samples/tree/main/video/IndirectDisplay){.external .text rel="nofollow"} [Indirect Display Driver Overview](https://learn.microsoft.com/en-us/windows-hardware/drivers/display/indirect-display-driver-model-overview){.external .text rel="nofollow"} [UMDF](https://learn.microsoft.com/en-us/windows-hardware/drivers/wdf/overview-of-the-umdf){.external .text rel="nofollow"}, [KMDF](https://learn.microsoft.com/en-us/windows-hardware/drivers/kernel/){.external .text rel="nofollow"} The Indirect Display Driver (IDD) enables GPUs to render graphics at arbitrary resolutions without a physical display connected on Windows OS systems. + RedHat vfio_pci Driver 6.2-rc1 [OSS](https://github.com/torvalds/linux/tree/master/drivers/vfio/pci){.external .text rel="nofollow"} in-kernel [RedHat](https://access.redhat.com/documentation/en-us/red_hat_enterprise_linux/5/html/virtualization/chap-virtualization-pci_passthrough){.external .text rel="nofollow"}, [kernel.org](https://docs.kernel.org/driver-api/vfio.html){.external .text rel="nofollow"} 2022.12.15 [irqfd](index.php/Virtual_I/O_Internals.html#Instruction_Execution){.external .text rel="nofollow"}, [ioeventfd](index.php/Virtual_I/O_Internals.html#Instruction_Execution){.external .text rel="nofollow"}, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"} Reference VFIO Stub driver used for discrete assignment of IO, and assignment of some SR-IOV-backed vGPU devices into virtual machines. This driver is commonly replaced with a vendor built VFIO interface with differing memory management and/or page pinning mechanisms which are specific to the vGPU software internals. + Mediated Core (mdev.ko) Driver 6.2-rc1 OSS 0.044 MB [kernel.org](https://docs.kernel.org/driver-api/vfio-mediated-device.html){.external .text rel="nofollow"} 2016.xx.xx [irqfd](index.php/Virtual_I/O_Internals.html#Instruction_Execution){.external .text rel="nofollow"}, [ioeventfd](index.php/Virtual_I/O_Internals.html#Instruction_Execution){.external .text rel="nofollow"}, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"}, [Type 1 IOMMU](index.php/Virtual_I/O_Internals.html#Mediated_DMA_Translations){.external .text rel="nofollow"} The Mediated Core driver provides a common interface for mediated device management that can be used by drivers of different devices. It is an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment (based on VFIO). + guest communication daemon Daemon 0.1.0 [OSS](https://){.external .text rel="nofollow"} [](){.external .text rel="nofollow"} 2023.02.08 [Virtio-Serial](https://fedoraproject.org/wiki/Features/VirtioSerial){.external .text rel="nofollow"}, CLI Handles IO to and from guests and the host using Virtio-Serial to handle multiple different guest modules. + mdev management CLI 1.0 [OSS](https://){.external .text rel="nofollow"} 0.084 MB [](){.external .text rel="nofollow"} 2023.01.06 CLI, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"}, [RMAPI](index.php/GPU_Driver_Internals.html#RM_API){.external .text rel="nofollow"}, [Mediated Core](index.php/Virtual_I/O_Internals.html#Mediated_Core){.external .text rel="nofollow"} Configures the the [nvidia-vgpu-mgr](index.php/GPU_Driver_Internals.html#nvidia-vgpu-mgr){.external .text rel="nofollow"} process. + Intel i915 SR-IOV Driver [5.15](https://github.com/intel/linux-intel-lts/tree/5.15/ADL-linux-ER){.external .text rel="nofollow"} OSS in-kernel Intel\'s open source GPU driver for [GuC](index.php/GPU_Firmware.html#GuC){.external .text rel="nofollow"}-equipped graphics accelerators. + [GuC](index.php/GPU_Firmware.html#GuC){.external .text rel="nofollow"} μOS Firmware Blob IOMMU Interrupts, Power Management Interrupts, [GTT](index.php/GPU_Driver_Internals.html#GTT_(Graphics_Translation_Table)){.external .text rel="nofollow"} Handles scheduling, and power management. + HuC [GTT](index.php/GPU_Driver_Internals.html#GTT_(Graphics_Translation_Table)){.external .text rel="nofollow"} Handles video encoding/decoding. + [Display Virtualization for Windows OS](index.php/GPU_Driver_Internals.html#Display_Surface_Virtualization_2){.external .text rel="nofollow"} Driver [791](https://github.com/intel/Display-Virtualization-for-Windows-OS/releases/){.external .text rel="nofollow"} [OSS](https://github.com/intel/Display-Virtualization-for-Windows-OS){.external .text rel="nofollow"} [github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt](https://github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt){.external .text rel="nofollow"} [udmabuf](https://github.com/ikwzm/udmabuf){.external .text rel="nofollow"}, [UMDF](https://learn.microsoft.com/en-us/windows-hardware/drivers/wdf/overview-of-the-umdf){.external .text rel="nofollow"}, [KMDF](https://learn.microsoft.com/en-us/windows-hardware/drivers/kernel/){.external .text rel="nofollow"} Intel\'s \'Display Virtualization for Windows OS\' provides a virtual pixel surface used for hardware graphics rendering using Microsoft\'s open source \'Indirect Display Driver (IDD)\'. Display virtualization for Windows OS makes use of display memory sharing primitives provided in-driver by the i915 host. + Nvidia [OpenRM](index.php/OpenRM.html "OpenRM") Driver 525.85.12 OSS [github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md](https://github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md){.external .text rel="nofollow"} 2023.01.31 Nvidia\'s open source GPU driver for [GSP](index.php/GPU_Firmware.html#GSP){.external .text rel="nofollow"}-equipped graphics accelerators. + [GSP](index.php/GPU_Firmware.html#GSP){.external .text rel="nofollow"} RM (uproc) Firmware Blob 2023.01.31 RPC Embedded firmware based on [LibOS](https://lwn.net/Articles/637658/){.external .text rel="nofollow"} containing the [RM Core](index.php/GPU_Driver_Internals.html#RM_Core){.external .text rel="nofollow"}. + Falcon/NvRISC (uproc) FBIF (Frame Buffer Interface) / GMMU Embedded firmware which handles many aspects of the device including configuring the GPU\'s GMMU controller. + nvidia-vgpud Daemon [v15.2](https://docs.nvidia.com/grid/15.0/whats-new-vgpu/index.html){.external .text rel="nofollow"} Blob 0.108 MB [docs.nvidia.com/grid](https://docs.nvidia.com/grid/index.html){.external .text rel="nofollow"} 2023.01.xx CLI, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"}, [RMAPI](index.php/GPU_Driver_Internals.html#RM_API){.external .text rel="nofollow"}, [Mediated Core](index.php/Virtual_I/O_Internals.html#Mediated_Core){.external .text rel="nofollow"} Configures the the [nvidia-vgpu-mgr](index.php/GPU_Driver_Internals.html#nvidia-vgpu-mgr){.external .text rel="nofollow"} process. + nvidia-vgpu-mgr 0.132 MB 2023.01.xx [vmiop](index.php/GPU_Driver_Internals.html#vmiop){.external .text rel="nofollow"}, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"}, [RMAPI](index.php/GPU_Driver_Internals.html#RM_API){.external .text rel="nofollow"}, [vRPC](index.php/GPU_Driver_Internals.html#Guest_kernel_(nvidia.ko)){.external .text rel="nofollow"}, pRPC, [Mediated Core](index.php/Virtual_I/O_Internals.html#Mediated_Core){.external .text rel="nofollow"} Handles IO to and from guest RM, host RM, and hardware. + libnvidia-vgpu.so Library 3.1 MB 2023.01.xx [vmiop](index.php/GPU_Driver_Internals.html#vmiop){.external .text rel="nofollow"}, [RMAPI](index.php/GPU_Driver_Internals.html#RM_API){.external .text rel="nofollow"}, [Mediated Core](index.php/Virtual_I/O_Internals.html#Mediated_Core){.external .text rel="nofollow"} Handles IO to and from guest RM, host RM, and hardware. Contains circular dependancies with [nvidia-vgpu-mgr](index.php/GPU_Driver_Internals.html#nvidia-vgpu-mgr){.external .text rel="nofollow"}. + nvidia-vgpu-vfio.ko Driver 0.108 MB 2023.01.xx [Type 1 IOMMU](index.php/Virtual_I/O_Internals.html#Mediated_DMA_Translations){.external .text rel="nofollow"}, [irqfd, ioeventfd](index.php/Virtual_I/O_Internals.html#Instruction_Execution){.external .text rel="nofollow"}, [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external .text rel="nofollow"}, [Mediated Core](index.php/Virtual_I/O_Internals.html#Mediated_Core){.external .text rel="nofollow"} Handles incremental memory mapping (non-page pinning per the standard vfio-pci driver). + ------------- ----------------------------------------------------------------------------------------------------------------------------------------------- ------------- ----------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------- ----------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + : Component Table + +## [More Information]{#More_Information .mw-headline} + +1. [Nvidia RISC-V + Story](https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf){.external + .text rel="nofollow"} +2. [](){.external .text + rel="nofollow"} +3. [Intel Graphics Programmer\'s Reference Manuals + (PRM)](https://01.org/linuxgraphics/documentation/hardware-specification-prms){.external + .text rel="nofollow"} +4. [i915: Hardware Contexts (and some bits about + batchbuffers)](https://bwidawsk.net/blog/2013/1/i915-hardware-contexts-and-some-bits-about-batchbuffers/){.external + .text rel="nofollow"} +5. [i915: The Global GTT Part + 1](https://bwidawsk.net/blog/2014/6/the-global-gtt-part-1/){.external + .text rel="nofollow"} +6. [i915: Aliasing PPGTT Part + 2](https://bwidawsk.net/blog/2014/6/aliasing-ppgtt-part-2/){.external + .text rel="nofollow"} +7. [i915: True PPGTT Part + 3](https://bwidawsk.net/blog/2014/7/true-ppgtt-part-3/){.external + .text rel="nofollow"} +8. [i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit + address space, GPU \"mirroring\", and yeah, something about relocs + too)](https://bwidawsk.net/blog/2014/7/future-ppgtt-part-4-dynamic-page-table-allocations-64-bit-address-space-gpu-mirroring-and-yeah-something-about-relocs-too/){.external + .text rel="nofollow"} +9. [i915: Security of the Intel Graphics Stack - Part 1 - + Introduction](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external + .text rel="nofollow"} +10. [i915: Security of the Intel Graphics Stack - Part 2 - FW \<-\> + GuC](https://igor-blue.github.io/2021/02/24/graphics-part2.html){.external + .text rel="nofollow"} +11. [i915: An Introduction to Intel GVT-g (with new + architecture)](https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf){.external + .text rel="nofollow"} +::: + +::: printfooter +Retrieved from +\"[https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials\_(SBOM)&oldid=23786](index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23786.html){dir="ltr"}\" +::: +::: + +::: {#catlinks .catlinks .catlinks-allhidden mw="interface"} +::: +::: +::: + +::: {#mw-navigation} +## Navigation menu + +::: {#mw-head} +### Personal tools {#p-personal-label .vector-menu-heading} + +::: vector-menu-content +- [[Log + in](https://open-iov.org/index.php?title=Special:UserLogin&returnto=GPU+Software+Bill+Of+Materials+%28SBOM%29&returntoquery=oldid%3D23786 "You are encouraged to log in; however, it is not mandatory [o]"){accesskey="o"}]{#pt-login} +::: + +::: {#left-navigation} +### Namespaces {#p-namespaces-label .vector-menu-heading} + +::: vector-menu-content +- [[Page](index.php/GPU_Software_Bill_Of_Materials_(SBOM).html "View the content page [c]"){accesskey="c"}]{#ca-nstab-main} +- [[Discussion](https://open-iov.org/index.php?title=Talk:GPU_Software_Bill_Of_Materials_(SBOM)&action=edit&redlink=1 "Discussion about the content page (page does not exist) [t]"){rel="discussion" + accesskey="t"}]{#ca-talk} +::: + +### Variants [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-variants-label .vector-menu-heading} + +::: vector-menu-content +::: +::: + +::: {#right-navigation} +### Views {#p-views-label .vector-menu-heading} + +::: vector-menu-content +- [[Read](index.php/GPU_Software_Bill_Of_Materials_(SBOM).html)]{#ca-view} +- [[View + source](index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=edit.html "This page is protected. + You can view its source [e]"){accesskey="e"}]{#ca-viewsource} +- [[View + history](index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html "Past revisions of this page [h]"){accesskey="h"}]{#ca-history} +::: + +### More [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-cactions-label .vector-menu-heading} + +::: vector-menu-content +::: + +::: {#p-search .vector-search-box role="search"} +
+ +### Search + +::: {#simpleSearch search-loc="header-navigation"} +::: + +
+::: +::: +::: + +::: {#mw-panel} +::: {#p-logo role="banner"} +[](images/archive/c/c3/20221214193624!I915_Scheduling_Events_and_Requests.png.html "Visit the main page"){.mw-wiki-logo} +::: + +### Navigation {#p-navigation-label .vector-menu-heading} + +::: vector-menu-content +- [[Main + page](images/archive/c/c3/20221214193624!I915_Scheduling_Events_and_Requests.png.html "Visit the main page [z]"){accesskey="z"}]{#n-mainpage-description} +- [[Recent + changes](https://open-iov.org/index.php/Special:RecentChanges "A list of recent changes in the wiki [r]"){accesskey="r"}]{#n-recentchanges} +- [[Random + page](index.php/Special:Random.html "Load a random page [x]"){accesskey="x"}]{#n-randompage} +- [[Help about + MediaWiki](https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents)]{#n-help-mediawiki} +::: + +### Tools {#p-tb-label .vector-menu-heading} + +::: vector-menu-content +- [[What links + here](index.php/Special:WhatLinksHere/GPU_Software_Bill_Of_Materials_(SBOM).html "A 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28.5 MB +- **Format**: ELF, RV64IMAC (RISC-V 64-bit) +- **Base Address**: 0x04000000 +- **MD5**: `13ce12a392a31eeb79a2e6ebd3a4a93a` + +## Architecture Overview + +### Memory Map +``` +0x04000000 - 0x05FFFFFF : Code + Read-only data (~32 MB) +0x04296040 : Global state structure (cRam0000000004296048) +0x0429B750 : Error/status registers +0x041DC350 : Stack canary / frame guard +0x429B000 - 0x429BFFF : Memory allocator arena (0x429B450 = alloc entry) +``` + +### Calling Convention (RISC-V RV64IMAC) +| Register | Purpose | +|----------|---------| +| s0 (x8) | Frame pointer | +| s1 (x9), s4 (x12), s10 (x20) | RA save locations | +| s1-s11 | Callee-saved (pushed to stack) | +| a0-a7 | Arguments / return values | +| sp | Stack pointer (grows down, frames 96-560 bytes) | + +--- + +## RPC System + +### 12 RPC Types (Jump Table at 0x059BFEB0) + +| Type | Name | Handler A | Handler B | Dispatcher | +|------|------|-----------|-----------|------------| +| 0x01 | ALLOC | — | — | Primary | +| 0x02 | FREE | — | — | Primary | +| 0x03 | MAP | 0x05766AB7 | 0x05778A37 | Secondary | +| 0x04 | UNMAP | 0x057669B7 | 0x05779937 | Primary + Secondary | +| 0x05 | PIN | 0x057664B7 | 0x0577A3B7 | Secondary | +| 0x06 | UNPIN | 0x057682B7 | 0x05779FB7 | Secondary | +| 0x07 | SCHEDULE | 0x05767F37 | 0x0575AEB7 | Primary + Secondary | +| 0x08 | YIELD | 0x0575AE37 | 0x05767337 | Secondary | +| 0x09 | NOTIFY | 0x0577C8B7 | 0x05767837 | Secondary | +| 0x0A | BAR_TRAP | 0x057675B7 | — | Secondary | +| 0x0B | MIGRATE | — | — | Primary | +| 0x0C | DEBUG | — | — | — | + +### Primary Dispatcher (0x057A1AC0) +``` +Entry: FUN_ram_057a1ac0(param_1, param_2, param_3, param_4, *out_id, *out_a, *out_b, *out_c) +``` +- Extracts RPC type from `param_1` +- Validates against max type (bgeu x12, x13 checks for types 11 and 13) +- MIGRATE (0x0B) branches at 0x057A1BDC and 0x057A1D54 +- Indexes into 32-entry jump table at **0x057A3AD8** + +#### Primary Dispatcher Sub-Command Jump Table (0x057A3AD8) + +| Subcmd | Target | Decompiled | Description | +|--------|--------|------------|-------------| +| 0 | 0x057A1DB4 | ✅ | Returns ID=0x40 | +| 1 | 0x057A1C18 | ✅ | | +| 2 | 0x057A39FC | ✅ | | +| 3 | 0x057A1BCC | ✅ | | +| 4 | 0x057A1EF4 | ✅ | | +| 5 | 0x057A1E94 | ✅ | | +| 6 | 0x057A3A28 | ✅ | | +| 7 | 0x057A3A60 | ✅ | | +| 8 | 0x057A1C6C | ✅ | | +| 9 | 0x057A3A48 | ✅ | | +| 10 | 0x057A1F6C | ✅ | | +| 11 | 0x057A3AC4 | ✅ | | +| 12 | 0x057A1E10 | ✅ | | +| 13 | 0x057A3A90 | ✅ | | +| 14 | 0x057A39BC | ✅ | | +| 15 | 0x057A3AAC | ✅ | | +| 16 | 0x057A3A78 | ✅ | | +| 17 | 0x057A1CCC | ✅ | | +| 18 | 0x057A39E0 | ✅ | | +| 19 | 0x057A1FA8 | ✅ | | +| 20 | 0x057A2094 | ✅ | | +| 21 | 0x057A2074 | ✅ | | +| 22 | 0x057A2044 | ✅ | | +| 23 | 0x057A20D4 | ✅ | | +| 24 | 0x057A20B4 | ✅ | | +| 25 | 0x057A1FC8 | ✅ | | +| 26 | 0x057A2008 | ✅ | | +| 27 | 0x057A1FE8 | ✅ | | +| 28 | 0x057A2024 | ✅ | | +| 29 | 0x057A219C | ✅ | | +| 30 | 0x057A20FC | ✅ | | +| 31 | 0x057A214C | ✅ | | + +**Pattern**: Each sub-command returns a constant ID in `*out_id` (e.g., 0x10, 0x14, 0x40) and echoes input params to output pointers. + +### Secondary Dispatcher (0x04ED39DC) +- Branch-based dispatch for ALL 11 RPC types +- 141 KB decompiled — handles MAP, UNMAP, PIN, UNPIN, SCHEDULE, YIELD, NOTIFY, BAR_TRAP +- Entry: 0x04ED34B8 (PIN handler from secondary) + +### Specialized Main Handlers + +| Function | Address | Size | Role | +|----------|---------|------|------| +| `rpc_alloc_main` | 0x057E94EC | 40 KB | Core ALLOC implementation | +| `rpc_schedule_main` | 0x051EFBF4 | 1.8 KB | Core SCHEDULE implementation | +| `rpc_bar_trap_handler` | 0x04CB8188 | 40 KB | BAR1 emulation | +| `rpc_pin_handler` | 0x04ED34B8 | — | PIN from secondary dispatcher | + +--- + +## BAR Emulation (RPC 0x0A) + +### Handler: 0x04CB8188 (40 KB) +**Strings Referenced**: +- `BAR1` at 0x0406570E, 0x04085DE0 +- `Bar1Rest` at 0x040656DA +- `ForceBarAccess` at 0x040656F2 +- `Bar1Aperture` at 0x04065722 + +**Key Operations**: +- Memory allocation via `UNK_ram_058A1A9C` at arena 0x429B450 +- Buffer management with 0x429B428 (cache/flush) +- Error codes: 0x51 (OOM), 0x1E (timeout), 0x1D, 0x1F, 0x25, 0x37, 0x56 +- Uses `ebreak` for fatal errors with logging at 0x05AB7DA0 +- Stack canary check against 0x041DC350 + +**Integration Point for vGPU-IO**: +```c +// Register BAR trap handler at 0x04CB8188 +// Monitor BAR1, Bar1Rest, ForceBarAccess, Bar1Aperture registers +// Emulate BAR1 aperture/size for guest VF +``` + +--- + +## WPR Management + +### Handlers: 0x04F00B0C, 0x04F00C78 (62 KB each) + +**String References (60 locations)**: +- `WPR_WRITE_COMPLETE`, `WPR_READ_COMPLETE` +- `WPR_WRITE_TIMEOUT`, `WPR_READ_TIMEOUT` +- `NV_WPR_WRITE_COMPLETE`, `NV_WPR_READ_COMPLETE` +- `NV_WPR_WRITE_TIMEOUT`, `NV_WPR_READ_TIMEOUT` + +**Key Operations**: +- VBIOS parsing (checks for `0xAA55`, `0x57464F4E` "WFON", `0x5746564E` "WFVN") +- Memory allocation at 0x429B450 +- DMA/copy via `UNK_ram_0588F9C4`, `UNK_ram_05AEC86C` +- State machine with completion/timeout handling +- Error codes: 0x1E-0x25, 0x37, 0x51, 0x56, 0xFFFF + +**Integration Point for vGPU-IO**: +```c +// Hook WPR completion callbacks from string reference locations +// Implement NV_WPR_WRITE/READ_COMPLETE/TIMEOUT notifications +// Manage WPR regions for guest VF memory isolation +``` + +--- + +## Migration Protocol (RPC 0x0B) + +### Dual Jump Tables + +#### Table 1: 0x04179ED8 (Primary dispatcher MIGRATE branch at 0x057A1BDC) +| Index | Target | Decompiled | +|-------|--------|------------| +| 0 | 0x057A2344 | ✅ Returns ID=0x14, reads flag at `in_t1+0x7F9` | +| 1 | 0x057A2320 | ✅ | +| 2 | 0x057A230C | ✅ | +| 3 | 0x057A22F8 | ✅ Returns ID=0x10 | +| 4 | 0x057A2388 | ✅ | +| 5 | 0x057A23D8 | ✅ | +| 6 | 0x057A23AC | ✅ | +| 7 | 0x057A2478 | ✅ | +| 8 | 0x057A2428 | ✅ | +| 9 | 0x057A2454 | ✅ | +| 10 | 0x057A2404 | ✅ | +| 11 | 0x057A2364 | ✅ | +| 12 | 0x057A1F3C | (dup) | +| 13 | 0x057A299C | | +| 14 | 0x057A1F3C | (dup) | +| 15 | 0x057A1F3C | (dup) | + +#### Table 2: 0x04179FBC (Primary dispatcher MIGRATE branch at 0x057A1D5C) +| Index | Target | Decompiled | +|-------|--------|------------| +| 0 | 0x057A257C | ✅ | +| 1 | 0x057A25E4 | ✅ | +| 2 | 0x057A24EC | ✅ | +| 3 | 0x057A2608 | ✅ | +| 4 | 0x057A2534 | ✅ | +| 5 | 0x057A25C0 | ✅ | +| 6 | 0x057A24A4 | ✅ | +| 7 | 0x057A259C | ✅ | +| 8 | 0x057A2510 | ✅ | +| 9 | 0x057A2558 | ✅ | +| 10 | 0x057A24C8 | ✅ | +| 11 | 0x057A262C | ✅ | +| 12 | 0x057A345C | ✅ | +| 13 | 0x057A36D8 | ✅ | +| 14 | 0x057A35D8 | ✅ | +| 15 | 0x057A3658 | ✅ | + +**Pattern**: Migration sub-commands follow same descriptor pattern as primary dispatcher — return constant ID, echo params. + +--- + +## Entry Point & Boot Sequence + +### 0x04009000 (573 bytes) +- Initializes global state at 0x04296040 +- Sets up stack canary at 0x041DC350 +- Configures memory allocator arena at 0x429B450 +- Registers RPC dispatchers +- Jumps to main scheduler loop + +--- + +## Decompiled Output Directory + +``` +$OPEN_IOV_ROOT/firmware/570-GSP/decompiled/ +├── entry_ram_04009000.c # Boot entry +├── FUN_ram_04cb8188_ram_04cb8188.c # BAR trap handler (40 KB) +├── FUN_ram_04cc58f8_ram_04cc58f8.c # Secondary dispatcher (141 KB) +├── FUN_ram_04d00a18_ram_04d00a18.c # ALLOC-dominant (142 KB) +├── FUN_ram_04ed39dc_ram_04ed39dc.c # Secondary dispatcher (141 KB) +├── FUN_ram_04f00b0c_ram_04f00b0c.c # WPR handler 1 (62 KB) +├── FUN_ram_04f00c78_ram_04f00c78.c # WPR handler 2 (62 KB) +├── FUN_ram_051efbf4_ram_051efbf4.c # SCHEDULE main (1.8 KB) +├── FUN_ram_054a7de0_ram_054a7de0.c # ALLOC-dominant (67 KB) +├── FUN_ram_05723ef4_ram_05723ef4.c # Tertiary dispatcher (13 KB) +├── FUN_ram_057a1ac0_ram_057a1ac0.c # Primary dispatcher (558 B) +├── FUN_ram_057a1bcc_ram_057a1bcc.c ... # 32 sub-commands (~550 B each) +├── FUN_ram_057e94ec_ram_057e94ec.c # ALLOC main (40 KB) +├── FUN_ram_059be7f4_ram_059be7f4.c # RPC jump table (4.9 KB) +├── FUN_ram_057664b7_ram_057664b7.c ... # MAP/PIN/UNPIN/SCHED/YIELD/NOTIFY handlers +└── FUN_ram_057a22f8_ram_057a22f8.c ... # 28 migration handlers +``` + +--- + +## vGPU-IO Integration Checklist + +### Memory Management (ALLOC/FREE/MAP/UNMAP) +- [ ] Implement kernel RPC client calling 0x057A1AC0 +- [ ] Parse sub-command descriptors from 0x057A3AD8 jump table +- [ ] Hook ALLOC main at 0x057E94EC for vGPU memory carve-out + +### Page Pinning (PIN/UNPIN) +- [ ] Call secondary dispatcher PIN at 0x04ED34B8 +- [ ] Implement UNPIN via 0x057682B7 / 0x05779FB7 + +### Scheduling (SCHEDULE/YIELD) +- [ ] Use 0x05767F37 / 0x0575AEB7 / 0x051EFBF4 for vCPU scheduling +- [ ] Implement YIELD at 0x0575AE37 / 0x05767337 + +### BAR Emulation (BAR_TRAP) +- [ ] Register handler at 0x04CB8188 +- [ ] Emulate BAR1/Bar1Rest/ForceBarAccess/Bar1Aperture for VF +- [ ] Monitor 0x429B450 allocator for BAR backing store + +### WPR Management +- [ ] Hook completion callbacks from string refs (0x04F00B0C, 0x04F00C78) +- [ ] Implement NV_WPR_* notification forwarding to guest +- [ ] Manage WPR regions per-VF for isolation + +### Migration (MIGRATE) +- [ ] Implement dual jump table dispatch (0x04179ED8, 0x04179FBC) +- [ ] Handle 28 migration sub-commands +- [ ] Coordinate with guest VF live migration protocol + +--- + +## Tools & Scripts + +| Script | Purpose | +|--------|---------| +| `DecompileFunctions.java` | Ghidra headless decompilation | +| `trace_all_subsystems.py` | Binary analysis: WPR/BAR/Migration strings, jump tables | +| `gsp-fwimage-570.144/` | Ghidra project directory | + +### Ghidra Usage +```bash +/snap/ghidra/current/ghidra/support/analyzeHeadless \ + /path/to/project gsp-analysis \ + -import gsp-570.144.fwimage.bin \ + -noanalysis \ + -postScript DecompileFunctions.java \ + 0xADDRESS1,0xADDRESS2,... +``` + +--- + +## References +- Handoff: `$OPEN_IOV_ROOT/../Handoff-vGPU-IO.md` +- RPC Map: `$OPEN_IOV_ROOT/firmware/570-GSP/RPC_HANDLER_MAP.md` +- Final Report: `$OPEN_IOV_ROOT/firmware/570-GSP/FINAL_REPORT.md` +- Analysis Results: `$OPEN_IOV_ROOT/firmware/570-GSP/analysis_results.json` \ No newline at end of file diff --git a/wiki/GSP-RPC-Emulation.md b/wiki/GSP-RPC-Emulation.md new file mode 100644 index 0000000..2e6849a --- /dev/null +++ b/wiki/GSP-RPC-Emulation.md @@ -0,0 +1,227 @@ +# GSP vGPU RPC Emulation + +## Overview + +Open-IOV includes **emulation mode** that allows operation with unmodified consumer/OpenRM GSP firmware by emulating missing vGPU RPC handlers locally in kernel and userspace. + +## Problem + +The NVIDIA GSP firmware on consumer drivers (550.163.01) and OpenRM lacks the vGPU-specific RPC handlers that exist only in the GRID host driver firmware: + +| Handler | Address | Size | Purpose | +|---------|---------|------|---------| +| BAR Trap | 0x04CB8188 | 40KB | BAR1/ForceBarAccess/Aperture | +| WPR Handler 1 | 0x04F00B0C | 62KB | Write/Read Protect Regions | +| WPR Handler 2 | 0x04F00C78 | 62KB | Write/Read Protect Regions | +| Migration | 0x04179ED8/0x04179FBC | - | Live migration | + +Without these handlers, VF creation times out at BAR configuration (RPC to 0x04CB8188). + +## Solution: Emulation Mode + +Emulation mode intercepts vGPU RPC calls and handles them locally instead of sending to GSP: + +``` +┌─────────────────────────────────────────────────────────────────┐ +│ Emulation Architecture │ +├─────────────────────────────────────────────────────────────────┤ +│ │ +│ Userspace App (libiov.so) │ +│ │ │ +│ ▼ │ +│ ┌─────────────────┐ ┌─────────────────┐ │ +│ │ Kernel IOCTL │────▶│ Emulation Layer │ │ +│ │ Handler │ │ (kernel) │ │ +│ └─────────────────┘ └────────┬────────┘ │ +│ │ │ +│ ┌───────────────┼───────────────┐ │ +│ ▼ ▼ ▼ │ +│ ┌──────────┐ ┌──────────┐ ┌──────────┐ │ +│ │ BAR Emu │ │ WPR Emu │ │ Mem Emu │ │ +│ │ (kernel) │ │ (kernel) │ │ (kernel) │ │ +│ └──────────┘ └──────────┘ └──────────┘ │ +│ │ │ │ │ +│ ▼ ▼ ▼ │ +│ ┌──────────────────────────────────────────┐ │ +│ │ Userspace Emulator (libiov.so) │ │ +│ │ rpc_emu_bar_*(), rpc_emu_wpr_*() │ │ +│ └──────────────────────────────────────────┘ │ +│ │ +└─────────────────────────────────────────────────────────────────┘ +``` + +## Auto-Detection (Default Behavior) + +**Emulation mode is ON by default** and auto-detects at driver load: + +1. Driver initializes RPC communication with GSP +2. Sends test `BAR_TRAP` RPC (non-destructive READ) +3. **If GSP responds** (ret=0) → vGPU handlers present → **emulation disabled** +4. **If GSP times out/errors** (ret=-ETIMEDOUT/-EIO/-ENODEV) → handlers missing → **emulation enabled** + +``` +dmesg output: + gsp-vgpu: Auto-detecting GSP vGPU RPC handler support... + gsp-vgpu: GSP lacks vGPU RPC handlers (ret=-110) - ENABLING emulation mode + # or + gsp-vgpu: GSP has vGPU RPC handlers - DISABLING emulation mode +``` + +## Module Parameters + +| Parameter | Type | Default | Description | +|-----------|------|---------|-------------| +| `emulation_mode` | bool | 1 (ON) | Current state (read-only, shows auto-detected value) | +| `emulation_override` | bool | 0 (auto) | Override: 1=force emulation ON, 0=force emulation OFF | + +```bash +# Default: auto-detect +sudo insmod gsp-vgpu.ko firmware_name=gsp-570.144.fwimage.bin + +# Force emulation ON (testing with GRID GSP) +sudo insmod gsp-vgpu.ko firmware_name=gsp-570.144.fwimage.bin emulation_override=1 + +# Force emulation OFF (requires GRID GSP) +sudo insmod gsp-vgpu.ko firmware_name=gsp-570.144.fwimage.bin emulation_override=0 +``` + +## Emulated RPC Handlers + +### Kernel Emulation (`driver/`) + +| RPC Type | Handler | Emulation | +|----------|---------|-----------| +| `GSP_RPC_ALLOC` (0x01) | `gsp_vf_mem_alloc()` | Synthetic handles/VAs from local counter | +| `GSP_RPC_PIN` (0x05) | `gsp_vf_mem_pin()` | Synthetic DMA addresses from local counter | +| `GSP_RPC_MAP` (0x03) | `gsp_vf_mem_map()` | Identity map (return requested VA) | +| `GSP_RPC_BAR_TRAP` (0x0A) | `gsp_bar_trap_handler()` | Local aperture/force_access state | +| `GSP_RPC_MAP` (WPR) | `gsp_vf_wpr_protect()` | Local WPR region list | +| `GSP_RPC_UNMAP` (WPR) | `gsp_vf_wpr_unprotect()` | Local WPR region removal | + +### Userspace Emulation (`userspace/lib/rpc_emulator.c`) + +| Function | Purpose | +|----------|---------| +| `rpc_emu_bar_config()` | Local aperture offset/size + backing store | +| `rpc_emu_bar_force_access()` | Local force_access state | +| `rpc_emu_bar_save/restore()` | Migration state serialization | +| `rpc_emu_wpr_protect_write/read()` | Local WPR region tracking | +| `rpc_emu_wpr_unprotect()` | Local WPR region removal | +| `rpc_emu_wpr_set_timeout()` | Local timeout tracking | +| `rpc_emu_wpr_check_access()` | Access violation detection | + +## Emulation Data Structures + +### BAR State (per VF) +```c +struct gsp_bar_state { + uint64_t aperture_offset; // BAR1 aperture base + uint64_t aperture_size; // BAR1 aperture size (max 256KB) + bool force_access; // ForceBarAccess enabled + uint32_t force_vf; // VF holding force access + void *backing_store; // Emulated BAR memory + size_t backing_size; // Backing store size +}; +``` + +### WPR Region List (per VF) +```c +struct gsp_wpr_region { + struct list_head list; + uint64_t base; // Region base address + uint64_t size; // Region size + uint32_t flags; // GSP_WPR_WRITE/READ/EXECUTE + uint32_t vf_id; // Owning VF + void (*completion_cb)(...); // Write/read complete callback + void (*timeout_cb)(...); // Timeout callback + uint64_t timeout_ns; // Timeout in nanoseconds +}; +``` + +### Userspace Emulator State +```c +struct emu_bar_state { + uint64_t aperture_offset; + uint64_t aperture_size; + bool force_access; + uint32_t force_vf; + void *backing_store; + size_t backing_size; + pthread_mutex_t lock; +}; + +struct emu_wpr_state { + struct emu_wpr_region *regions; // Linked list + pthread_mutex_t lock; +}; +``` + +## Fallback Logic + +Userspace library (`libiov.so`) implements fallback: + +```c +vgpu_error_t vgpu_bar_config(vgpu_vf_t vf, uint64_t offset, uint64_t size) { + // 1. Try kernel IOCTL (sends RPC to GSP) + ret = ioctl(fd, GSP_IOCTL_BAR_CONFIG, &args); + + // 2. If GSP lacks handlers (ENOTSUP/ETIMEDOUT/EIO), use emulator + if (ret < 0 && dev->emulation_enabled && + (errno == ENOTSUP || errno == ETIMEDOUT || errno == EIO)) { + return rpc_emu_bar_config(vf->id, offset, size); + } + + return map_errno(errno); +} +``` + +## Limitations + +| Feature | Emulation Status | Notes | +|---------|-----------------|-------| +| BAR Aperture Config | ✅ Full | Local state + backing store | +| ForceBarAccess | ✅ Full | Per-VF exclusive access | +| BAR Save/Restore | ✅ Full | Migration support | +| WPR Write Protect | ✅ Full | Region tracking + access check | +| WPR Read Protect | ✅ Full | Region tracking + access check | +| WPR Timeout | ✅ Partial | Timeout stored, callbacks not wired | +| Memory Alloc | ✅ Basic | Synthetic handles/VAs | +| Memory Pin | ✅ Basic | Synthetic DMA addresses | +| Memory Map | ✅ Basic | Identity mapping | +| Migration | ⚠️ Partial | BAR/WPR state only | +| Scheduling | ❌ No | Returns success, no actual scheduling | +| Notifications | ❌ No | No async event delivery | + +## Testing Emulation + +```bash +# 1. Load driver (auto-enables emulation on consumer GSP) +sudo insmod driver/gsp-vgpu.ko firmware_name=gsp-570.144.fwimage.bin + +# 2. Verify emulation enabled in dmesg +dmesg -T | grep -i emulation +# gsp-vgpu: GSP lacks vGPU RPC handlers (ret=-110) - ENABLING emulation mode + +# 3. Run example - should complete without timeouts +sudo LD_LIBRARY_PATH=userspace/lib ./userspace/examples/example_vgpu /dev/gsp-vgpu + +# 4. Check debugfs for emulated state +cat /sys/kernel/debug/gsp-vgpu/vfs/vf1/bar_state +cat /sys/kernel/debug/gsp-vgpu/vfs/vf1/wpr_regions +``` + +## Future Work + +- [ ] Wire WPR timeout callbacks to kernel timers +- [ ] Implement emulated scheduling with work queues +- [ ] Add async notification support via eventfd +- [ ] Complete migration state for WPR regions +- [ ] Performance optimization (batch RPC emulation) +- [ ] Conformance tests vs GRID GSP behavior + +## Related Documentation + +- [BAR Emulation Specification](BAR-Emulation-Specification.md) +- [WPR Management](WPR-Management.md) +- [RPC Message Format](RPC-Message-Format.md) +- [Integration Guide](vGPU-IO-Integration-Guide.md) \ No newline at end of file diff --git a/wiki/Glossary.md b/wiki/Glossary.md new file mode 100644 index 0000000..2c61a83 --- /dev/null +++ b/wiki/Glossary.md @@ -0,0 +1,163 @@ +# Glossary + +## Terms & Abbreviations + +### General +| Term | Definition | +|------|------------| +| **GSP** | GPU System Processor - NVIDIA's on-GPU RISC-V microcontroller | +| **vGPU** | Virtual GPU - Partitioned GPU for multi-tenant workloads | +| **VF** | Virtual Function - Single vGPU instance with dedicated resources | +| **PF** | Physical Function - Host GPU managing VFs (SR-IOV) | +| **IOV** | I/O Virtualization - SR-IOV implementation | +| **RPC** | Remote Procedure Call - GSP-host communication protocol | +| **BAR** | Base Address Register - PCIe memory-mapped I/O window | +| **WPR** | Write/Read Protect Region - Memory isolation mechanism | +| **SR-IOV** | Single Root I/O Virtualization - PCIe virtualization standard | + +### Firmware Architecture +| Term | Definition | +|------|------------| +| **RV64IMAC** | RISC-V 64-bit ISA with Integer, Multiply, Atomic, Compressed extensions | +| **Dispatcher** | Central RPC routing function (primary/secondary) | +| **Jump Table** | Array of function pointers for sub-command dispatch | +| **Sub-Command** | Specific operation within an RPC type | +| **Descriptor** | Return structure with ID and echoed parameters | +| **Entry Point** | Firmware boot address (0x04009000) | +| **Frame Guard** | Stack canary at 0x041DC350 | + +### Memory Management +| Term | Definition | +|------|------------| +| **VRAM** | Video RAM - GPU local memory | +| **Sysmem** | System Memory - Host DRAM | +| **Page Table** | GPU virtual-to-physical mapping tables | +| **Pinning** | Locking pages for DMA access | +| **Bounce Buffer** | Intermediate buffer for data transfer | +| **Aperture** | Mappable BAR window size | +| **Backing Store** | Memory backing emulated BAR regions | + +### RPC Types +| RPC | Name | Purpose | +|-----|------|---------| +| 0x01 | **ALLOC** | Allocate GPU memory | +| 0x02 | **FREE** | Free GPU memory | +| 0x03 | **MAP** | Map memory to VF address space | +| 0x04 | **UNMAP** | Unmap memory from VF | +| 0x05 | **PIN** | Pin pages for DMA | +| 0x06 | **UNPIN** | Unpin pages | +| 0x07 | **SCHEDULE** | VF scheduling control | +| 0x08 | **YIELD** | Voluntary yield | +| 0x09 | **NOTIFY** | Event notification | +| 0x0A | **BAR_TRAP** | BAR access emulation | +| 0x0B | **MIGRATE** | Live VF migration | +| 0x0C | **DEBUG** | Debug interface | + +### Migration +| Term | Definition | +|------|------------| +| **Pre-copy** | Iterative page transfer while VF runs | +| **Post-copy** | Start VF on destination, fetch pages on demand | +| **Quiesce** | Pause VF for consistent state snapshot | +| **Dirty Page** | Page modified since last transfer | +| **Cutover** | Switch execution from source to destination | +| **Token** | Opaque migration context handle | + +### BAR Emulation +| Term | Definition | +|------|------------| +| **BAR1** | Primary 32-bit BAR for register access | +| **Bar1Rest** | BAR1 state restoration | +| **ForceBarAccess** | Hypervisor bypass of VF permissions | +| **Aperture** | Configurable BAR window size/offset | + +### WPR (Write/Read Protect Region) +| Term | Definition | +|------|------------| +| **Write Protect** | Trap on write access to region | +| **Read Protect** | Trap on read access to region | +| **NV_WPR** | NVIDIA-specific WPR extensions | +| **Completion** | Successful trap handling | +| **Timeout** | Trap handling exceeded time limit | + +### Hardware Registers +| Register | Purpose | +|----------|---------| +| **Doorbell** | Host→GSP notification (PCIe BAR0 + 0x1000) | +| **Message Ring** | Shared memory for RPC messages | +| **Cache Manager** | 0x429B428 - Flush/invalidate | +| **Allocator Arena** | 0x429B450 - Memory allocation | +| **Global Error Flag** | 0x04296048 - Global error state | +| **Stack Canary** | 0x041DC350 - Frame integrity | + +### Tools & Scripts +| Tool | Purpose | +|------|---------| +| **analyzeHeadless** | Ghidra headless analyzer | +| **DecompileFunctions.java** | Ghidra script for batch decompilation | +| **trace_all_subsystems.py** | Binary analysis script | +| **RPC_HANDLER_MAP.md** | Complete RPC address map | +| **FINAL_REPORT.md** | Full analysis report | + +### Debugging +| Term | Definition | +|------|------------| +| **ebreak** | RISC-V breakpoint instruction (fatal in FW) | +| **String Ref** | Cross-reference to string literal | +| **XRef** | Cross-reference (code/data) | +| **Pcode** | Ghidra's intermediate representation | +| **VBIOS** | Video BIOS - firmware for GPU initialization | + +### Calling Convention (RISC-V) +| Register | ABI Name | Purpose | +|----------|----------|---------| +| x0 | zero | Hardwired zero | +| x1 | ra | Return address | +| x2 | sp | Stack pointer | +| x3 | gp | Global pointer | +| x4 | tp | Thread pointer | +| x5-7 | t0-t2 | Temporaries | +| x8 | s0/fp | Frame pointer | +| x9 | s1 | Callee-saved (RA save) | +| x10-11 | a0-a1 | Arguments/returns | +| x12 | s4 | Callee-saved (RA save) | +| x13-17 | a2-a6 | Arguments | +| x18-27 | s2-s11 | Callee-saved | +| x28-31 | t3-t6 | Temporaries | + +### Firmware Sections (ELF) +| Section | Purpose | +|---------|---------| +| `.text` | Executable code | +| `.rodata` | Read-only data | +| `.data` | Initialized data | +| `.bss` | Zero-initialized data | +| `.section_task_rm_*` | Task-specific sections | + +### Migration Phases +| Phase | Description | +|-------|-------------| +| **QUERY** | Check migratability | +| **PREPARE** | Quiesce, snapshot | +| **TRANSFER** | Iterative page copy | +| **COMMIT** | Final sync, cutover | +| **CLEANUP** | Release resources | + +## File Naming Conventions + +### Decompiled Output +``` +FUN_ram_
_ram_
.c +``` +- `FUN_ram_057A1AC0_ram_057A1AC0.c` = Function at 0x057A1AC0 + +### Ghidra Projects +``` +gsp-/ +``` +- `gsp-subcmds`, `gsp-rpc-handlers`, `gsp-bar-fns`, etc. + +## References +- RISC-V ISA: https://riscv.org/technical/specifications/ +- SR-IOV Spec: https://pcisig.com/specifications/iov/ +- Ghidra: https://ghidra-sre.org/ \ No newline at end of file diff --git a/wiki/Migration-Protocol.md b/wiki/Migration-Protocol.md new file mode 100644 index 0000000..4fbc879 --- /dev/null +++ b/wiki/Migration-Protocol.md @@ -0,0 +1,395 @@ +# Migration Protocol (RPC 0x0B) + +## Overview +The MIGRATE RPC (type 0x0B) implements live migration for vGPU virtual functions. It uses **dual jump tables** for two-phase migration operations, accessed via the primary dispatcher at 0x057A1AC0. + +## Key Addresses + +### Migration Jump Tables + +#### Table 1: 0x04179ED8 (Primary MIGRATE branch at 0x057A1BDC) +| Index | Target | Decompiled | Description | +|-------|--------|------------|-------------| +| 0 | 0x057A2344 | ✅ | Phase 1: Prepare - returns ID 0x14, checks flag at +0x7F9 | +| 1 | 0x057A2320 | ✅ | Phase 1: Prepare variant | +| 2 | 0x057A230C | ✅ | Phase 1: Prepare variant | +| 3 | 0x057A22F8 | ✅ | Phase 1: Prepare - returns ID 0x10 | +| 4 | 0x057A2388 | ✅ | Phase 1: Prepare variant | +| 5 | 0x057A23D8 | ✅ | Phase 1: Prepare variant | +| 6 | 0x057A23AC | ✅ | Phase 1: Prepare variant | +| 7 | 0x057A2478 | ✅ | Phase 1: Prepare variant | +| 8 | 0x057A2428 | ✅ | Phase 1: Prepare variant | +| 9 | 0x057A2454 | ✅ | Phase 1: Prepare variant | +| 10 | 0x057A2404 | ✅ | Phase 1: Prepare variant | +| 11 | 0x057A2364 | ✅ | Phase 1: Prepare variant | +| 12 | 0x057A1F3C | (dup) | Duplicate entry | +| 13 | 0x057A299C | — | Phase 2: Transfer | +| 14 | 0x057A1F3C | (dup) | Duplicate entry | +| 15 | 0x057A1F3C | (dup) | Duplicate entry | + +#### Table 2: 0x04179FBC (Primary MIGRATE branch at 0x057A1D5C) +| Index | Target | Decompiled | Description | +|-------|--------|------------|-------------| +| 0 | 0x057A257C | ✅ | Phase 2: Transfer | +| 1 | 0x057A25E4 | ✅ | Phase 2: Transfer | +| 2 | 0x057A24EC | ✅ | Phase 2: Transfer | +| 3 | 0x057A2608 | ✅ | Phase 2: Transfer | +| 4 | 0x057A2534 | ✅ | Phase 2: Transfer | +| 5 | 0x057A25C0 | ✅ | Phase 2: Transfer | +| 6 | 0x057A24A4 | ✅ | Phase 2: Transfer | +| 7 | 0x057A259C | ✅ | Phase 2: Transfer | +| 8 | 0x057A2510 | ✅ | Phase 2: Transfer | +| 9 | 0x057A2558 | ✅ | Phase 2: Transfer | +| 10 | 0x057A24C8 | ✅ | Phase 2: Transfer | +| 11 | 0x057A262C | ✅ | Phase 2: Transfer | +| 12 | 0x057A345C | ✅ | Phase 3: Commit | +| 13 | 0x057A36D8 | ✅ | Phase 3: Commit | +| 14 | 0x057A35D8 | ✅ | Phase 3: Commit | +| 15 | 0x057A3658 | ✅ | Phase 3: Commit | + +## Migration Phases + +### Phase 0: Discovery (Pre-migration) +```c +// Query VF migratability +int gsp_migrate_query(struct gsp_vf *vf, struct migrate_query *out) { + migrate_payload_t payload = { + .phase = MIGRATE_PHASE_QUERY, + .subcmd = 0, + .src_vf = vf->id, + .dst_vf = 0, + }; + return gsp_rpc_send(vf->gsp, RPC_MIGRATE, &payload, sizeof(payload), out, sizeof(*out)); +} +``` + +### Phase 1: Prepare (Table 1, indices 0-11) +**Goal**: Quiesce VF, prepare memory state for transfer + +```c +// Subcmd 3 (0x057A22F8) - Returns ID 0x10 +int migrate_prepare_quiesce(vf_id) { + // 1. Pause VF scheduling + // 2. Flush pending commands + // 3. Pin all VF memory + // 4. Return quiesce token +} + +// Subcmd 0 (0x057A2344) - Returns ID 0x14, checks flag at in_t1+0x7F9 +int migrate_prepare_snapshot(vf_id, *token) { + // 1. Snapshot VF register state + // 2. Snapshot BAR configurations + // 3. Snapshot WPR regions + // 4. Snapshot page tables + // 5. Return snapshot handle +} +``` + +### Phase 2: Transfer (Table 1 index 13, Table 2 indices 0-11) +**Goal**: Transfer memory pages to destination + +```c +// Table 2, subcmd 0 (0x057A257C) +int migrate_transfer_pages(vf_id, page_list, *progress) { + // 1. Iterate page list + // 2. For each page: + // a. Copy via DMA (0x0588F9C4) + // b. Verify checksum + // c. Mark page dirty if modified + // 3. Return bytes transferred +} + +// Table 2, subcmd 11 (0x057A262C) - Dirty page tracking +int migrate_track_dirty(vf_id, *dirty_bitmap) { + // Return bitmap of pages dirtied since last transfer +} +``` + +### Phase 3: Commit (Table 2 indices 12-15) +**Goal**: Final synchronization, cutover to destination + +```c +// Subcmd 12 (0x057A345C) +int migrate_commit_finalize(vf_id, dst_vf_id) { + // 1. Final dirty page transfer + // 2. Transfer register state + // 3. Activate destination VF + // 4. Release source VF resources + // 5. Notify completion +} + +// Subcmd 13 (0x057A36D8) +int migrate_commit_verify(vf_id, *verify_result) { + // 1. Verify memory integrity + // 2. Verify register state + // 3. Verify device state + // 4. Return PASS/FAIL +} +``` + +### Phase 4: Cleanup (Post-migration) +```c +int migrate_cleanup(src_vf_id) { + // 1. Release pinned memory + // 2. Free snapshot buffers + // 3. Remove WPR regions + // 4. Destroy migration context +} +``` + +## Migration Message Format + +```c +typedef struct { + uint32_t phase; // MIGRATE_PHASE_* + uint32_t subcmd; // Sub-command index (0-15 per table) + uint64_t src_vf; // Source VF ID + uint64_t dst_vf; // Destination VF ID + uint64_t data_ptr; // Data buffer (page list, bitmap, etc.) + uint64_t data_size; // Buffer size + uint32_t flags; // MIGRATE_LIVE, MIGRATE_POSTCOPY, etc. + uint32_t reserved; + uint64_t token; // Opaque migration token +} __attribute__((packed)) migrate_payload_t; + +#define MIGRATE_PHASE_QUERY 0 +#define MIGRATE_PHASE_PREPARE 1 +#define MIGRATE_PHASE_TRANSFER 2 +#define MIGRATE_PHASE_COMMIT 3 +#define MIGRATE_PHASE_CLEANUP 4 + +#define MIGRATE_FLAG_LIVE (1<<0) // Live migration +#define MIGRATE_FLAG_POSTCOPY (1<<1) // Post-copy mode +#define MIGRATE_FLAG_AUTO_COMMIT (1<<2) // Auto-commit after transfer +#define MIGRATE_FLAG_VERIFY (1<<3) // Verify integrity +``` + +## Sub-Command Descriptors (Returned by Handlers) + +All migration handlers follow the primary dispatcher pattern: + +```c +typedef struct { + uint32_t subcmd_id; // Constant: 0x10, 0x14, etc. + uint8_t echo_flags_b; // Copy of input flags_b + uint8_t echo_flags_a; // Copy of input flags_a + uint8_t echo_flags_c; // Copy of input flags_c +} migrate_descriptor_t; +``` + +**Known Subcmd IDs**: +| Subcmd | ID | Phase | +|--------|-----|-------| +| 0x057A22F8 (Table1[3]) | 0x10 | Prepare | +| 0x057A2344 (Table1[0]) | 0x14 | Prepare | +| Others | TBD | Transfer/Commit | + +## vGPU-IO Integration + +### Migration State Machine +```c +typedef enum { + MIG_STATE_IDLE = 0, + MIG_STATE_QUERY, + MIG_STATE_PREPARE, + MIG_STATE_TRANSFER, + MIG_STATE_COMMIT, + MIG_STATE_CLEANUP, + MIG_STATE_FAILED, + MIG_STATE_COMPLETED +} mig_state_t; + +struct gsp_migration { + struct gsp_vf *vf; + mig_state_t state; + uint64_t token; + uint64_t dst_vf; + struct migrate_progress progress; + struct completion comp; + struct mutex lock; +}; +``` + +### Migration Coordinator +```c +int gsp_migration_start(struct gsp_vf *vf, uint64_t dst_vf) { + struct gsp_migration *mig = kzalloc(sizeof(*mig), GFP_KERNEL); + vf->migration = mig; + mig->vf = vf; + mig->dst_vf = dst_vf; + mig->state = MIG_STATE_QUERY; + + // Phase 0: Query + struct migrate_query qry; + gsp_migrate_query(vf, &qry); + if (!qry.migratable) return -EINVAL; + + // Phase 1: Prepare + mig->state = MIG_STATE_PREPARE; + migrate_payload_t prep = { + .phase = MIGRATE_PHASE_PREPARE, + .subcmd = 3, // Quiesce + .src_vf = vf->id, + .dst_vf = dst_vf, + }; + migrate_descriptor_t desc; + gsp_rpc_send(vf->gsp, RPC_MIGRATE, &prep, sizeof(prep), &desc, sizeof(desc)); + mig->token = desc.subcmd_id; // Use returned token + + // Phase 2: Transfer (iterative) + mig->state = MIG_STATE_TRANSFER; + while (!gsp_migration_transfer_iter(mig)) { + msleep(10); // Throttle + if (signal_pending(current)) break; + } + + // Phase 3: Commit + mig->state = MIG_STATE_COMMIT; + migrate_payload_t commit = { + .phase = MIGRATE_PHASE_COMMIT, + .subcmd = 12, + .src_vf = vf->id, + .dst_vf = dst_vf, + .token = mig->token, + .flags = MIGRATE_FLAG_VERIFY, + }; + gsp_rpc_send(vf->gsp, RPC_MIGRATE, &commit, sizeof(commit), NULL, 0); + + // Phase 4: Cleanup + mig->state = MIG_STATE_CLEANUP; + gsp_migration_cleanup(mig); + + mig->state = MIG_STATE_COMPLETED; + return 0; +} +``` + +### Transfer Iteration +```c +bool gsp_migration_transfer_iter(struct gsp_migration *mig) { + migrate_payload_t xfer = { + .phase = MIGRATE_PHASE_TRANSFER, + .subcmd = 0, + .src_vf = mig->vf->id, + .dst_vf = mig->dst_vf, + .data_ptr = (uint64_t)mig->progress.page_list, + .data_size = mig->progress.page_count * sizeof(uint64_t), + .token = mig->token, + }; + + struct migrate_progress prog; + int ret = gsp_rpc_send(mig->vf->gsp, RPC_MIGRATE, + &xfer, sizeof(xfer), &prog, sizeof(prog)); + + if (ret) return true; // Error = done + + mig->progress.bytes_transferred += prog.bytes_transferred; + mig->progress.pages_transferred += prog.pages_transferred; + mig->progress.dirty_pages = prog.dirty_pages; + + // Check if more dirty pages to transfer + if (prog.dirty_pages > 0 && !(mig->flags & MIGRATE_FLAG_POSTCOPY)) { + return false; // Continue iterating + } + + return true; // Transfer complete +} +``` + +### Post-Copy Mode +```c +int gsp_migration_postcopy(struct gsp_migration *mig) { + // Enable post-copy on destination + migrate_payload_t pc = { + .phase = MIGRATE_PHASE_TRANSFER, + .subcmd = 11, // Dirty tracking + .src_vf = mig->vf->id, + .dst_vf = mig->dst_vf, + .flags = MIGRATE_FLAG_POSTCOPY, + .token = mig->token, + }; + + // Page fault handler on destination + gsp_page_fault_handler = gsp_migration_page_fault; + + return gsp_rpc_send(mig->vf->gsp, RPC_MIGRATE, &pc, sizeof(pc), NULL, 0); +} +``` + +## Integration with BAR/WPR + +### BAR State Migration +```c +int gsp_migration_bar_save(struct gsp_migration *mig) { + // Save BAR1 aperture, force access state + struct bar_save_msg bar_save = { + .vf_id = mig->vf->id, + .bar = 1, + }; + return gsp_rpc_send(mig->vf->gsp, RPC_BAR_TRAP, + BAR_SUBCMD_SAVE, &bar_save, sizeof(bar_save), + mig->bar_state_buf, &mig->bar_state_size); +} + +int gsp_migration_bar_restore(struct gsp_migration *mig) { + // Restore BAR1 on destination + struct bar_restore_msg bar_restore = { + .vf_id = mig->dst_vf, + .bar = 1, + .data = mig->bar_state_buf, + .data_size = mig->bar_state_size, + }; + return gsp_rpc_send(mig->vf->gsp, RPC_BAR_TRAP, + BAR_SUBCMD_RESTORE, &bar_restore, sizeof(bar_restore)); +} +``` + +### WPR Region Migration +```c +int gsp_migration_wpr_save(struct gsp_migration *mig) { + // Save WPR regions for VF + migrate_payload_t wpr = { + .phase = MIGRATE_PHASE_PREPARE, + .subcmd = 4, // WPR snapshot + .src_vf = mig->vf->id, + .dst_vf = mig->dst_vf, + .token = mig->token, + }; + return gsp_rpc_send(mig->vf->gsp, RPC_MIGRATE, &wpr, sizeof(wpr), NULL, 0); +} +``` + +## Error Handling + +| Phase | Error | Recovery | +|-------|-------|----------| +| Prepare | EBUSY | Wait, retry | +| Prepare | ENOMEM | Reduce snapshot size | +| Transfer | ETIMEDOUT | Checkpoint, retry | +| Transfer | EIO | Failover to post-copy | +| Commit | EINVAL | Rollback to source | +| Commit | ENOSPC | Expand destination | + +## Debugging + +### Migration Trace Points +```c +trace_gsp_mig_phase(vf_id, phase, subcmd, token); +trace_gsp_mig_transfer(vf_id, pages, bytes, dirty); +trace_gsp_mig_commit(vf_id, status, verify); +trace_gsp_mig_error(vf_id, phase, error); +``` + +### GSP Log Strings +Search for migration-related strings in firmware: +- Migration phase markers +- Page transfer progress +- Commit verification results + +--- + +## Reference +- Primary Dispatcher MIGRATE branches: 0x057A1BDC, 0x057A1D54 +- Jump Table 1: 0x04179ED8 (16 entries) +- Jump Table 2: 0x04179FBC (16 entries) +- Decompiled handlers: 28 functions in decompiled/ \ No newline at end of file diff --git a/wiki/README.md b/wiki/README.md new file mode 100644 index 0000000..a7fee86 --- /dev/null +++ b/wiki/README.md @@ -0,0 +1,21 @@ +# vGPU-IO Wiki + +## Documentation Index + +### Core Analysis +- [GSP 570.144W Firmware Analysis](GSP-570.144W-Firmware-Analysis.md) - Complete firmware analysis +- [RPC Message Format](RPC-Message-Format.md) - Wire protocol specification +- [BAR Emulation Specification](BAR-Emulation-Specification.md) - BAR1/Bar1Rest/ForceBarAccess +- [WPR Management](WPR-Management.md) - Write/Read Protect Region handling +- [Migration Protocol](Migration-Protocol.md) - Live migration RPC 0x0B +- [GSP RPC Emulation](GSP-RPC-Emulation.md) - Emulation mode for consumer/OpenRM GSP + +### Integration Guides +- [vGPU-IO Integration Guide](vGPU-IO-Integration-Guide.md) - Kernel driver implementation +- [Kernel RPC Client](Kernel-RPC-Client.md) - Calling convention & message building +- [Testing & Validation](Testing-and-Validation.md) - Verification procedures + +### Reference +- [Address Reference](Address-Reference.md) - All key addresses in one table +- [Error Codes](Error-Codes.md) - GSP error code reference +- [Glossary](Glossary.md) - Terms and abbreviations \ No newline at end of file diff --git a/wiki/RPC-Message-Format.md b/wiki/RPC-Message-Format.md new file mode 100644 index 0000000..e627871 --- /dev/null +++ b/wiki/RPC-Message-Format.md @@ -0,0 +1,316 @@ +# GSP RPC Message Format Specification + +## Overview +The GSP firmware uses a dispatcher-based RPC system with two dispatchers: +- **Primary** (0x057A1AC0): ALLOC, FREE, MAP, UNMAP, PIN, UNPIN, SCHEDULE, YIELD, NOTIFY, BAR_TRAP, MIGRATE, DEBUG +- **Secondary** (0x04ED39DC): Branch-based dispatch for all 11 types + +## Primary Dispatcher Call Convention + +### Entry Point +``` +FUN_ram_057a1ac0( + uint32_t rpc_type, // param_1: RPC type (0x01-0x0C) + uint8_t flags_a, // param_2 + uint8_t flags_b, // param_3 + uint8_t flags_c, // param_4 + uint32_t *out_subcmd_id,// param_5: Returns sub-command ID + uint8_t *out_a, // param_6: Echoes flags_b + uint8_t *out_b, // param_7: Echoes flags_a + uint8_t *out_c // param_8: Echoes flags_c +) -> int64_t +``` + +### RPC Type to Sub-Command Mapping +The primary dispatcher validates RPC type, then indexes into the 32-entry jump table at **0x057A3AD8**. + +| RPC Type | Name | Subcmd Range | Notes | +|----------|------|--------------|-------| +| 0x01 | ALLOC | 0-31 | Uses 0x057E94EC main | +| 0x02 | FREE | 0-31 | | +| 0x03 | MAP | — | Uses secondary dispatcher | +| 0x04 | UNMAP | 0-31 | Primary + secondary | +| 0x05 | PIN | — | Uses secondary dispatcher | +| 0x06 | UNPIN | — | Uses secondary dispatcher | +| 0x07 | SCHEDULE | 0-31 | Uses 0x051EFBF4 main | +| 0x08 | YIELD | — | Uses secondary dispatcher | +| 0x09 | NOTIFY | — | Uses secondary dispatcher | +| 0x0A | BAR_TRAP | — | Uses 0x04CB8188 | +| 0x0B | MIGRATE | 0-15 x2 | Dual jump tables | +| 0x0C | DEBUG | — | Unimplemented | + +### Sub-Command Descriptor (Returned by Jump Table Handlers) +Each sub-command handler at the jump table returns: +```c +typedef struct { + uint32_t subcmd_id; // Constant ID (e.g., 0x10, 0x14, 0x40) + uint8_t echo_flags_b; // Copy of input flags_b + uint8_t echo_flags_a; // Copy of input flags_a + uint8_t echo_flags_c; // Copy of input flags_c +} __attribute__((packed)) subcmd_descriptor_t; +``` + +**Example: Subcmd 3 (0x057A1BCC)** +```c +// Returns ID = 0x10 +*out_subcmd_id = 0x10; +*out_a = flags_b; +*out_b = flags_a; +*out_c = flags_c; +return 0; +``` + +**Example: Subcmd 0 (0x057A1DB4)** +```c +// Returns ID = 0x40 +*out_subcmd_id = 0x40; +*out_a = flags_b; +*out_b = flags_a; +*out_c = flags_c; +return 0; +``` + +## Secondary Dispatcher Call Convention + +### Entry Point +``` +FUN_ram_04ed39dc(rpc_message_t *msg) -> int64_t +``` + +### Message Structure (Inferred) +```c +typedef struct { + uint32_t rpc_type; // 0x01-0x0B + uint32_t sub_type; // Sub-operation code + uint64_t payload_ptr; // Pointer to RPC-specific payload + uint32_t payload_size; // Size of payload + uint32_t flags; // Control flags + uint64_t context; // Opaque context + uint32_t sequence; // Sequence number + uint32_t reserved; +} __attribute__((packed)) rpc_message_t; +``` + +### Branch-Based Dispatch +Secondary dispatcher uses `bgeu`/`bltu` branches on `rpc_type` register: +```assembly +# Pseudocode +if (rpc_type >= 0x0C) goto error; +switch(rpc_type): + case 0x03: call MAP_handler_A; + case 0x04: call UNMAP_handler_A; + case 0x05: call PIN_handler_A (0x04ED34B8); + case 0x06: call UNPIN_handler_A; + case 0x07: call SCHEDULE_handler_A; + case 0x08: call YIELD_handler_A; + case 0x09: call NOTIFY_handler_A; + case 0x0A: call BAR_TRAP_handler (0x057675B7); +``` + +## RPC-Specific Payloads + +### ALLOC (0x01) - Via 0x057E94EC +```c +typedef struct { + uint64_t size; // Allocation size in bytes + uint32_t type; // Memory type (VRAM, sysmem, etc.) + uint32_t alignment; // Alignment requirement + uint64_t va_hint; // Virtual address hint + uint32_t flags; // CACHE_COHERENT, UNCACHED, etc. + uint32_t pid; // Process ID + uint32_t vf_id; // VF ID (for vGPU) + uint32_t reserved; + uint64_t *out_handle; // Output: allocation handle + uint64_t *out_va; // Output: mapped virtual address + uint64_t *out_pa; // Output: physical address +} alloc_payload_t; +``` + +### MAP (0x03) - Handlers 0x05766AB7 / 0x05778A37 +```c +typedef struct { + uint64_t handle; // Allocation handle from ALLOC + uint64_t va; // Target virtual address + uint64_t size; // Map size + uint32_t prot; // PROT_READ|PROT_WRITE|PROT_EXEC + uint32_t flags; // MAP_FIXED, MAP_SHARED, etc. + uint32_t vf_id; // Target VF + uint32_t reserved; +} map_payload_t; +``` + +### PIN (0x05) - Handler 0x04ED34B8 +```c +typedef struct { + uint64_t handle; // Allocation handle + uint64_t offset; // Offset within allocation + uint64_t size; // Size to pin + uint32_t vf_id; // Target VF + uint32_t flags; // PIN_WRITE, PIN_READ, PIN_LONGTERM + uint64_t *out_dma_addr; // Output: DMA address for device +} pin_payload_t; +``` + +### SCHEDULE (0x07) - Via 0x051EFBF4 / 0x05767F37 +```c +typedef struct { + uint32_t vf_id; // VF to schedule + uint32_t priority; // Scheduling priority + uint64_t time_slice_ns; // Time slice in nanoseconds + uint32_t flags; // PREEMPTIBLE, REALTIME, etc. + uint32_t reserved; +} schedule_payload_t; +``` + +### BAR_TRAP (0x0A) - Handler 0x04CB8188 +```c +typedef struct { + uint32_t bar_index; // BAR number (0-5) + uint32_t trap_type; // READ, WRITE, ATOMIC + uint64_t offset; // Offset within BAR + uint64_t value; // Value for writes + uint32_t size; // Access size (1,2,4,8) + uint32_t vf_id; // Trapping VF + uint64_t *out_value; // Output: read value +} bar_trap_payload_t; +``` + +### MIGRATE (0x0B) - Dual Jump Tables +```c +typedef struct { + uint32_t phase; // 0=prepare, 1=transfer, 2=commit, 3=cleanup + uint32_t subcmd; // Sub-command index (0-15 for each table) + uint64_t src_vf; // Source VF + uint64_t dst_vf; // Destination VF + uint64_t data_ptr; // Migration data buffer + uint64_t data_size; // Buffer size + uint32_t flags; // LIVE, POSTCOPY, etc. + uint32_t reserved; +} migrate_payload_t; +``` + +## Wire Format (Host → GSP) + +### Message Header (64 bytes) +```c +typedef struct { + uint32_t magic; // 0x47535052 ("GSPR") + uint32_t version; // Protocol version (1) + uint32_t rpc_type; // 0x01-0x0C + uint32_t sequence; // Monotonic sequence + uint64_t timestamp_ns; // Submission timestamp + uint32_t payload_size; // Size of payload + uint32_t flags; // MSG_SYNC, MSG_ASYNC, MSG_NOREPLY + uint64_t correlation_id;// For async matching + uint64_t reserved[3]; // Padding to 64 bytes +} __attribute__((packed)) rpc_header_t; +``` + +### Complete Message +``` ++------------------+ +| rpc_header_t | 64 bytes ++------------------+ +| payload (varies) | payload_size bytes ++------------------+ +| padding to 256B | (alignment) ++------------------+ +``` + +## Response Format + +### Synchronous Response +```c +typedef struct { + int64_t status; // 0 = success, negative = error + uint32_t rpc_type; // Echo of request + uint32_t sequence; // Echo of request + uint64_t timestamp_ns; // Completion timestamp + uint32_t payload_size; // Response payload size + uint32_t reserved; +} __attribute__((packed)) rpc_response_header_t; +``` + +### Error Codes +| Code | Name | Description | +|------|------|-------------| +| 0 | OK | Success | +| -1 (0xFFFF) | EPERM | Permission denied | +| -2 (0xFFFE) | ENOENT | Not found | +| -3 (0xFFFD) | EINVAL | Invalid argument | +| -6 (0xFFFA) | ENODEV | No such device | +| -12 (0xFFF4) | ENOMEM | Out of memory | +| -16 (0xFFEE) | EBUSY | Resource busy | +| -22 (0xFFEA) | EINVAL | Invalid argument | +| -28 (0xFFE4) | ENOSPC | No space left | +| -37 (0xFFDB) | ENOLCK | No locks available | +| -56 (0xFFC8) | EBADMSG | Bad message | +| -84 (0xFFAC) | EOVERFLOW | Value too large | +| -90 (0xFFA6) | ENOSTR | Not a stream | +| -91 (0xFFA5) | ENODATA | No data available | +| -94 (0xFFA2) | ENOSR | Out of streams resources | +| -97 (0xFF9F) | EPROTO | Protocol error | +| -111 (0xFF91) | ETIMEDOUT | Connection timed out | + +## Kernel Client Implementation + +### Message Builder +```c +static int gsp_rpc_send(gsp_client_t *client, uint32_t rpc_type, + void *payload, size_t payload_size, + void *response, size_t *response_size) { + rpc_header_t hdr = { + .magic = 0x47535052, + .version = 1, + .rpc_type = rpc_type, + .sequence = atomic_inc(&client->seq), + .timestamp_ns = ktime_get_ns(), + .payload_size = payload_size, + .flags = MSG_SYNC, + }; + + // Build complete message + uint8_t msg[256]; + memcpy(msg, &hdr, sizeof(hdr)); + memcpy(msg + 64, payload, payload_size); + + // Submit to GSP doorbell + return gsp_doorbell_ring(client->gsp, msg, sizeof(msg)); +} +``` + +### Doorbell Mechanism +```c +// GSP doorbell register (PCIe BAR0 + offset) +#define GSP_DOORBELL_OFFSET 0x1000 + +static void gsp_doorbell_ring(gsp_device_t *gsp, void *msg, size_t len) { + // Copy message to shared memory ring + // Ring GSP doorbell + writel(1, gsp->bar0 + GSP_DOORBELL_OFFSET); +} +``` + +## Async Completion + +### Notification Mechanism +```c +typedef struct { + uint32_t rpc_type; + uint32_t sequence; + int64_t status; + uint64_t timestamp_ns; + uint32_t payload_size; + uint32_t reserved; +} async_completion_t; + +// Delivered via MSI-X or GSP notification queue +``` + +--- + +## Reference +- Primary Dispatcher: 0x057A1AC0 +- Secondary Dispatcher: 0x04ED39DC +- Jump Table: 0x057A3AD8 (32 entries) +- RPC Type Jump Table: 0x059BFEB0 (12 types) \ No newline at end of file diff --git a/wiki/Virtual_IO_Internals.md b/wiki/Virtual_IO_Internals.md new file mode 100644 index 0000000..d97344e --- /dev/null +++ b/wiki/Virtual_IO_Internals.md @@ -0,0 +1,1736 @@ +::: {#mw-page-base .noprint} +::: + +::: {#mw-head-base .noprint} +::: + +::: {#content .mw-body role="main"} +[]{#top} + +::: {#siteNotice} +::: + +::: mw-indicators +::: + +# Virtual I/O Internals {#firstHeading .firstHeading} + +::: {#bodyContent .vector-body} +::: {#siteSub .noprint} +From Open-IOV +::: + +::: {#contentSub} +::: {.mw-revision .warningbox} +::: {#mw-revision-info} +Revision as of 17:54, 19 June 2023 by +[Arthur](./index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html "User:Arthur (page does not exist)"){.new +.mw-userlink} +[([talk](./index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html "User talk:Arthur (page does not exist)"){.new +.mw-usertoollinks-talk} \| +[contribs](index.php/Special:Contributions/Arthur.html "Special:Contributions/Arthur"){.mw-usertoollinks-contribs})]{.mw-usertoollinks} +[([[[→‎References (Talks & Reading +Material)](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#References_(Talks_&_Reading_Material))]{.autocomment}]{dir="auto"})]{.comment} +::: + +::: {#mw-revision-nav} +([diff](https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23792 "Virtual I/O Internals")) +[← Older +revision](https://open-iov.org/index.php?title=Virtual_I/O_Internals&direction=prev&oldid=23792 "Virtual I/O Internals") +\| Latest revision (diff) \| Newer revision → (diff) +::: +::: +::: + +::: {#contentSub2} +::: + +::: {#jump-to-nav} +::: + +[Jump to +navigation](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#mw-head){.mw-jump-link} +[Jump to +search](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#searchInput){.mw-jump-link} + +::: {#mw-content-text .mw-body-content .mw-content-ltr lang="en" dir="ltr"} +::: mw-parser-output +The following document details the internals of a **VFIO (Virtual +Function I/O)** driven **Shared** **I/O Device.** + +> An absence of critical technical documentation has historically slowed +> growth and adoption of developer ecosystems for GPU virtualization. +> +> This +> [CC-BY-4.0](https://creativecommons.org/licenses/by/4.0/){.external +> .text rel="nofollow"} licensed content can either be used with +> attribution, or used as inspiration for new documentation, created by +> GPU vendors for public commercial distribution as developer +> documentation. +> +> Where possible, this documentation will clearly label dates and +> versions of observed-but-not-guaranteed behaviour vs. +> vendor-documented stable interfaces/behaviour with guarantees of +> forward or backward compatibility. + +This article places emphasis on the **Virtual GPU (vGPU)** use case +however these concepts apply generically to virtualization of I/O +devices (TPUs, NICs, storage peripherals, ect..). + + -------------------------------------------------------------------------------------- ------------------------------------------------------------------------- --------------------------------------------- + Mdev Mode SR-IOV Mode SIOV Mode + No hardware assistance needed. Hardware assistance needed. Hardware assistance needed. + Host requires insight about guest workload. Host ignorance of guest workload. Host requires insight about guest workload. + Error reporting. No guest driver error reporting. Error reporting. + In depth dynamic monitoring. Basic dynamic monitoring. In depth dynamic monitoring. + Software defined MMU guest separation. Firmware defined MMU guest separation. Firmware defined MMU guest separation. + Requires deferred instructions to be supported by host software (support libraries). Guest is ignorant of host supported software such as support libraries. + Routing interrupts. Routing interrupts. Routing interrupts. + Device reset. Device reset. Device reset. + Enable/Disable device. Enable/Disable device. Enable/Disable device. + Support for multiple scheduling techniques. Support for multiple scheduling techniques. Support for multiple scheduling techniques. + Single PCI requester ID. Multiple PCI requester IDs. Multiple PCI requester IDs. + -------------------------------------------------------------------------------------- ------------------------------------------------------------------------- --------------------------------------------- + + : Comparison of Assistance Modes + +::: {#toc .toc role="navigation" aria-labelledby="mw-toc-heading"} +::: {.toctitle lang="en" dir="ltr"} +## Contents {#mw-toc-heading} + +[]{.toctogglespan} +::: + +- [[1]{.tocnumber} [All + Modes]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#All_Modes) + - [[1.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Knowledge_Resources_Used) + - [[1.2]{.tocnumber} [Binding VFIO + devices]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Binding_VFIO_devices) + - [[1.3]{.tocnumber} [Programming the + IOMMU]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Programming_the_IOMMU) + - [[1.4]{.tocnumber} [VFIO Memory Mapped + IO]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#VFIO_Memory_Mapped_IO) + - [[1.5]{.tocnumber} [Getting the VFIO Group File + Descriptor]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Getting_the_VFIO_Group_File_Descriptor) + - [[1.6]{.tocnumber} [VFIO device file + descriptor]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#VFIO_device_file_descriptor) + - [[1.7]{.tocnumber} [VFIO + Interrupts]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#VFIO_Interrupts) + - [[1.7.1]{.tocnumber} + [IRQs]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#IRQs) + - [[1.7.1.1]{.tocnumber} [Get Device + Info]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Get_Device_Info) + - [[1.7.1.2]{.tocnumber} [Get Region + Info]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Get_Region_Info) + - [[1.7.1.3]{.tocnumber} [Get IRQ + Info]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Get_IRQ_Info) + - [[1.7.1.4]{.tocnumber} [Set + IRQs]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Set_IRQs) + - [[1.8]{.tocnumber} [Device + Decomposure/Recomposure]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Device_Decomposure/Recomposure) + - [[1.9]{.tocnumber} [Memory Management Unit + (MMU)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Memory_Management_Unit_(MMU)) + - [[1.9.1]{.tocnumber} [MMIO Isolation (Platform + MMU)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#MMIO_Isolation_(Platform_MMU)) + - [[1.9.2]{.tocnumber} [VRAM Isolation (GPU + GMMU)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#VRAM_Isolation_(GPU_GMMU)) + - [[1.9.3]{.tocnumber} [Platform MMIO \<-\> GPU Shadow + Pages]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Platform_MMIO_%3C-%3E_GPU_Shadow_Pages) + - [[1.10]{.tocnumber} [VFIO Quirks (region + traps)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#VFIO_Quirks_(region_traps)) + - [[1.11]{.tocnumber} [Known IOMMU + Issues]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Known_IOMMU_Issues) +- [[2]{.tocnumber} [Mdev + Mode]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Mdev_Mode) + - [[2.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Knowledge_Resources_Used_2) + - [[2.2]{.tocnumber} [Mediated + Core]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Mediated_Core) + - [[2.3]{.tocnumber} [Device + Initialization]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Device_Initialization) + - [[2.3.1]{.tocnumber} [Registering VFIO MDEV as a + driver]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Registering_VFIO_MDEV_as_a_driver) + - [[2.3.2]{.tocnumber} [Registering PCIE Device with the + Mediated + Core]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Registering_PCIE_Device_with_the_Mediated_Core) + - [[2.3.3]{.tocnumber} [Registering Mediated Callbacks + (CBs)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Registering_Mediated_Callbacks_(CBs)) + - [[2.3.4]{.tocnumber} [Creating a Mediated Device via + mdev-sysfsdev + API]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Creating_a_Mediated_Device_via_mdev-sysfsdev_API) + - [[2.3.5]{.tocnumber} [QEMU adds VFIO device to IOMMU + container-group]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#QEMU_adds_VFIO_device_to_IOMMU_container-group) + - [[2.3.6]{.tocnumber} [QEMU passes mdev device file + descriptor to + VM]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#QEMU_passes_mdev_device_file_descriptor_to_VM) + - [[2.4]{.tocnumber} [Instruction + Execution]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Instruction_Execution) + - [[2.4.1]{.tocnumber} [IRQ + remapping]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#IRQ_remapping) + - [[2.4.2]{.tocnumber} [Interrupt + Injection]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Interrupt_Injection) + - [[2.5]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Memory_Management) + - [[2.5.1]{.tocnumber} [Region + Passthrough]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Region_Passthrough) + - [[2.5.1.1]{.tocnumber} [Emulated + Regions]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Emulated_Regions) + - [[2.5.1.2]{.tocnumber} [Passthrough + Regions]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Passthrough_Regions) + - [[2.5.1.3]{.tocnumber} [Region + Access]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Region_Access) + - [[2.5.2]{.tocnumber} [EPT Page + Violations]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#EPT_Page_Violations) + - [[2.5.3]{.tocnumber} [Mediated DMA + Translations]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Mediated_DMA_Translations) + - [[2.6]{.tocnumber} + [Scheduling]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Scheduling) + - [[2.7]{.tocnumber} [Kernel + API]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Kernel_API) + - [[2.8]{.tocnumber} [Sample + Code]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Sample_Code) + - [[2.8.1]{.tocnumber} + [Compilation]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Compilation) + - [[2.8.2]{.tocnumber} [Loading Kernel + Modules]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Loading_Kernel_Modules) + - [[2.8.3]{.tocnumber} [Unloading Kernel + Modules]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Unloading_Kernel_Modules) + - [[2.8.4]{.tocnumber} [Additional + Documentation]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Additional_Documentation) + - [[2.9]{.tocnumber} [Mdev Mode + Requirements]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Mdev_Mode_Requirements) +- [[3]{.tocnumber} [SR-IOV + Mode]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#SR-IOV_Mode) + - [[3.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Knowledge_Resources_Used_3) + - [[3.2]{.tocnumber} [Instruction + Execution]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Instruction_Execution_2) + - [[3.3]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Memory_Management_2) + - [[3.4]{.tocnumber} + [Scheduling]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Scheduling_2) + - [[3.5]{.tocnumber} [SR-IOV Mode + Requirements]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#SR-IOV_Mode_Requirements) +- [[4]{.tocnumber} [SIOV + Mode]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#SIOV_Mode) + - [[4.1]{.tocnumber} [Knowledge Resources + Used]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Knowledge_Resources_Used_4) + - [[4.2]{.tocnumber} [Memory + Management]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Memory_Management_3) + - [[4.2.1]{.tocnumber} [IOMMU Aware Mediated + Device]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#IOMMU_Aware_Mediated_Device) + - [[4.2.2]{.tocnumber} [Shared Hardware + Workqueues]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#Shared_Hardware_Workqueues) + - [[4.3]{.tocnumber} [SIOV Mode + Requirements]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#SIOV_Mode_Requirements) +- [[5]{.tocnumber} [References (Talks & Reading + Material)]{.toctext}](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html#References_(Talks_&_Reading_Material)) +::: + +## [All Modes]{#All_Modes .mw-headline} + +This section will cover concepts which apply both to [Mdev +Mode](index.php/Mediated_Device_Internals.html#Mdev_Mode){.external +.text rel="nofollow"}, [SR-IOV +Mode](index.php/Mediated_Device_Internals.html#SR-IOV_Mode){.external +.text rel="nofollow"} & [SIOV +Mode](index.php/Mediated_Device_Internals.html#SIOV_Mode){.external +.text rel="nofollow"}. + +### [Knowledge Resources Used]{#Knowledge_Resources_Used .mw-headline} + +This section is supported by significant contributions in open source by +Alex Williamson. + +See references 2, 14, & 22 in the [References (Talks & Reading +Material)](index.php/Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} section. + +### [Binding VFIO devices]{#Binding_VFIO_devices .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/9/9e/Vfio-pci_driver_bindings.png/300px-Vfio-pci_driver_bindings.png){.thumbimage +decoding="async" width="300" height="218" +srcset="images/thumb/9/9e/Vfio-pci_driver_bindings.png/450px-Vfio-pci_driver_bindings.png 1.5x, images/thumb/9/9e/Vfio-pci_driver_bindings.png/600px-Vfio-pci_driver_bindings.png 2x"}](index.php/File:Vfio-pci_driver_bindings.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Vfio-pci_driver_bindings.png.html "Enlarge"){.internal} +::: + +**Figure 1:** VFIO group nodes are unit of ownership that VFIO uses. See +slides from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/3/33/IOCTL_set_VFIO_container.png/300px-IOCTL_set_VFIO_container.png){.thumbimage +decoding="async" width="300" height="242" +srcset="images/thumb/3/33/IOCTL_set_VFIO_container.png/450px-IOCTL_set_VFIO_container.png 1.5x, images/thumb/3/33/IOCTL_set_VFIO_container.png/600px-IOCTL_set_VFIO_container.png 2x"}](index.php/File:IOCTL_set_VFIO_container.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:IOCTL_set_VFIO_container.png.html "Enlarge"){.internal} +::: + +**Figure 2:** IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places +the VFIO Group inside the VFIO Container. See slides from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/300px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png){.thumbimage +decoding="async" width="300" height="214" +srcset="images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/450px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 1.5x, images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/600px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 2x"}](index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html "Enlarge"){.internal} +::: + +**Figure 3:** Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, +&MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and +pin pages. See slides from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/300px-Ioctl-VFIO_GROUP_GET_FD.png){.thumbimage +decoding="async" width="300" height="204" +srcset="images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/450px-Ioctl-VFIO_GROUP_GET_FD.png 1.5x, images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/600px-Ioctl-VFIO_GROUP_GET_FD.png 2x"}](index.php/File:Ioctl-VFIO_GROUP_GET_FD.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Ioctl-VFIO_GROUP_GET_FD.png.html "Enlarge"){.internal} +::: + +**Figure 4:** Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, +\"0000:01:00.0\") to obtain the VFIO Group file descriptor. See slides +from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 1:** Binding devices to the vfio-pci driver results in VFIO +group nodes. + +Opening the file \"/dev/vfio/vfio\" creates a VFIO Container. + +**Figure 2:** The interrupt routine +**`IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER)`** places the VFIO +group inside the VFIO container. + +### [Programming the IOMMU]{#Programming_the_IOMMU .mw-headline} + +When this has been done +**`IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU)`** can then be +used to set an IOMMU type for the container which places it in a user +interactable state. + +Once this IOMMU type state has been set and the VFIO container has been +made interactable additional VFIO groups may be added to the container +without requiring that the group\'s IOMMU type be set again as newly +added groups automatically inherit the container\'s IOMMU context. + +### [VFIO Memory Mapped IO]{#VFIO_Memory_Mapped_IO .mw-headline} + +**Figure 3:** Once the VFIO Groups have been placed inside the VFIO +container and the IOMMU type has been set the user may then map and +unmap which will automatically inserts Memory Mapped IO (MMIO) entries +into the IOMMU as well as pin/unpin pages as necessary. This can be +accomplished using **`IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP)`** for +map/pin and **`IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP)`** for +unmap/unpin. + +### [Getting the VFIO Group File Descriptor]{#Getting_the_VFIO_Group_File_Descriptor .mw-headline} + +**Figure 4:** Once the device has been bound to a VFIO driver, set in a +VFIO container, the VFIO container has it\'s IOMMU type set, and a +memory map/page pin of the VFIO device has been completed a file +descriptor can then be obtained for the device. This file descriptor can +be used for interrupts (ioctls), to probe for information about the BAR +regions, and configure the IRQs. + +### [VFIO device file descriptor]{#VFIO_device_file_descriptor .mw-headline} + +VFIO device file descriptors are divided into regions and each region is +mapped into a device resource. Region count and info (file offset, +allowable access, ect..) can be discovered through interrupt (IOCTL). +Each file descriptor region corresponding to a PCI resource is +represented as a file offset. + +In the case of RPC Mode this structure is emulated whereas in SR-IOV +Mode the structure is mapped to a real PCI resource. + + --------------------------------------------------- + 00:00.0 VGA compatible controller + Region 0 Bar0 (Config Space) starts at offset 0 + Region 1 Bar1 (MSI - Message Signaled Interrupts) + Region 2 Bar2 (MSIX) + Region 3 Bar3 + Region 4 Bar4 + Region 5 Bar5 (IO port space) + Expansion ROM + --------------------------------------------------- + + : BAR regions in a VGA PCI device. + +Below is what the file offsets looks like internally for each BAR region +starting from address 0 and growing with the addition of former regions +as you progress through the file. + + --------------------- ------------------- ------------------- ----------------------- ------ + \<- File Offset -\> + 0 -\> A A -\> (A+B) (A+B) -\> (A+B+C) (A+B+C) -\> (A+B+C+D) \... + Region 0 (size A) Region 1 (size B) Region 2 (size C) Region 3 (size D) \... + --------------------- ------------------- ------------------- ----------------------- ------ + + : VFIO representation of PCI BAR regions offsets. + +### [VFIO Interrupts]{#VFIO_Interrupts .mw-headline} + +Guests communicate with the host via VFIO Interrupt Requests +([IRQs](https://infogalactic.com/info/Interrupt_request_(PC_architecture)){.external +.text rel="nofollow"}). These are sent via an irqfd (IRQ [File +Descriptor](https://infogalactic.com/info/File_descriptor){.external +.text rel="nofollow"}). Similarly, the host receives these interrupts +via +[eventfd](https://man7.org/linux/man-pages/man2/eventfd.2.html){.external +.text rel="nofollow"} (Event File Descriptor). The resulting data can be +returned via a +[callback](https://infogalactic.com/info/Callback_(computer_programming)){.external +.text rel="nofollow"}. + +#### [IRQs]{#IRQs .mw-headline} + +Device properties discovered via interrupt (IOCTL). + +##### [Get Device Info]{#Get_Device_Info .mw-headline} + + ------------------------- ------------- ---------------------------- + VFIO_DEVICE_GET_INFO + struct vfio_device_info + argz + flags + VFIO_DEVICE_FLAGS_PCI + VFIO_DEVICE_FLAGS_PLATFORM + VFIO_DEVICE_FLAGS_RESET + num_irqs + num_regions + ------------------------- ------------- ---------------------------- + +The IRQ **`VFIO_DEVICE_GET_INFO`** can provide information to +distinguish between PCI and platform devices as well as the number of +regions and IRQs for a particular device. + +The upstream API can be read **[here +(vfio.h)](https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L194){.external +.text rel="nofollow"}**. + +**Sample mdev code** to service this request can be found +**[here](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L470){.external +.text rel="nofollow"}**, and +**[here](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L522){.external +.text rel="nofollow"}**. + +##### [Get Region Info]{#Get_Region_Info .mw-headline} + + ----------------------------- ------------ ----------------------------- + VFIO_DEVICE_GET_REGION_INFO + struct vfio_region_info + argz + cap_offset + flags + VFIO_REGION_INFO_FLAG_CAPS + VFIO_REGION_INFO_FLAG_MMAP + VFIO_REGION_INFO_FLAG_READ + VFIO_REGION_INFO_FLAG_WRITE + index + offset + size + ----------------------------- ------------ ----------------------------- + +Once the interrupt user knows the number of regions within a VFIO device +they can use IRQ **`VFIO_DEVICE_GET_REGION_INFO`** to probe each region +for additional information. This interrupt will return information such +as if it can be read from or written to, if the device supports MMAP, as +well as what the offset and size of the region is within the VFIO file +descriptor. + +The upstream API can be read [**here +(vfio.h)**](https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L240){.external +.text rel="nofollow"}. + +**Sample mdev code** to service this request can be found +[**here**](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L425){.external +.text rel="nofollow"}, and +[**here**](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L545){.external +.text rel="nofollow"}. + +##### [Get IRQ Info]{#Get_IRQ_Info .mw-headline} + + -------------------------- ------- -------------------------- + VFIO_DEVICE_GET_IRQ_INFO + struct vfio_irq_info + argz + count + flags + VFIO_IRQ_INFO_AUTOMASKED + VFIO_IRQ_INFO_EVENTFD + VFIO_IRQ_INFO_MASKABLE + VFIO_IRQ_INFO_NORESIZE + index + -------------------------- ------- -------------------------- + +**`VFIO_DEVICE_GET_IRQ_INFO`** is used to retrieve information about a +device IRQ. + +**`VFIO_IRQ_INFO_AUTOMASKED`** is used to mask interrupts when they +occur to protect the host. + +The upstream API can be read **[here +(vfio.h)](https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L480){.external +.text rel="nofollow"}** + +**Sample mdev code** to service this request can be found +[**here**](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L463){.external +.text rel="nofollow"}, and +[**here**](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L570){.external +.text rel="nofollow"}. + +##### [Set IRQs]{#Set_IRQs .mw-headline} + + ---------------------- ---------- ----------------------------- + VFIO_DEVICE_SET_IRQS + struct vfio_irq_set + argz + count + data\[\] + flags + VFIO_IRQ_SET_ACTION_MASK + VFIO_IRQ_SET_ACTION_TRIGGER + VFIO_IRQ_SET_ACTION_UNMASK + VFIO_IRQ_SET_DATA_BOOL + VFIO_IRQ_SET_DATA_EVENTFD + VFIO_IRQ_SET_DATA_NONE + index + start + ---------------------- ---------- ----------------------------- + +**`VFIO_DEVICE_SET_IRQS`** is used to setup IRQs. Actions can be +configured such as trigger which is when the device triggers an +interrupt (IOCTL), masking and unmasking actions can be set. Bool and +None data types are used for loopback testing of the device. Start and +index may be used to modify subregions. + +The upstream API can be read **[here +(vfio.h)](https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L524){.external +.text rel="nofollow"}**. + +### []{#Device_Decomposure.2FRecomposure}[Device Decomposure/Recomposure]{#Device_Decomposure/Recomposure .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 5: Device Decomposure and Recomposure via +VFIO.](images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/300px-Device_Decomposure_and_Recomposure_via_VFIO.png){.thumbimage +decoding="async" width="300" height="147" +srcset="images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/450px-Device_Decomposure_and_Recomposure_via_VFIO.png 1.5x, images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/600px-Device_Decomposure_and_Recomposure_via_VFIO.png 2x"}](index.php/File:Device_Decomposure_and_Recomposure_via_VFIO.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Device_Decomposure_and_Recomposure_via_VFIO.png.html "Enlarge"){.internal} +::: + +**Figure 5:** Device Decomposure and Recomposure via VFIO. See slides +from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 5:** Virtual Function IO (VFIO) devices are deconstructed in +userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, +VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon +assignment of a Virtual Function (VF) to a QEMU virtual machine. + +### []{#Memory_Management_Unit_.28MMU.29}[Memory Management Unit (MMU)]{#Memory_Management_Unit_(MMU) .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +::: {.MediaTransformError style="width: 300px; height: 275px; display:inline-block;"} +Error creating thumbnail: File missing +::: + +::: thumbcaption +::: magnify +[](index.php/File:Figure_6-_MMU_-_GMMU_IOVA_translation-isolation..png.html "Enlarge"){.internal} +::: + +**Figure 6:** MMU - GMMU IOVA translation/isolation. +::: +::: +::: + +**Figure 6:** This section will touch upon the mechanisms used for +enforcement of Host Physical Address (HPA) to Guest Physical Address +(GPA) isolation. + +#### []{#MMIO_Isolation_.28Platform_MMU.29}[MMIO Isolation (Platform MMU)]{#MMIO_Isolation_(Platform_MMU) .mw-headline} + +The platform\'s CPU communicates with the GPU by reading/writing to and +from pinned MMIO pages in [Random Access Memory +(RAM)](https://infogalactic.com/info/Random-access_memory){.external +.text rel="nofollow"}. MMIO pages within the RAM are subject to IO +Virtual Address (IOVA) translations by the platform\'s discrete MMU +controller which is programmed by the CPU. These IOVA translations serve +as a mechanism to enforce HPA to GPA isolation in the context of the +platform. + +#### []{#VRAM_Isolation_.28GPU_GMMU.29}[VRAM Isolation (GPU GMMU)]{#VRAM_Isolation_(GPU_GMMU) .mw-headline} + +The GPU core performs virtualized operations by reading/writing to and +from shadow page tables in onboard [Video Random Access Memory +(VRAM)](https://en.wikipedia.org/wiki/Video_random_access_memory "wikipedia:Video random access memory"){.extiw}. +Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) +translations by the GPU\'s discrete GPU MMU controller (GMMU) which is +programmed by the Embedded CPU (GPU co-processor). These IOVA +translations serve as a mechanism to enforce HPA to GPA isolation in the +context of the virtual GPUs and multi-process isolation in single user +environments. + +#### []{#Platform_MMIO_.3C-.3E_GPU_Shadow_Pages}[Platform MMIO \<-\> GPU Shadow Pages]{#Platform_MMIO_<->_GPU_Shadow_Pages .mw-headline} + +In the context of VFIO pinned MMIO pages in RAM act as an interface to +communicate with VRAM shadow pages allowing GPU drivers on the platform +to send instructions to the GPU. When the GPU or Platform alters memory +contained in a shadow page or pinned MMIO page the change is mirrored in +the corresponding IO Virtual Address (IOVA). For example if shadow page +0 is changed by the GPU this change is mirrored in MMIO page 0 on the +platform (the reverse example also applies). When communications occur +between the platform and GPU the information first moves through the +MMU/GMMU and is then written to RAM/VRAM. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 7: A depiction of region overlays within a VFIO file +descriptor.](images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/300px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png){.thumbimage +decoding="async" width="300" height="268" +srcset="images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/450px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 1.5x, images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/600px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 2x"}](index.php/File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html "Enlarge"){.internal} +::: + +**Figure 7:** A depiction of region overlays within a VFIO file +descriptor. See slides from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +### []{#VFIO_Quirks_.28region_traps.29}[VFIO Quirks (region traps)]{#VFIO_Quirks_(region_traps) .mw-headline} + +**Figure 7:** Regions of the PCI BAR require emulation (slow path) via +emulated traps (known as quirks). These regions are primarily in PCI +configuration space. QEMU may overlap a region overlay which when +read/written to/from triggers a VM-exit to trap and emulate the region +in order that appropriate translations may occur (such as those +concerned with IO Virtual Address - IOVA). + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Peer-to-Peer DMA Isolation under +IOMMU](images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/300px-Screen_Shot_2022-05-06_at_10.46.59_AM.png){.thumbimage +decoding="async" width="300" height="224" +srcset="images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/450px-Screen_Shot_2022-05-06_at_10.46.59_AM.png 1.5x, images/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png 2x"}](index.php/File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html "Enlarge"){.internal} +::: + +**Figure 8:** Peer-to-Peer DMA Isolation under IOMMU. See slides from: +[\[2\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +### [Known IOMMU Issues]{#Known_IOMMU_Issues .mw-headline} + +**DMA Aliasing** + +- Not all devices generate unique IDs. +- Not all devices generate IDs they should.\ + +**DMA Isolation** + +- **Figure 8:** Peer-to-Peer DMA Isolation. In many circumstances IO + Virtual Address (IOVA) translations do not occur properly in the + context of DMA peering. Transactions that occur through the IOMMU + are unaffected. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 0: Approches to GPU +Virtualization.](images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/300px-Figure_0-_Approches_to_GPU_Virtualization..png){.thumbimage +decoding="async" width="300" height="153" +srcset="images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/450px-Figure_0-_Approches_to_GPU_Virtualization..png 1.5x, images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/600px-Figure_0-_Approches_to_GPU_Virtualization..png 2x"}](index.php/File:Figure_0-_Approches_to_GPU_Virtualization..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Figure_0-_Approches_to_GPU_Virtualization..png.html "Enlarge"){.internal} +::: + +**Figure 0:** Approaches to GPU Virtualization. See slides from: +[\[61\]](index.php/Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +## [Mdev Mode]{#Mdev_Mode .mw-headline} + +**Mdev Mode (VFIO Mediated Device)** is a method of virtualizing I/O +devices enabling full API capabilities without the requirement for +hardware assistance. + +### [Knowledge Resources Used]{#Knowledge_Resources_Used_2 .mw-headline} + +This section is supported by significant contributions in open source by +Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, +Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. + +See references 1, 7, 8, 17, 18, 19, 70 in the [References (Talks & +Reading +Material)](index.php/Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} section. + +### [Mediated Core]{#Mediated_Core .mw-headline} + +The mediated device framework made 3 major changes to the VFIO driver. + +- **1: [Mediated core module + (new)](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_core.c){.external + .text rel="nofollow"}**\ + -Mediated bus driver, create mediated device.\ + -Physical device interface for vendor callbacks.\ + -Generic Mediated device management user interface (sysfs). +- **2: [Mediated device module + (new)](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_driver.c){.external + .text rel="nofollow"}**\ + -Manage created mediated device, fully compatible with VFIO user API + (UAPI). +- **3: [VFIO IOMMU driver + (enhancement)](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/vfio_iommu_type1.c){.external + .text rel="nofollow"}**\ + -VFIO IOMMU API Type1 compatible, easy to extend to non-Type1. + +The full list of these changes can be seen in the [**lists.gnu.org +Qemu-devel** mailing list +archive](https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg03922.html){.external +.text rel="nofollow"}. + +### [Device Initialization]{#Device_Initialization .mw-headline} + +This section will deal with how an Mdev driver is initialized. + +**Sample mdev code** for device initialization can be found +**[here](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L229){.external +.text rel="nofollow"}**. + +#### [Registering VFIO MDEV as a driver]{#Registering_VFIO_MDEV_as_a_driver .mw-headline} + +VFIO Mdev must be registered as a driver. This register event occurs +between the Mdev Driver Register Interface and the VFIO MDEV interface. + +#### [Registering PCIE Device with the Mediated Core]{#Registering_PCIE_Device_with_the_Mediated_Core .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Registering the mediated +device.](images/thumb/7/75/Mdev-gpu.png/300px-Mdev-gpu.png){.thumbimage +decoding="async" width="300" height="208" +srcset="images/thumb/7/75/Mdev-gpu.png/450px-Mdev-gpu.png 1.5x, images/thumb/7/75/Mdev-gpu.png/600px-Mdev-gpu.png 2x"}](index.php/File:Mdev-gpu.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Mdev-gpu.png.html "Enlarge"){.internal} +::: + +**Figure 9:** Registering the mediated device. This step may be +accomplished via the vendor driver or via +[GVM/Mdev-GPU](){.external .text +rel="nofollow"} for drivers which do not include support for Mdev +functionality and/or do not support arbitrary Mdev types. +::: +::: +::: + +**Figure 9:** The vendor driver must register with the Mediated Core\'s +Device Register Interface. The example shown uses the [GVM +Project](){.external .text rel="nofollow"}\'s +[Mdev-GPU](){.external .text +rel="nofollow"} component to accomplish this step on behalf of the +vendor driver. + +#### []{#Registering_Mediated_Callbacks_.28CBs.29}[Registering Mediated Callbacks (CBs)]{#Registering_Mediated_Callbacks_(CBs) .mw-headline} + +**Figure 9:** The vendor driver must now register Mediated Callbacks +which it expects to receive from Mdev devices. The example shown uses +the [GVM Project](){.external .text +rel="nofollow"}\'s +[Mdev-GPU](){.external .text +rel="nofollow"} component to accomplish this step on behalf of the +vendor driver. + +#### [Creating a Mediated Device via mdev-sysfsdev API]{#Creating_a_Mediated_Device_via_mdev-sysfsdev_API .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/300px-Echoing_a_UUID_into_the_sysfsdev_API.png){.thumbimage +decoding="async" width="300" height="235" +srcset="images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/450px-Echoing_a_UUID_into_the_sysfsdev_API.png 1.5x, images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/600px-Echoing_a_UUID_into_the_sysfsdev_API.png 2x"}](index.php/File:Echoing_a_UUID_into_the_sysfsdev_API.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Echoing_a_UUID_into_the_sysfsdev_API.png.html "Enlarge"){.internal} +::: + +**Figure 10:** Echoing a UUID into the mdev-sysfsdev API. This +functionality is included in +[mdevctl](https://github.com/mdevctl/mdevctl){.external .text +rel="nofollow"} and in [](){.external .text +rel="nofollow"}. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 10:** The user of an mdev capable device driver may echo values +such as a UUID into the mdev-sysfsdev interface to create a unique +mediated device. UUIDs must be unique per mdev device within a host. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev +file +descriptor.](images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/300px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png){.thumbimage +decoding="async" width="300" height="231" +srcset="images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/450px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 1.5x, images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/600px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 2x"}](index.php/File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html "Enlarge"){.internal} +::: + +**Figure 11:** QEMU creates VFIO-mdev IOMMU binding and acquires mdev +file descriptor. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +#### [QEMU adds VFIO device to IOMMU container-group]{#QEMU_adds_VFIO_device_to_IOMMU_container-group .mw-headline} + +**Figure 11:** When starting a QEMU process with a VFIO-mdev attached +QEMU calls the VFIO API to add the VFIO device to an IOMMU +container/group. QEMU then runs the IOCTL to obtain a file descriptor +for the device. + +#### [QEMU passes mdev device file descriptor to VM]{#QEMU_passes_mdev_device_file_descriptor_to_VM .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 11: QEMU presenting the VFIO file descriptor into the virtual +machine.](images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/300px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png){.thumbimage +decoding="async" width="300" height="234" +srcset="images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/450px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 1.5x, images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/600px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 2x"}](index.php/File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html "Enlarge"){.internal} +::: + +**Figure 12:** QEMU presenting the VFIO file descriptor into the virtual +machine. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 12:** Once QEMU has obtained the VFIO file descriptor for the +Mdev device via IOCTL it is then QEMU\'s job to present the file +descriptor into the virtual machine so that the mdev may be used by the +guest. + +### [Instruction Execution]{#Instruction_Execution .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![](images/thumb/a/aa/Ioeventfd-and-irqfd.png/300px-Ioeventfd-and-irqfd.png){.thumbimage +decoding="async" width="300" height="215" +srcset="images/thumb/a/aa/Ioeventfd-and-irqfd.png/450px-Ioeventfd-and-irqfd.png 1.5x, images/thumb/a/aa/Ioeventfd-and-irqfd.png/600px-Ioeventfd-and-irqfd.png 2x"}](index.php/File:Ioeventfd-and-irqfd.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Ioeventfd-and-irqfd.png.html "Enlarge"){.internal} +::: + +**Figure 13:** A simple diagram of signalling from host to guest (via +irqfd) & guest to host (via ioeventfd) From +[blog.allenx](http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 13:** Mdev Mode moves instruction information across a virtual +function (VF) device using [Remote Procedure +Calls](https://infogalactic.com/info/Remote_procedure_call){.external +.text rel="nofollow"} generally by way of [software +interrupt](https://infogalactic.com/info/Interrupt){.external .text +rel="nofollow"} +([IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external +.text rel="nofollow"}). Signals to and from the guest and the host GPU +driver may be passed over file descriptors such as the [Interrupt +Request File Descriptor +(irqfd)](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3){.external +.text rel="nofollow"} and [IO Event File Descriptor +(ioeventfd)](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a){.external +.text rel="nofollow"}. The irqfd may be used to signal from the host +into the guest whereas the ioeventfd may be used to signal from the +guest into the host. Guest GPU instructions which would normally +serialize as pRPCs (physical Remote Procedure Calls) are instead +serialized from the guest as vRPCs (virtual Remote Procedure Calls) +which are executed by the host mediated driver. + +#### [IRQ remapping]{#IRQ_remapping .mw-headline} + +Interrupt Requests (IRQs) must be remapped (trapped for virtualized +execution) to protect the host from sensitive instructions which may +affect global memory state. + +#### [Interrupt Injection]{#Interrupt_Injection .mw-headline} + +**\--** + +**\--Researching\--** + +**\--** + +### [Memory Management]{#Memory_Management .mw-headline} + +Mdev memory management is handled by vendor driver software. + +#### [Region Passthrough]{#Region_Passthrough .mw-headline} + +Guests may be presented with emulated memory regions or via passthrough +regions or a mixture of the two such as in the case of passthrough +regions with BAR 0 configuration space emulation while other regions are +passthrough\'d. + +##### [Emulated Regions]{#Emulated_Regions .mw-headline} + +Emulated memory regions use indirect emulated communication requiring a +VM-exit (slow). These regions are often used for virtual PCI config +space such as [in this sample +code](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L112){.external +.text rel="nofollow"}. + +##### [Passthrough Regions]{#Passthrough_Regions .mw-headline} + +Passthrough memory regions use direct communication requiring no VM-exit +(fast). + +##### [Region Access]{#Region_Access .mw-headline} + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 13: QEMU gets region info via VFIO UAPI from vendor driver +through vfio-mdev and Mediated +CBs](images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/300px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png){.thumbimage +decoding="async" width="300" height="236" +srcset="images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/450px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 1.5x, images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/600px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 2x"}](index.php/File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html "Enlarge"){.internal} +::: + +**Figure 14:** QEMU gets region info via VFIO UAPI from vendor driver +through vfio-mdev and Mediated CBs. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 14:** QEMU gets region information via VFIO User API (UAPI) +from the vendor driver through VFIO-mdev and Mediated Callbacks. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +::: {.MediaTransformError style="width: 300px; height: 238px; display:inline-block;"} +Error creating thumbnail: File missing +::: + +::: thumbcaption +::: magnify +[](index.php/File:Guest_driver_accessing_Mdev_MMIO_space_backed_by_mdev_file_descriptor_triggers_EPT_violation..png.html "Enlarge"){.internal} +::: + +**Figure 15:** Guest driver accessing Mdev MMIO space backed by mdev +file descriptor triggers EPT violation. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 15:** The guest\'s vendor driver accesses the Mdev MMIO trapped +region backed by a mdev file descriptor (fd) which triggers an Extended +Page Table (EPT) violation. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI +driver.](images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/300px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png){.thumbimage +decoding="async" width="300" height="235" +srcset="images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/450px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 1.5x, images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/600px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 2x"}](index.php/File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html "Enlarge"){.internal} +::: + +**Figure 16:** KVM services EPT violation and forwards to QEMU VFIO PCI +driver. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 16:** KVM services EPT violation and forwards to QEMU VFIO PCI +driver. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev +file +descriptor.](images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/300px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png){.thumbimage +decoding="async" width="300" height="235" +srcset="images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/450px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 1.5x, images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/600px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 2x"}](index.php/File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html "Enlarge"){.internal} +::: + +**Figure 17:** QEMU convert request from KVM to Read/Write acess to Mdev +file descriptor. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 17:** QEMU convert request from KVM to R/W access to Mdev file +descriptor. + +#### [EPT Page Violations]{#EPT_Page_Violations .mw-headline} + +Guest [Memory Mapped IO +(MMIO)](https://infogalactic.com/info/Memory-mapped_I/O){.external .text +rel="nofollow"} trips Extended Page Table (EPT) violations which are +trapped by the host MMU. KVM services EPT violations and forwards to +QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W +access to the [Mdev File Descriptor +(FD)](https://infogalactic.com/info/File_descriptor){.external .text +rel="nofollow"}. Reads and writes are then handled by the host GPU +device driver via mediated [callbacks +(CBs)](https://infogalactic.com/info/Callback_(computer_programming)){.external +.text rel="nofollow"} and +[VFIO-mdev](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst){.external +.text rel="nofollow"}. + +#### [Mediated DMA Translations]{#Mediated_DMA_Translations .mw-headline} + +**\--** + +**\--Researching\--** + +**\--** + +Because memory is not statically allocated by the vendor driver under +the mediated device framework there is no requirement to make use of +traditional VFIO pinned pages (via the vfio-pci module) rather MMIO +memory can be mapped at runtime incrementally. As a result non-standard +mediated device vfio stub modules may be used. + +**Figure 18:** Memory regions get added by QEMU. + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Memory Regions Added by +QEMU](images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/300px-Memory_Regions_Added_by_QEMU.png){.thumbimage +decoding="async" width="300" height="225" +srcset="images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/450px-Memory_Regions_Added_by_QEMU.png 1.5x, images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/600px-Memory_Regions_Added_by_QEMU.png 2x"}](index.php/File:Memory_Regions_Added_by_QEMU.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Memory_Regions_Added_by_QEMU.png.html "Enlarge"){.internal} +::: + +**Figure 18:** Memory Regions Added by QEMU. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 19:** QEMU calls VFIO_DMA_MAP via Memory listener. (not just +guest physical memory but also device memory will be added through this +memory listener) + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![QEMU calls VFIO DMA MAP via Memory +listener](images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/300px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png){.thumbimage +decoding="async" width="300" height="237" +srcset="images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/450px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 1.5x, images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/600px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 2x"}](index.php/File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html "Enlarge"){.internal} +::: + +**Figure 19:** QEMU calls VFIO DMA MAP via Memory listener. See slides +from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +::: {.thumb .tright} +::: {.thumbinner style="width:302px;"} +[![Type 1 IOMMU Tracks +VA-GFN](images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/300px-Type_1_IOMMU_Tracks_VA-GFN.png){.thumbimage +decoding="async" width="300" height="237" +srcset="images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/450px-Type_1_IOMMU_Tracks_VA-GFN.png 1.5x, images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/600px-Type_1_IOMMU_Tracks_VA-GFN.png 2x"}](index.php/File:Type_1_IOMMU_Tracks_VA-GFN.png.html){.image} + +::: thumbcaption +::: magnify +[](index.php/File:Type_1_IOMMU_Tracks_VA-GFN.png.html "Enlarge"){.internal} +::: + +**Figure 20:** Type 1 IOMMU Tracks \. See slides from: +[\[1\]](index.php/Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} +::: +::: +::: + +**Figure 20:** Type 1 IOMMU tracks \. We +build a table to list the QEMU VAs and track the their mapping relation +to Guest Frame Numbers (GFNs). + +### [Scheduling]{#Scheduling .mw-headline} + +Scheduling is handled by the host mdev driver. + +### [Kernel API]{#Kernel_API .mw-headline} + +Kernel documentation used for implementing a VFIO Mediated Device may be +found at +[kernel.org](https://www.kernel.org/doc/html/latest/driver-api/vfio-mediated-device.html){.external +.text rel="nofollow"}. + +### [Sample Code]{#Sample_Code .mw-headline} + +Sample code for various mdev implementations may be found below: + +**Mediated Virtual PCI Display Host Device:** + +1. [mdpy.c](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy.c){.external + .text rel="nofollow"} +2. [mdpy-fb.c](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy-fb.c){.external + .text rel="nofollow"} +3. [mbochs.c](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mbochs.c){.external + .text rel="nofollow"}. + +**Serial PCI Port-based Mediated Device:** + +1. [mtty.c](https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mtty.c){.external + .text rel="nofollow"}. + +###### [Compilation]{#Compilation .mw-headline} + +To compile the kernel modules linked above you should have your +distro\'s equivalent of the build-essential package installed. The +included Makefile should provide all that is necessary to successfully +compile the kernel modules. You can type the following command to +compile the modules from within the directory: + +`make` + +When the make operation has been completed successfully the directory +will now contain .ko files. These files are the binary kernel modules. + +###### [Loading Kernel Modules]{#Loading_Kernel_Modules .mw-headline} + +Now that you have compiled the kernel modules you may load them via the +insmod command. + +For example to load the **mtty.ko** module run the following command +from within the directory where you built the modules: + +`insmod mtty.ko` + +###### [Unloading Kernel Modules]{#Unloading_Kernel_Modules .mw-headline} + +To unload any of the kernel modules you may make use of the rmmod +command. + +For example to unload the **mtty.ko** module run the following command: + +`rmmod mtty.ko` + +###### [Additional Documentation]{#Additional_Documentation .mw-headline} + +An additional guide explaining how to make use of the mtty.c sample code +may be found at [line +308](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294#n308){.external +.text rel="nofollow"} of the kernel.org VFIO Mediated Device +documentation. + +### [Mdev Mode Requirements]{#Mdev_Mode_Requirements .mw-headline} + +Driver Support. + +Software HPA\<-\>GPA Boundary Enforcement. + +## [SR-IOV Mode]{#SR-IOV_Mode .mw-headline} + +**SR-IOV Mode (Single Root I/O Virtualization)** involves hardware +assisted virtualization on I/O peripherals. + +### [Knowledge Resources Used]{#Knowledge_Resources_Used_3 .mw-headline} + +This section is supported by significant contributions in open source by +Zheng Xiao, Jerry Jiang, & Ken Xue. + +See reference 6 in the [References (Talks & Reading +Material)](index.php/Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} section. + +### [Instruction Execution]{#Instruction_Execution_2 .mw-headline} + +SR-IOV communicates instructions from a virtual function (VF) directly +to the [PCI +BAR](https://infogalactic.com/info/PCI_configuration_space){.external +.text rel="nofollow"}. + +### [Memory Management]{#Memory_Management_2 .mw-headline} + +Guests are presenting with passthrough memory regions by the device +firmware. + +### [Scheduling]{#Scheduling_2 .mw-headline} + +Scheduling may be handled by the host mdev driver and/or the device +firmware. + +### [SR-IOV Mode Requirements]{#SR-IOV_Mode_Requirements .mw-headline} + +Driver Support. + +Device SR-IOV support. + +Firmware HPA\<-\>GPA Boundary Enforcement. + +## [SIOV Mode]{#SIOV_Mode .mw-headline} + +**SIOV (Scalable I/O Virtualization)** involves the combination of +concepts form both [SR-IOV +Mode](index.php/Mediated_Device_Internals.html#SR-IOV_Mode){.external +.text rel="nofollow"} and [Mdev +Mode](index.php/Mediated_Device_Internals.html#Mdev_Mode){.external +.text rel="nofollow"} as well as novel concepts like shared IOMMU aware +buffers and offloading of PCI config space VM-exits (slow path) to a +discrete controller. + +**Revision 1.0 of the SIOV specification** can be read on the [Open +Compute Project +website](https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf){.external +.text rel="nofollow"}. + +### [Knowledge Resources Used]{#Knowledge_Resources_Used_4 .mw-headline} + +This section is supported by significant contributions in open source by +Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. + +See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the [References (Talks +& Reading +Material)](index.php/Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)){.external +.text rel="nofollow"} section. + +### [Memory Management]{#Memory_Management_3 .mw-headline} + +Enhancements to [Intel +VT-d](https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/002/intel-virtualization-technology-for-directed-i-o/){.external +.text rel="nofollow"} introduce new \'Scalable Mode\' to allow the +platform to assign more granular IOMMU allocations to mediated devices +([mdev memory +management](index.php/Mediated_Device_Internals.html#Memory_Management){.external +.text rel="nofollow"}). This change is referred to as an IOMMU Aware +Mediated Device. + +#### [IOMMU Aware Mediated Device]{#IOMMU_Aware_Mediated_Device .mw-headline} + +SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated +Device Framework. + +The full list of these changes can be seen in the [mailing list archive +on **lwn.net** under **(vfio/mdev: IOMMU aware mediated +device)**](https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/){.external +.text rel="nofollow"}. + +#### [Shared Hardware Workqueues]{#Shared_Hardware_Workqueues .mw-headline} + +SIOV makes use of Shared Hardware Workqueues which may be accessed by +processes or Virtual Machines. + +[According to +**kernel.org**](https://www.kernel.org/doc/html/latest/x86/sva.html){.external +.text rel="nofollow"}: *\"In order to allow the hardware to distinguish +the context for which work is being executed in the hardware by SWQ +interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit +number defined by the PCIe SIG. PASID value is encoded in all +transactions from the device. This allows the IOMMU to track I/O on a +per-PASID granularity in addition to using the PCIe Resource Identifier +(RID) which is the Bus/Device/Function.\"* + +### [SIOV Mode Requirements]{#SIOV_Mode_Requirements .mw-headline} + +Driver Support. + +Device SIOV support. + +Firmware HPA\<-\>GPA Boundary Enforcement. + +## []{#References_.28Talks_.26_Reading_Material.29}[References (Talks & Reading Material)]{#References_(Talks_&_Reading_Material) .mw-headline} + +1. [\[2016\] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti + Wankhede](https://www.youtube.com/watch?v=Xs0TJU_sIPc){.external + .text rel="nofollow"} - + [slides](https://www.linux-kvm.org/images/5/59/02x03-Neo_Jia_and_Kirti_Wankhede-vGPU_on_KVM-A_VFIO_based_Framework.pdf){.external + .text rel="nofollow"} +2. [\[2016\] An Introduction to PCI Device Assignment with VFIO by Alex + Williamson](https://www.youtube.com/watch?v=WFkdTFTOTpA){.external + .text rel="nofollow"} - + [slides](http://events17.linuxfoundation.org/sites/events/files/slides/An%20Introduction%20to%20PCI%20Device%20Assignment%20with%20VFIO%20-%20Williamson%20-%202016-08-30_0.pdf){.external + .text rel="nofollow"} +3. [\[2017\] Scalable I/O Virtualization by Kevin + Tian](https://events19.linuxfoundation.cn/wp-content/uploads/2017/11/Intel%C2%AE-Scalable-I_O-Virtualization_Kevin-Tian.pdf){.external + .text rel="nofollow"} +4. [\[2019\] Bring a Scalable IOV Capable Device into Linux World by + Xin Zeng & Yi + Liu](https://www.youtube.com/watch?v=G6D-jaCs6sc){.external .text + rel="nofollow"} - + [slides](https://static.sched.com/hosted_files/kvmforum2019/5e/Bring%20a%20scalable%20IOV%20capable%20device%20into%20Linux%20-%20KVM%202019.pdf){.external + .text rel="nofollow"} +5. [Scalable I/O Virtualization Revision + 1.0](https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf){.external + .text rel="nofollow"} +6. [\[2018\] Live Migration Support for GPU with SRIOV by Zheng Xiao, + Jerry Jiang & Ken + Xue](https://www.youtube.com/watch?v=_tB3EbFDcRQ){.external .text + rel="nofollow"} - + [slides](https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Live-Migration-Support-for-GPU-with-SRIOV-Challenges-and-Solution-Zheng-Xiao-Alibaba-Cloud-Jerry-Jiang-Ken-Xue-AMD.pdf){.external + .text rel="nofollow"} +7. [\[2017\] Intel GVT-g: From Production to Upstream - Zhi Wang, + Intel](https://www.youtube.com/watch?v=UODxW1opfn0){.external .text + rel="nofollow"} +8. [\[2016\] Qemu Graphics Update 2016 by Gerd + Hoffmann](https://www.youtube.com/watch?v=DKYvQ3FdFeo){.external + .text rel="nofollow"} +9. [IOCTL](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst){.external + .text rel="nofollow"} +10. [eventfd](https://man7.org/linux/man-pages/man2/eventfd.2.html){.external + .text rel="nofollow"} - + [root/virt/kvm/eventfd.c](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/eventfd.c){.external + .text rel="nofollow"} +11. (kernel diff:: [KVM: + irqfd](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3){.external + .text rel="nofollow"}) +12. (kernel diff:: [KVM: add ioeventfd + support](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a){.external + .text rel="nofollow"}) +13. [KVM irqfd & + ioeventfd](https://web.archive.org/web/20220120223711/http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd){.external + .text rel="nofollow"} +14. [VFIO - Virtual Function + I/O](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio.rst){.external + .text rel="nofollow"} - + [root/virt/kvm/vfio.c](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/vfio.c){.external + .text rel="nofollow"} +15. [VFIO Mediated + Devices](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst){.external + .text rel="nofollow"} +16. [IOMMU Aware Mediated + Device](https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/){.external + .text rel="nofollow"} +17. [Hardware-Assisted Mediated Pass-Through with VFIO by Kevin + Tian](https://www.youtube.com/watch?v=95KSKrZM8oQ){.external .text + rel="nofollow"} +18. [\[2017\] Generic Buffer Sharing Mechanism for Mediated Devices by + Tina Zhang](https://www.youtube.com/watch?v=cHMLBcHplhk){.external + .text rel="nofollow"} +19. [\[2019\] Toward a Virtualization World Built on Mediated + Pass-Through - Kevin + Tian](https://www.youtube.com/watch?v=KWRKx_uxUDI){.external .text + rel="nofollow"} +20. [Auxiliary + Bus](https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/auxiliary_bus.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294){.external + .text rel="nofollow"} +21. [Shared Virtual + Addressing](https://www.kernel.org/doc/html/latest/x86/sva.html){.external + .text rel="nofollow"} +22. [vfio.blogspot.com](https://vfio.blogspot.com/){.external .text + rel="nofollow"} +23. [XenGT by Kevin + Tian](https://01.org/sites/default/files/xengt.pdf){.external .text + rel="nofollow"} +24. [VMWare Academic Publications: GPU Virtualization by Micah Dowty & + Jeremy + Sugerman](https://web.archive.org/web/20130721094438/http://labs.vmware.com/academic/publications/gpu-virtualization){.external + .text rel="nofollow"} +25. [PCI SIG I/O + Virtualization](https://pcisig.com/specifications/iov){.external + .text rel="nofollow"} +26. [VMGL by the University of Toronto Computer Science + Department](https://web.archive.org/web/20120108034526/http://sysweb.cs.toronto.edu/vmgl){.external + .text rel="nofollow"} +27. [Kepler VGX + Hypervisor](https://web.archive.org/web/20120518125815/http://www.nvidia.com/object/vgx-hypervisor.html){.external + .text rel="nofollow"} +28. [Intel Virtualization Technology for Directed I/O (VT-d): Enhancing + Intel platforms for efficient virtualization of I/O + devices](https://web.archive.org/web/20090218010221/http://software.intel.com/en-us/articles/intel-virtualization-technology-for-directed-io-vt-d-enhancing-intel-platforms-for-efficient-virtualization-of-io-devices){.external + .text rel="nofollow"} +29. [DMA-Mapping.txt (Dynamic DMA + Mapping)](https://lwn.net/2001/0712/a/dma-interface.php3){.external + .text rel="nofollow"} +30. [KVM MMU Virtualization by Xiao + Guangrong](https://events.static.linuxfound.org/slides/2011/linuxcon-japan/lcj2011_guangrong.pdf){.external + .text rel="nofollow"} +31. [OSDEV: PCI](https://wiki.osdev.org/PCI){.external .text + rel="nofollow"} +32. [Down to the TLP: How PCI express devices talk (Part + I)](http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1){.external + .text rel="nofollow"} +33. [Down to the TLP: How PCI express devices talk (Part + II)](http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2){.external + .text rel="nofollow"} +34. [Intel ACRN: Enabling SR-IOV + Virtualization](https://projectacrn.github.io/latest/tutorials/sriov_virtualization.html){.external + .text rel="nofollow"} +35. [Kernel.org + sysfs-bus-pci](https://docs.kernel.org/admin-guide/abi-testing.html#abi-file-testing-sysfs-bus-pci){.external + .text rel="nofollow"} +36. [Linux Kernel Labs: Memory + Mapping](https://linux-kernel-labs.github.io/refs/heads/master/labs/memory_mapping.html){.external + .text rel="nofollow"} +37. [Inside Windows Page Frame Number (PFN) - Part + 1](https://rayanfam.com/topics/inside-windows-page-frame-number-part1/){.external + .text rel="nofollow"} +38. [Direct Rendering Infrastructure + (DRI)](https://en.wikipedia.org/wiki/Direct_Rendering_Infrastructure){.external + .text rel="nofollow"} +39. [DRI User + Guide](https://dri.sourceforge.net/doc/DRIuserguide.html){.external + .text rel="nofollow"} +40. [Linux Kernel Labs: IO + Virtualization](https://linux-kernel-labs.github.io/refs/heads/master/lectures/virt.html#i-o-virtualization){.external + .text rel="nofollow"} +41. [Gallium3D: Main + Page](https://dri.freedesktop.org/doxygen/gallium/){.external .text + rel="nofollow"} +42. [Gallium3D + Wiki](https://web.archive.org/web/20080107043445/http://www.tungstengraphics.com/wiki/index.php/Gallium3D){.external + .text rel="nofollow"} +43. [Gallium3D talk from XDS + 2007](https://web.archive.org/web/20090219182518/http://www.tungstengraphics.com/wiki/files/gallium3d-xds2007.pdf){.external + .text rel="nofollow"} +44. [Memory Management High Level Design + (ARCN)](https://projectacrn.github.io/latest/developer-guides/hld/hv-memmgt.html){.external + .text rel="nofollow"} +45. [Block Architecture Diagrams for Geforce + series](https://web.archive.org/web/20080111122628/http://www.digit-life.com/articles2/gffx/nv40-part1-a.html){.external + .text rel="nofollow"} +46. [Block diagrams for 40 series instruction + format](http://freenv.svn.sourceforge.net/viewvc/freenv/doc/shaderinsnformat/bitdiagen/){.external + .text rel="nofollow"} +47. [PCI Configuration + Space](https://en.wikipedia.org/wiki/PCI_configuration_space "wikipedia:PCI configuration space"){.extiw} +48. [GPU virtual memory in WDDM + 2.0](https://learn.microsoft.com/en-us/windows-hardware/drivers/display/gpu-virtual-memory-in-wddm-2-0){.external + .text rel="nofollow"} +49. [Intel Graphics Programmer\'s Reference Manuals + (PRM)](https://01.org/linuxgraphics/documentation/hardware-specification-prms){.external + .text rel="nofollow"} +50. [i915: Hardware Contexts (and some bits about + batchbuffers)](https://bwidawsk.net/blog/2013/1/i915-hardware-contexts-and-some-bits-about-batchbuffers/){.external + .text rel="nofollow"} +51. [i915: The Global GTT Part + 1](https://bwidawsk.net/blog/2014/6/the-global-gtt-part-1/){.external + .text rel="nofollow"} +52. [i915: Aliasing PPGTT Part + 2](https://bwidawsk.net/blog/2014/6/aliasing-ppgtt-part-2/){.external + .text rel="nofollow"} +53. [i915: True PPGTT Part + 3](https://bwidawsk.net/blog/2014/7/true-ppgtt-part-3/){.external + .text rel="nofollow"} +54. [i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit + address space, GPU \"mirroring\", and yeah, something about relocs + too)](https://bwidawsk.net/blog/2014/7/future-ppgtt-part-4-dynamic-page-table-allocations-64-bit-address-space-gpu-mirroring-and-yeah-something-about-relocs-too/){.external + .text rel="nofollow"} +55. [i915: Security of the Intel Graphics Stack - Part 1 - + Introduction](https://igor-blue.github.io/2021/02/10/graphics-part1.html){.external + .text rel="nofollow"} +56. [i915: Security of the Intel Graphics Stack - Part 2 - FW \<-\> + GuC](https://igor-blue.github.io/2021/02/24/graphics-part2.html){.external + .text rel="nofollow"} +57. [A deep dive into QEMU: PCI slave + devices](https://airbus-seclab.github.io/qemu_blog/pci_slave.html){.external + .text rel="nofollow"} +58. [Debugging QEMU Guests with GDB (start & stop, examine state like + registers & memory, set breakpoints & + watchpoints)](https://qemu-project.gitlab.io/qemu/system/gdb.html){.external + .text rel="nofollow"} +59. [IOMMU + Introduction](https://terenceli.github.io/%E6%8A%80%E6%9C%AF/2019/08/04/iommu-introduction){.external + .text rel="nofollow"} +60. [Arch Wiki: Intel + Graphics](https://wiki.archlinux.org/title/intel_graphics){.external + .text rel="nofollow"} +61. [An Introduction to Intel Graphics Virtualization Technology (legacy + GVT-g) by Zhi + Wang](https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf){.external + .text rel="nofollow"} +62. [Kernel.org: vfio iommu type1: Add support for mediated + devices](https://patchwork.kernel.org/project/qemu-devel/patch/1478293856-8191-11-git-send-email-kwankhede@nvidia.com/){.external + .text rel="nofollow"} +63. [Hardware and Compute Abstraction Layers For Accelerated Computing + Using Graphics Hardware and Conventional + CPUs](https://archive.ll.mit.edu/HPEC/agendas/proc07/Day3/10_Hensley_Abstract.pdf){.external + .text rel="nofollow"} +64. [More Shadow Walker: The Progression of TLB-Splitting on + x86](https://www.blackhat.com/docs/us-14/materials/us-14-Torrey-MoRE-Shadow-Walker-The-Progression-Of-TLB-Splitting-On-x86.pdf){.external + .text rel="nofollow"} +65. [MMU Virtualization Via Intel EPT: Technical + Details](https://revers.engineering/mmu-ept-technical-details/){.external + .text rel="nofollow"} +66. [Alex Williamson Github: VFIO Development (tree + next)](https://github.com/awilliam/linux-vfio/tree/next){.external + .text rel="nofollow"} +67. [GPU PMU: performance monitoring with perf + event](https://events.static.linuxfound.org/slides/2011/linuxcon-japan/lcj2011_linming.pdf){.external + .text rel="nofollow"} +68. [Remote Procedure Call + (RPC)](https://book.systemsapproach.org/e2e/rpc.html){.external + .text rel="nofollow"} +69. [Virtual Open Systems: API + Remoting](http://www.virtualopensystems.com/en/products/api-remoting/){.external + .text rel="nofollow"} +70. [A Full GPU Virtualization Solution with Mediated Pass-Through by + Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu + Dong](https://www.usenix.org/conference/atc14/technical-sessions/presentation/tian){.external + .text rel="nofollow"} - + [\[Paper\]](https://www.usenix.org/system/files/conference/atc14/atc14-paper-tian.pdf){.external + .text rel="nofollow"} - + [\[Video\]](https://www.youtube.com/watch?v=vvYmDQKZ6MQ){.external + .text rel="nofollow"} - [\[Slides + 1\]](https://www.usenix.org/sites/default/files/conference/protected-files/atc14_slides_tian.pdf){.external + .text rel="nofollow"} - [\[Slides + 2\]](https://cseweb.ucsd.edu/~yiying/cse291j-winter20/reading/GPU-Virtualization.pdf){.external + .text rel="nofollow"} +71. [\[2014\] KvmGT: A Full GPU Virtualization Solution by Jike + Song](https://www.youtube.com/watch?v=-iuIu7_GuEo){.external .text + rel="nofollow"} +72. [docs.kernel.org: DRM Memory + Management](https://docs.kernel.org/gpu/drm-mm.html){.external .text + rel="nofollow"} +73. [docs.kernel.org: PCI Bus + Subsystem](https://docs.kernel.org/PCI/index.html){.external .text + rel="nofollow"} +74. [openglbook.com: What is + OpenGL?](https://openglbook.com/chapter-0-preface-what-is-opengl.html){.external + .text rel="nofollow"} +75. [\[2020\] Getting pixels on screen: introduction to Kernel Mode + Setting (KMS) by Simon + Ser](https://yewtu.be/watch?v=haes4_Xnc5Q){.external .text + rel="nofollow"} - + [slides](https://fs.emersion.fr/protected/presentations/present.html?src=kms-foss-north/index.md#1){.external + .text rel="nofollow"} +76. [Dynamic Mediation for Live Migration + VFIO-PCI](https://sdic.sjtu.edu.cn/wp-content/uploads/2019/12/Mediated-Pass-Through-MPT-NVIDIA-vGPU.pptx){.external + .text rel="nofollow"} +77. [DRM Management Via + CGroups](https://lwn.net/Articles/746127/){.external .text + rel="nofollow"} +78. [DRM: Add GEM (\"graphics execution manager\") to i915 + driver.](https://lwn.net/Articles/292583/){.external .text + rel="nofollow"} +::: + +::: printfooter +Retrieved from +\"[https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23792](index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html){dir="ltr"}\" +::: +::: + +::: {#catlinks .catlinks .catlinks-allhidden mw="interface"} +::: +::: +::: + +::: {#mw-navigation} +## Navigation menu + +::: {#mw-head} +### Personal tools {#p-personal-label .vector-menu-heading} + +::: vector-menu-content +- [[Log + in](https://open-iov.org/index.php?title=Special:UserLogin&returnto=Virtual+I%2FO+Internals&returntoquery=oldid%3D23792 "You are encouraged to log in; however, it is not mandatory [o]"){accesskey="o"}]{#pt-login} +::: + +::: {#left-navigation} +### Namespaces {#p-namespaces-label .vector-menu-heading} + +::: vector-menu-content +- [[Page](index.php/Virtual_I/O_Internals.html "View the content page [c]"){accesskey="c"}]{#ca-nstab-main} +- [[Discussion](https://open-iov.org/index.php?title=Talk:Virtual_I/O_Internals&action=edit&redlink=1 "Discussion about the content page (page does not exist) [t]"){rel="discussion" + accesskey="t"}]{#ca-talk} +::: + +### Variants [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-variants-label .vector-menu-heading} + +::: vector-menu-content +::: +::: + +::: {#right-navigation} +### Views {#p-views-label .vector-menu-heading} + +::: vector-menu-content +- [[Read](index.php/Virtual_I/O_Internals.html)]{#ca-view} +- [[View + source](index.php%3Ftitle=Virtual_I%252FO_Internals&action=edit.html "This page is protected. + You can view its source [e]"){accesskey="e"}]{#ca-viewsource} +- [[View + history](index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html "Past revisions of this page [h]"){accesskey="h"}]{#ca-history} +::: + +### More [expanded]{.vector-menu-checkbox-expanded} [collapsed]{.vector-menu-checkbox-collapsed} {#p-cactions-label .vector-menu-heading} + +::: vector-menu-content +::: + +::: {#p-search .vector-search-box role="search"} +
+ +### Search + +::: {#simpleSearch search-loc="header-navigation"} +::: + +
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The GSP firmware implements WPR through two handlers at **0x04F00B0C** and **0x04F00C78** (62 KB each). + +## Key Addresses + +| Handler | Address | Size | Role | +|---------|---------|------|------| +| WPR Handler 1 | 0x04F00B0C | 62 KB | Primary WPR management | +| WPR Handler 2 | 0x04F00C78 | 62 KB | Secondary/timeout handling | +| String Table | 60 locations | — | Completion/timeout strings | + +## String References (60 Total) + +### Completion Events +``` +WPR_WRITE_COMPLETE 0x5E478F8 +WPR_READ_COMPLETE 0x5E478E0 +NV_WPR_WRITE_COMPLETE 0x5E478C8 +NV_WPR_READ_COMPLETE 0x5E478B0 +``` + +### Timeout Events +``` +WPR_WRITE_TIMEOUT 0x5E47898 +WPR_READ_TIMEOUT 0x5E47880 +NV_WPR_WRITE_TIMEOUT 0x5E47868 +NV_WPR_READ_TIMEOUT 0x5E47850 +``` + +## WPR State Machine + +### Handler 1: 0x04F00B0C (Primary) + +```c +typedef enum { + WPR_STATE_IDLE = 0, + WPR_STATE_WRITE_PENDING = 1, + WPR_STATE_READ_PENDING = 2, + WPR_STATE_COMPLETE = 3, + WPR_STATE_TIMEOUT = 4, + WPR_STATE_ERROR = 0xFFFF +} wpr_state_t; + +typedef struct { + uint64_t region_base; // Protected region base + uint64_t region_size; // Region size (page-aligned) + uint32_t vf_id; // Owning VF + uint32_t flags; // WPR_WRITE | WPR_READ | WPR_EXECUTE + wpr_state_t state; + uint64_t timeout_ns; // Operation timeout + void *completion_cb; // Callback on complete + void *timeout_cb; // Callback on timeout +} wpr_region_t; +``` + +### Operation Flow + +#### Write Protect +``` +1. VF requests WPR_WRITE on region [base, base+size) +2. Handler validates alignment (4KB) and permissions +3. Programs MMU/IOMMU write-protect bits +4. Starts timeout timer (configurable) +5. On GPU write attempt: + a. Trap to GSP via page fault + b. Check if VF owns region + c. If allowed: emulate write, return OK + d. If denied: trigger WPR_WRITE_COMPLETE/NV_WPR_WRITE_COMPLETE +6. On timeout: trigger WPR_WRITE_TIMEOUT/NV_WPR_WRITE_TIMEOUT +``` + +#### Read Protect +``` +1. VF requests WPR_READ on region +2. Programs MMU/IOMMU read-protect bits +3. On GPU read attempt: + a. Trap to GSP + b. Return zero/poison data or emulate + c. Trigger WPR_READ_COMPLETE/NV_WPR_READ_COMPLETE +4. On timeout: trigger WPR_READ_TIMEOUT/NV_WPR_READ_TIMEOUT +``` + +## VBIOS Parsing (Handler 2: 0x04F00C78) + +The WPR handlers parse VBIOS structures for legacy compatibility: + +```c +int parse_vbios_for_wpr(void *vbios_ptr, size_t size) { + // Search for signatures: + // 0xAA55 - Standard VBIOS signature + // 0x57464F4E ("WFON") - WPR enable + // 0x5746564E ("WFVN") - WPR version + + for (offset = 0; offset < size; offset += 0x1000) { + uint32_t sig = *(uint32_t*)(vbios_ptr + offset); + + if (sig == 0xAA55) { + // Check for WPR structures + parse_wpr_tables(vbios_ptr + offset); + } + else if (sig == 0x57464F4E || sig == 0x5746564E) { + // WPR enabled in VBIOS + wpr_vbios_enabled = true; + wpr_vbios_offset = offset; + } + } +} +``` + +## Integration with GSP Subsystems + +### Memory Allocator (0x429B450) +```c +// Allocate WPR metadata structures +wpr_region_t *wpr_alloc_region() { + return UNK_ram_058A1A9C(0x429B450, sizeof(wpr_region_t)); +} + +// Allocate bounce buffers for emulation +void *wpr_alloc_bounce(size_t size) { + return UNK_ram_058A1A9C(0x429B450, size); +} +``` + +### DMA/Copy Engine (0x0588F9C4, 0x05AEC86C) +```c +// Copy data for WPR emulation +int wpr_emulate_access(wpr_region_t *rgn, void *dst, void *src, size_t size) { + return UNK_ram_0588F9C4(dma_engine, src, dst, size); +} +``` + +### Logging (0x05AB7DA0) +```c +// Log WPR events +void wpr_log_event(const char *event_str, uint32_t vf_id, uint64_t addr) { + UNK_ram_05AB7DA0(1, &event_str); // Log string + UNK_ram_05AB7DA0(2, &vf_id); // Log VF ID + UNK_ram_05AB7DA0(3, &addr); // Log address +} +``` + +## vGPU-IO Integration + +### Kernel WPR API +```c +struct gsp_wpr_ops { + int (*protect_write)(struct gsp_device *gsp, + uint32_t vf_id, + uint64_t base, uint64_t size); + int (*protect_read)(struct gsp_device *gsp, + uint32_t vf_id, + uint64_t base, uint64_t size); + int (*unprotect)(struct gsp_device *gsp, + uint32_t vf_id, + uint64_t base); + int (*set_timeout)(struct gsp_device *gsp, + uint32_t vf_id, + uint64_t timeout_ns); + int (*register_callback)(struct gsp_device *gsp, + uint32_t vf_id, + enum wpr_event_type type, + void (*cb)(struct wpr_event *)); +}; + +static const struct gsp_wpr_ops gsp_wpr_ops = { + .protect_write = gsp_wpr_write_protect, + .protect_read = gsp_wpr_read_protect, + .unprotect = gsp_wpr_unprotect, + .set_timeout = gsp_wpr_set_timeout, + .register_callback = gsp_wpr_register_callback, +}; +``` + +### VF WPR Lifecycle +```c +// VF initialization: register WPR regions +int gsp_vf_wpr_init(struct gsp_vf *vf) { + // Protect VF's page tables + gsp_wpr_ops.protect_write(vf->gsp, vf->id, + vf->pt_base, vf->pt_size); + + // Protect VF's command buffers + gsp_wpr_ops.protect_write(vf->gsp, vf->id, + vf->cmd_base, vf->cmd_size); + + // Set default timeout (10ms) + gsp_wpr_ops.set_timeout(vf->gsp, vf->id, 10000000); + + // Register completion callbacks + gsp_wpr_ops.register_callback(vf->gsp, vf->id, + WPR_EVENT_WRITE_COMPLETE, + vf_wpr_write_complete_cb); + gsp_wpr_ops.register_callback(vf->gsp, vf->id, + WPR_EVENT_TIMEOUT, + vf_wpr_timeout_cb); + + return 0; +} + +// VF cleanup +void gsp_vf_wpr_fini(struct gsp_vf *vf) { + gsp_wpr_ops.unprotect(vf->gsp, vf->id, vf->pt_base); + gsp_wpr_ops.unprotect(vf->gsp, vf->id, vf->cmd_base); + // ... unregister callbacks +} +``` + +### Callback Handling +```c +static void vf_wpr_write_complete_cb(struct wpr_event *evt) { + struct gsp_vf *vf = evt->vf; + + // Log the write attempt + dev_dbg(vf->dev, "WPR write complete: VF=%u addr=0x%llx\n", + vf->id, evt->address); + + // If this was a page table update, invalidate TLB + if (evt->address >= vf->pt_base && + evt->address < vf->pt_base + vf->pt_size) { + gsp_tlb_invalidate(vf->gsp, vf->id); + } +} + +static void vf_wpr_timeout_cb(struct wpr_event *evt) { + struct gsp_vf *vf = evt->vf; + + dev_warn(vf->dev, "WPR timeout: VF=%u type=%d addr=0x%llx\n", + vf->id, evt->type, evt->address); + + // Escalate: reset VF or throttle + if (evt->type == WPR_EVENT_WRITE_TIMEOUT) { + gsp_vf_throttle(vf); + } else { + gsp_vf_reset(vf); + } +} +``` + +## Error Codes + +| Code | Name | Description | +|------|------|-------------| +| 0x1E | ETIME | Operation timed out | +| 0x1F | EDEV | Device error | +| 0x25 | EOVERFLOW | Region too large | +| 0x37 | EINVAL | Invalid alignment | +| 0x51 | ENOMEM | Out of memory | +| 0x56 | EBUSY | Region busy | +| 0xFFFF | EPERM | Permission denied | + +## Debugging + +### Monitor These Addresses +``` +0x04296048 : Global error flag +0x0429B750+0x111300 : Error status register +0x05E47850-0x05E478F8 : WPR string table +``` + +### GSP Log Patterns +``` +WPR_WRITE_COMPLETE VF= ADDR= +WPR_READ_COMPLETE VF= ADDR= +WPR_WRITE_TIMEOUT VF= ADDR= +WPR_READ_TIMEOUT VF= ADDR= +NV_WPR_WRITE_COMPLETE VF= ADDR= +NV_WPR_READ_COMPLETE VF= ADDR= +NV_WPR_WRITE_TIMEOUT VF= ADDR= +NV_WPR_READ_TIMEOUT VF= ADDR= +``` + +### Trace Points +```c +// In kernel driver +trace_gsp_wpr_protect(vf_id, base, size, type); +trace_gsp_wpr_event(vf_id, event_type, address, status); +trace_gsp_wpr_timeout(vf_id, address, elapsed_ns); +``` + +--- + +## Reference +- Handler 1: `FUN_ram_04f00b0c_ram_04f00b0c.c` (62 KB) +- Handler 2: `FUN_ram_04f00c78_ram_04f00c78.c` (62 KB) +- RPC Types: Handled via primary/secondary dispatchers \ No newline at end of file diff --git a/wiki/open-iov.org/api.php?action=rsd b/wiki/open-iov.org/api.php?action=rsd new file mode 100644 index 0000000..bdc15ca --- /dev/null +++ b/wiki/open-iov.org/api.php?action=rsd @@ -0,0 +1 @@ +https://www.mediawiki.org/wiki/Special:MyLanguage/APIfalseMediaWikihttps://www.mediawiki.org/https://open-iov.org/index.php/Main_Page \ No newline at end of file diff --git a/wiki/open-iov.org/favicon.ico.html b/wiki/open-iov.org/favicon.ico.html new file mode 100644 index 0000000..cd96554 --- /dev/null +++ b/wiki/open-iov.org/favicon.ico.html @@ -0,0 +1,245 @@ + + + + +Open-IOV + + + + + + + + + + + +
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AMDGPU

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The AMDGPU driver is AMD's open source GPU driver which comes included with the Linux kernel.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

This software's source code can be viewed here. +


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This Open-IOV page should aim to provide similar insights about APIs exposed to Linux developers to those documented on the OpenRM Driver API page. +


+This page may provide some of the required information from which details immediately relevant to graphics mediation can be consolidated: +

https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html +

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If you're new to GPU Virtualization start by reading the Introduction article. +

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Introduction +

About Open-IOV (CC-BY-4.0) +

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Abstract

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VFIO - vfio.h - mdev.h +

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Sample Code

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GPLv2 sources mirrored from elixir.bootlin.com with simple makefile changes. +

mtty.c - mdpy.c - mdpy-fb.c - mdpy-defs.h - mbochs.c +

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PCI passthrough via OVMF +

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Hypervisor From Scratch +

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Data Plane Development Kit: IVSHMEM Programming Guide +

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CPU Support

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In order to use mediated device functionality you may need to set some or all of the following settings in your machine's UEFI.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

UEFI Setup

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Intel CPUs (VT-d)

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Optimal UEFI Settings +

IOMMU >> Enabled +

SR-IOV Support >> Enabled +

VT-x >> Enabled +

ARI Mode >> Enabled +

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AMD CPUs (AMD-v)

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Optimal UEFI Settings +

SVM Mode >> Enabled +

SR-IOV Support >> Enabled +

ACS Enable >> Enabled +

IOMMU >> Enabled +

PCI AER Support >> Enabled +

ACS Enable >> Enabled +

ARI Mode >> Enabled +

Note to AMD CPU users: If you are using a first generation Ryzen or ThreadRipper platform you may need to update your motherboard UEFI to make proper use of IOMMU Groups. If your motherboard manufacturer has not made an update available you may need to apply an ACS override patch. Successive AMD CPU platforms are unaffected. +

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Application_Binary_Interface_(ABI).png ‎(800 × 600 pixels, file size: 146 KB, MIME type: image/png) +

Application Binary Interface (ABI) +

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File history

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File:Device Decomposure and Recomposure via VFIO.png

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Original file ‎(1,135 × 558 pixels, file size: 60 KB, MIME type: image/png) +

Device Decomposure and Recomposure via VFIO +

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Echoing a UUID into the sysfsdev API +

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Figure 0: Approches to GPU Virtualization. +

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Figure 0: i915 vGPU Scheduling +

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Figure 2: Firmware status information for an Intel DG2 device. +

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File:Figure 2- Intel vGPU Scheduler.png

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Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO +

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Figure 6: MMU - GMMU IOVA translation/isolation. +

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File:Figure 7- A depiction of region overlays within a VFIO file descriptor..png

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Figure 7: A depiction of region overlays within a VFIO file descriptor. +

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File:Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation..png

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Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. +

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I915 Scheduling Events and Requests +

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File:IOCTL set VFIO container.png

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Placing a VFIO binding into a VFIO Container. +

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IVSHMEM +

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"Accelerate up to 8 VMs plus DOM0." +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html b/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html new file mode 100644 index 0000000..72dfbda --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html @@ -0,0 +1,233 @@ + + + + +File:Intel i915 Host DRM + VFIO-Mdev..png - Open-IOV + + + + + + + + + + + +
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File:Intel i915 Host DRM + VFIO-Mdev..png

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Intel's i915 driver provides host and guest GPU acceleration via host DRM + VFIO-Mdev in the same driver. +

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File:Ioctl-VFIO GROUP GET FD.png

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Using an interrupt routine to obtain the VFIO Group file descriptor. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html new file mode 100644 index 0000000..ec1ed65 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html @@ -0,0 +1,233 @@ + + + + +File:Ioctl-VFIO IOMMU MAP-UNMAP DMA.png - Open-IOV + + + + + + + + + + + +
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File:Ioctl-VFIO IOMMU MAP-UNMAP DMA.png

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Using interrupts VFIO_IOMMU_MAP/UNMAP_DMA to pin/map regions of memory. +

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"A very simple" diagram of ioeventfd and irqfd. +

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File:KVMFR Looking Glass.png

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KVMFR Looking Glass +

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File:KVM services EPT violation and forwards to QEMU VFIO PCI driver..png

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KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

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Registering the mediated device. +

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File:Memory Regions Added by QEMU.png

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Memory Regions Added by QEMU +

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NUMA Node +

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File:QEMU calls VFIO DMA MAP via Memory listener.png

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QEMU calls VFIO DMA MAP via Memory listener +

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File:QEMU convert request from KVM to Read-Write acess to Mdev file descriptor..png

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QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. +

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File:QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor..png

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QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. +

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File:QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs.png

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QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs +

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File:QEMU presenting the VFIO file descriptor into the virtual machine..png

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QEMU presenting the VFIO file descriptor into the virtual machine. +

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SR-IOV-Diagram +

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Screen_Shot_2022-05-06_at_10.46.59_AM.png ‎(584 × 436 pixels, file size: 23 KB, MIME type: image/png) +

Peer-to-Peer DMA Isolation under IOMMU +

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Pictured: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. +

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An RDMA based proxy for the Looking Glass Memory Protocol. +

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Type 1 IOMMU Tracks VA-GFN +

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A VFIO diagram. +

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VFIO group nodes are unit of ownership that VFIO uses. +

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Virgl +

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GPU Driver Internals

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This page will detail the internals of various GPU drivers for use with I/O Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Article Structure

+

This article will aim to provide information about the following details of GPU drivers: +

+

High Level Architecture

+

This section will detail high level architectures of each driver. +

+

Initialization

+

This section will cover how the GPU's embedded components, the GPU driver, and virtualization functions are initialized. +

+

Scheduling

+

This section will detail how the device schedules instructions for execution. +

This will attempt to provide a comprehensive view of scheduling from virtualized processes down to execution within the device. +

+

In-VM Scheduling

+

The In-VM Scheduling section will detail how instructions scheduled within the virtual machine's GPU device driver. +

+

Between-VM Scheduling

+

The Between-VM Scheduling section will detail how the host kernel module and/or virtual GPU helper functions handle scheduling / context swaps between virtual machines on a computer system. +

+

Firmware Scheduling (if applicable)

+

The Firmware Scheduling section will cover the GPU's internal scheduling model if a deferred execution pathway is used (like i915's GuC or OpenRM's GSP). +

In the case an intermediate scheduling microcontroller is not used this section may be less applicable (ie: vExeclist scheduling under Intel vGPUs). +

+

Memory Management

+

The Memory Management section will cover how the GPU driver manages memory for virtual GPUs and host processes. +

This will aim detail paging abstractions used for global memory translation, and per-process memory translation. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will cover methods provided by the GPU driver suitable for high performance graphics sharing. +

+

Vendor Neutral

+

This section will detail functions in common between GPU drivers. +

Also see Display Virtualization for Windows OS. +

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Satyeshwar Singh. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will deal with graphics buffer sharing for vendor neutral GPUs. +

+
Display Flow in Linux
+

Userspace applications provide their buffers to compositor. +

Compositor asks Mesa to create a framebuffer. +

Framebuffer is allocated through vendor driver. +

Vendor driver flips the framebuffer on the screen. +

+
SR-IOV and Mdev
+

SR-IOV VFs don't have access to the display controller (only PF does). +

Known issue is displaying a VF's framebuffer on the screen. +

+
VFs in QEMU Hypervisor (VirtIO-GPU)
+

SR-IOV and Mdev VFs run in QEMU Hypervisor. +

QEMU has full access to all pages in VF's address space. +

VirtIO-GPU allows for allocating buffers (not API remoting in this case). +

Mesa's KMSRO allocates framebuffer via virtio-gpu. +

Mesa's KMSRO asks vendor driver to import framebuffer (no specific compositor dependancy). +

+
Transport
+

A Scatter Gather List (SGL) of physical pages is constructed by VirtIO-GPU of VF. +

+
QEMU Host-Side u-dma-buf
+

Host QEMU uses u-dma-buf driver to reconstruct a virtual memory pointer from the SGL shared by VF. +

u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers. +

+
QEMU Host-Side Modules
+

Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI. +

QEMU UI has several toolkits to support like GTK, SDL, etc. with GTK. being the default. +

GTK uses EGL and passes it the DMABUF as a texture. +

+
Windows VFs
+

Windows OS doesn't support DMABUF capability so we can't allocate buffers from VirtIO-GPU and share them with the Windows Kernel Mode Driver (KMD). +

Windows OS is different in the way that the FB is allocated via the OS rather than the miniport driver. +

Modified version of RedHat virtio-gpu-do (short for Display Only) driver used. +

+
Windows Driver Stack
+

OS (DWM) allocates frame buffers and asks GPU to write to them through Miniport. +

DVServer UMD (IDD) asks the OS for the FB copy. +

DVServer UMD (IDD) passes the virtual memory address to DVServer KMD. +

+
DVServer KMD
+

DVServer KMD finds the SGL (Scatter Gather List) of physical pages for this virtual memory address. +

This SGL is passed via virt-queue from the VF to the host QEMU. +

+
Android VFs
+

Android uses Linux kernel underneath. VirtIO-GPU is present in Android's kernel. +

KMSRO patch to allocate framebuffer via VirtIO-GPU also ported over to Android. +

Need modifications in the minigbm lib of Android to connect with KMSRO part. +

Rest of stack looks identical to Linux VF/PF. +

+

i915

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Zhi Wang, Ben Widawsky, and Igor Bogdanov. +

See references 2, 3, 4, 5, 6, 7, 8, and 9 in the References (Talks & Reading Material) section. +

+

High Level Architecture

+

i915 Clients

+

Processes which make use of the Intel i915 driver receive an i915 Client ID. +

+

Initialization

+

During initialization of the i915 driver the GuC binary blob is offloaded into the Graphics Translation Table (GTT). This allows the GuC to read GTT-loaded binary blob from shared framebuffer memory so that it may boot. +

+

Scheduling

+
Figure 0: i915 vGPU Scheduling
Figure 0: i915 vGPU high-level Scheduling. See slides from: [9]
+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (i915.ko)
    • +
  • Host kernel (i915.ko)
    • +
  • Device Firmware (GuC)
+
In-VM Scheduling
+
Guest kernel (i915.ko)
+
vExeclist
+

The vExeclist is a method to submit commands directly to the GPU without the use of an intermediate microcontroller. +

+
vGuC
+

vGuC is a command submission interface used to process commands to the Intel Graphics Microcontroller (GuC). +

+

Between-VM Scheduling

+
Figure 1: i915 vGPU Scheduling Requests & Events
Figure 1: i915 vGPU Scheduling Requests & Events. See slides from: [9]
+
Host kernel (i915.ko)
+

Submitting commands to the GPU under i915 can take several paths. One pathway makes use of direct command submission without an intermediate micro-controller whereas the other uses an intermediate micro-controller. The intermediate micro-controller approach increases the amount of binary-blob code used and abstracts the kernel module from the device's internal scheduling model. +

+
Execlist
+

Execlist executes commands synchronously on the device without an intermediate microcontroller. This is the preferred method of executing commands by some driver developers because of it's stability and transparency under current i915 development. +

+
GuC
+

GuC provides an execution pathway with an intermediate microcontroller providing a scheduling abstraction for Intel's preferred internal scheduling model. +

+
Figure 2: Intel vGPU Scheduler request flow.
Figure 2: i915 vGPU Scheduler request flow. See slides from: [9]
+
Device Firmware (GuC)
+

Memory Management

+
Translation Tables
+
GTT (Graphics Translation Table)
+

GPU Memory on-device is a part of a GTT or Graphics Translation Table. This table stores information globally for all graphics processes within the system. Some processes access the Global Graphics Translation Table (GGTT) such as DRI while other's receive a Per Process Graphics Translation Table (PPGTT) buffer based on their i915 Client ID. +

+
GGTT (Global Graphics Translation Table)
+
PPGTT (Per Process Graphics Translation Table)
+

Process-specific memory buffers are stored inside a Per Process Graphics Translation Table or PPGTT. This is a GPU MMU translated subregion or IOVA of global GPU memory specific to a GPU process's client ID. +

+
Aliasing PPGTT
+

Aliasing PPGTT (Per Process Graphics Translation Table) refers to partially separated GPU resources (process context). +

+
Real PPGTT
+

Real PPGTT (Per Process Graphics Translation Table) refers to fully separated GPU resources (process context). +

+

Display Surface Virtualization

+

The Intel vGPU makes use of two modes for Display Surface Virtualization. +

+
  • VirtIO-GPU (Linux)
    • +
  • Indirect Display Driver (Windows)
+

VirtIO-GPU

+

IDD (Indirect Display Driver)

+

The IDD (Indirect Display Driver) provides virtual display functions with arbitrary resolutions to any rendering device virtual or physical. +

Intel's IDD can be found in their Display Virtualization for Windows OS repository. +

+

Graphics Buffer Sharing

+

Intel's i915 driver provides functionality to directly map display memory from a guest vGPU Virtual Function (either SR-IOV or VFIO-Mdev) into the host GPU's Physical Function without slow memory copies or graphics compression. For users running GPU virtualization on their local device this results in a significant performance uplift compared to traditional graphics sharing functionality built for remote access use-cases such as VDI. +

Intel's 0copy display virtualization tools are simple to implement as sharing does not rely upon an added IVSHMEM (Inter-VM Shared Memory device) - rather the host directly maps the guest's display memory via udmabuf as the buffer sharing functions are provided within the i915 open source driver. +

+

OpenRM

+
Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO
Figure 3: GPU BAR to Timeshared Scheduling via Channel IO.
+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Andy Currid, Neo Jia, John Fanelli, and Neha Joshi. +

+

High Level Architecture

+

The Open Resource Manager (RM driver) makes use of a highly object oriented paradigm comprised of multiple "engines" which act as micro-services for servicing driver requests. +

The Open Resource Manager driver (also known as OpenRM) refers to Nvidia's open-kernel-modules. +

Broadly speaking the OpenRM driver consists of two parts. +

+
  • The Platform RM (OpenRM)
    • +
  • The Firmware RM (GSP RM / RM Core)
+

The Platform RM is loaded into the Linux Kernel as nvidia.ko. This module communicates with the GSP RM for via Remote Procedure Calls (RPCs) to communicate with engines from the RM Core. +

+
RM Clients
+

Processes (local, remote, or virtualized) which make use of the RM driver receive an RM Client ID. +

+

RM Server

+

The RM Server (or Resource Server) tracks RM Clients as well as the hardware and software resources they control, allocate, and free. +

+

RM API

+

API to control the Resource Manager Server. +

+

RM Core

+

Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors. Under OpenRM the RM Core runs within the GPU System Processor (GSP micro-controller) while in pre-open source versions of the Resource Manager the RM Core ran within the nvidia.ko kernel module +

+

Initialization

+

During bring up of the hardware several binary blobs are loaded from embedded Boot ROM memory to bootstrap embedded controller bring up from which point additional software is loaded from onboard SPI flash memory. +

Software loaded from SPI flash is necessary for the full initialization of the Falcon/NvRISC processor as well as a cached version of the software necessary to run the GPU System Processor (GSP). +

Once the platform is posted it is ready to communicate with the host platform's RM driver. The OpenRM driver offloads a binary blob containing the RM Core to the GPU System Processor (GSP) which is likely to contain a more recent version than the cached version contained in on-board SPI flash. +

+

Scheduling

+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (nvidia.ko)
    • +
  • Host kernel (nvidia.ko)
    • +
  • Host usermode (gpu-mgr / libnvidiavgpu.so)
    • +
  • Device Firmware (GSP)
+

Command Submission

+
Runlist
+

In-VM Scheduling

+

Virtual machines contain their own GPU scheduling within the Nvidia kernel module in the guest OS. +

+
Guest kernel (nvidia.ko)
+

Within a virtual machine running the Nvidia driver messages to the GPU are first sent to the guest nvidia.ko kernel module. +

+The guest then determines whether a vRPC (virtual Remote Procedure Call) or a pRPC (physical Remote Procedure Call) should be sent. Both pRPCs and vRPCs are sent through the host RM driver (Resource Manager).

Note: Unclear on execution pathway for pRPCs vs vRPCs. pRPCs may go directly to device.

+

Between-VM Scheduling

+

In addition to scheduling which occurs within the virtual machine the Resource Manager driver also schedules messages to the GPU between GPU-accelerated virtual machines and host processes. +

+
Host kernel (nvidia.ko)
+

Messages sent by the guest (via vRPC or pRPC) are received by the host Nvidia.ko driver. +

Nvidia.ko contains a virtual GPU state machine which contains status information for the virtual GPU. +

Nvidia.ko also contains a virtual GPU kernel scheduler which interacts with virtual GPU objects. +

Nvidia.ko also contains an RM Call scheduler which schedules calls on an RM class. +

The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin). +

+
Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)
+

After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and it's library libnvidia-vgpu.so) are executed to schedule VM-exits described below. +

+
nvidia-vgpu-mgr
+

The nvidia-vgpu-mgr is a process which provides the spawning of virtual GPU stubs and population with capability information. +

This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components. +

This process and the libnvidia-vgpu.so contain, and execute the VMIOP. +

This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the RM Core. +

+
vmiop
+

VMIOP (Virtual Machine Input Output Plugin) handles presenting virtualized functionality into the guest. +

The Virtual Machine Input Output Plugin software handles virtual displays, compute API offload, and most importantly BAR (Base Address Register) quirks. +

The VMIOP is an SDK (Software Development Kit) provided in binary format split between the libnvidiavgpu.so and nvidia-vgpu-mgr which provides userland helper functions for GPU virtualization. +

Messages to the VMIOP are scheduled by Linux kernel niceness (scheduling abstraction). +

+
Device Firmware (GSP)
+

Messages received by the host RM driver (Resource Manager) are then scheduled by the RM Core contained within the GSP (GPU System Processor). The GSP handles the device's internal scheduling model. +

+

Memory Management

+

Managing virtual machine memory is very important to the security of virtualization. +

This section will cover the method by which secure memory "enclaves" or IO Virtual Addresses (IOVAs) may be provisioned and separation enforced by hardware constructs within the GPU. +

+
Programming the MMU
+

In order to hardware enforce separation between memory allocated to Virtual Machines (VMs) virtualization software must program the GPU's MMU (GMMU controller) to create IO Virtual Addresses (IOVAs). +

In order to create such configurations several abstractions are used to translate high level representations of virtualization programmed via the vmiop and gpu-mgr into practical, architecture specific instructions. +

+
AMAPLibrary
+

The AMAPLibrary acts as a device abstraction framework for GPU driver software to program using high level representations of MMU configuration. +

The AMAPLibrary translates high level representations of GPU virtualization into graphics architecture-specific logic contained within architecture HALs (Hardware Abstraction Layers). +

+
Architecture HALs
+

GPU Hardware Abstraction Layers (HALs) contain logic specific to graphics architectures, for instance the precise method by which the GPU driver may interact with the Falcon to provision MMU protected memory. +

+
DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)
+

The Falcon (FAst Logic CONtroller) / NvRISC-V embedded controller emits DMAs to the Frame Buffer Interface (FBIF) in order to interact with the device's GMMU controller. +

User programs and VMs have their memory translated through the GMMU. +

Once created memory translations within a virtual machine's IO Virtual Address (IOVA) will be protected by the device's GMMU controller. +

+
Translation Tables
+
vmiop_gva
+

Display Surface Virtualization

+

amdgpu

+

References (Talks & Reading Material)

+
  1. Intel Graphics Programmer's Reference Manuals (PRM)
    2. +
  2. i915: Hardware Contexts (and some bits about batchbuffers)
    3. +
  3. i915: The Global GTT Part 1
    4. +
  4. i915: Aliasing PPGTT Part 2
    5. +
  5. i915: True PPGTT Part 3
    6. +
  6. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    7. +
  7. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    8. +
  8. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    9. +
  9. i915: An Introduction to Intel GVT-g (with new architecture)
    10. +
  10. lwn.net: Add udmabuf misc device
    11. +
  11. Nvidia RISC-v Story
    12. +
  12. IOMMU Introduction
    13. +
  13. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    14. +
  14. nVidia GPU Introduction (envytools)
    15. +
  15. Delivering High Performance Remote Graphics With Nvidia GRID Virtual GPU
    16. +
  16. NVIDIA Multi-Instance GPU
    17. +
  17. i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]
    18. +
  18. Lifecycle of a Triangle - Nvidia's logical pipeline
    19. +
  19. Nvidia Parallel Thread Execution (PTX)
    20. +
  20. i915/GEM Crashcourse
    21. +
  21. drm: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
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GPU Firmware

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GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel

+

Firmware Images

+This section will cover firmware images used in Intel GPUs.

Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.
Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. Source
+

Intel Firmware Support Package (FSP)

+

Much like CPUs Intel's GPUs also contain a Firmware Support Package (FSP). +

The Coreboot project provides public domain information on the FSP here. +

+
FSP Configuration
+

In the context of GPUs the FSP configures several functions of the device. +

Those functions are as follows: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
GPU Firmware Support Package +
FSP Parameter +Possible Values +
GFSP Status +0x00 +
FIVR SSC Value +*.*% +
FIVR RFI Value +*.*MHz +
GT Subsystem Vendor ID +0x8086 +
GT Subsystem Device ID +0x** +
HDA Subsystem Vendor ID +0x0000 +
HDA Subsystem Device ID +0x0000 +
P2SB Enable +Yes/No +
LMEBAR +Max +
GTMMADDR Prefetch Capability +Prefetch Enabled +
Display Present +Enabled/Disabled +
I2C For Third Party Devices +Enabled/Disabled +
I2C Device Address 1 +0x0000 +
I2C Device Address 2 +0x0000 +
I2C Bus Speed +Standard mode (0 to 100Kbps) +
+
Editing FSP Configuration
+

The FSP configuration editor can be downloaded here and it's user manual is available here. +

+
FSP Binary Format
+

The FSP's binary layout is detailed within the Intel® FSP External Architecture Specification v2.4 on page 14. +

+

Known Firmware Package Variations

+

Some firmware packages may include an **End of Manufacturing Flash Protection Mode** status of Protected or Unprotected. +

+
Figure 2: Firmware status information for an Intel DG2 device.
Figure 2: Firmware status information for an Intel DG2 device.
+

Similar SPI Write Protection functionality is made available through Intel CPUs under System Management Mode (SMM). +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Intel GPU. +

+

GuC

+

The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs. +

+
Hardware Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The GuC - an embedded i486 core that supports graphics scheduling, power management and firmware attestation." +

+
Software Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services." +

"It runs a single process - which initializes the system and then waits for interrupts/events in a loop." +

+
GuC Blob Checksum & Code Signing
+

"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing." +

+

Nvidia

+

Firmware Images

+

This section will cover firmware images used in Nvidia GPUs. +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU. +

+

Falcon / NV-RISCV

+

The Fast Logic CONtroller (Falcon) and Nvidia RISC-V (NV-RISCV) processors run the NvOS. +

+

GSP

+

The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core. +

The GSP runs Library Operating System (LibOS). +

+
GSP Initialization & Offload
+

The GSP is initialized multiple times during the system's bring up and runtime. +

GSP offload may occur during: +

+
  • Hardware bring up when a cached version of the RM Core is loaded from SPI flash
+
  • During host driver bring up when the RM Core is offloaded by the OpenRM driver.
    • +
  • During guest driver bring up when the RM Core is offloaded.
+ + + + + + + + + + + + + + + + + +
Possible GSP Offloads +
Load Source +Payload +Notes +
SPI Flash +Cached RM Core +Used as a fallback in case of no rm offload. +
OpenRM +RM Core +This is the RM Core which was traditionally contained in the proprietary RM driver. +
VGX Guest +Guest RM Core +Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via gspHeapSize?). +
+

CMU

+

AMD

+

References (Talks & Reading Material)

+
  1. Security of the Intel Graphics Stack - Part 1 - Introduction
    2. +
  2. Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    3. +
  3. Firmware Security Realizations Part 3: SPI Write Protections
    4. +
  4. Intel® FSP: Firmware Solutions for the Internet of Things
+ + + + +
+
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GPU Software Bill Of Materials (SBOM)

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From Open-IOV
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This page will keep a running list of components used to achieve GPU Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Component Table +
Vendor +Component +Description +Version +OSS or Blob +Filesize +Vendor Docs +Release Date +Interfaces / APIs +Notes +
Microsoft +Indirect Display Driver (IDD) +Driver + +OSS + +Indirect Display Driver Overview + +UMDF, KMDF +The Indirect Display Driver (IDD) enables GPUs to render graphics at arbitrary resolutions without a physical display connected on Windows OS systems. +
RedHat +vfio_pci +Driver +6.2-rc1 +OSS +in-kernel +RedHat, kernel.org +2022.12.15 +irqfd, ioeventfd, IOCTL +Reference VFIO Stub driver used for discrete assignment of IO, and assignment of some SR-IOV-backed vGPU devices into virtual machines. This driver is commonly replaced with a vendor built VFIO interface with differing memory management and/or page pinning mechanisms which are specific to the vGPU software internals. +
Mediated Core (mdev.ko) +Driver +6.2-rc1 +OSS +0.044 MB +kernel.org +2016.xx.xx +irqfd, ioeventfd, IOCTL, Type 1 IOMMU +The Mediated Core driver provides a common interface for mediated device management that can be used by drivers of different devices. It is an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment (based on VFIO). +
+guest communication daemon +Daemon +0.1.0 +OSS + + +2023.02.08 +Virtio-Serial, CLI +Handles IO to and from guests and the host using Virtio-Serial to handle multiple different guest modules. +
mdev management CLI +1.0 +OSS +0.084 MB + +2023.01.06 +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
Intel +i915 SR-IOV +Driver +5.15 +OSS +in-kernel + + + +Intel's open source GPU driver for GuC-equipped graphics accelerators. +
GuC μOS +Firmware +Blob + + + +IOMMU Interrupts, Power Management Interrupts, GTT +Handles scheduling, and power management. +
HuC + + + +GTT +Handles video encoding/decoding. +
Display Virtualization for Windows OS +Driver +791 +OSS + +github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt + +udmabuf, UMDF, KMDF +Intel's 'Display Virtualization for Windows OS' provides a virtual pixel surface used for hardware graphics rendering using Microsoft's open source 'Indirect Display Driver (IDD)'. Display virtualization for Windows OS makes use of display memory sharing primitives provided in-driver by the i915 host. +
Nvidia +OpenRM +Driver +525.85.12 +OSS + +github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md +2023.01.31 + +Nvidia's open source GPU driver for GSP-equipped graphics accelerators. +
GSP RM (uproc) +Firmware +Blob + + +2023.01.31 +RPC +Embedded firmware based on LibOS containing the RM Core. +
Falcon/NvRISC (uproc) + + + + +FBIF (Frame Buffer Interface) / GMMU +Embedded firmware which handles many aspects of the device including configuring the GPU's GMMU controller. +
nvidia-vgpud +Daemon +v15.2 +Blob +0.108 MB +docs.nvidia.com/grid +2023.01.xx +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
nvidia-vgpu-mgr +0.132 MB +2023.01.xx +vmiop, IOCTL, RMAPI, vRPC, pRPC, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. +
libnvidia-vgpu.so +Library +3.1 MB +2023.01.xx +vmiop, RMAPI, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. Contains circular dependancies with nvidia-vgpu-mgr. +
nvidia-vgpu-vfio.ko +Driver +0.108 MB +2023.01.xx +Type 1 IOMMU, irqfd, ioeventfd, IOCTL, Mediated Core +Handles incremental memory mapping (non-page pinning per the standard vfio-pci driver). +
+

More Information

+
  1. Nvidia RISC-V Story
    2. +
    3. +
  3. Intel Graphics Programmer's Reference Manuals (PRM)
    4. +
  4. i915: Hardware Contexts (and some bits about batchbuffers)
    5. +
  5. i915: The Global GTT Part 1
    6. +
  6. i915: Aliasing PPGTT Part 2
    7. +
  7. i915: True PPGTT Part 3
    8. +
  8. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    9. +
  9. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    10. +
  10. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    11. +
  11. i915: An Introduction to Intel GVT-g (with new architecture)
+ + + + +
+
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GPU Support

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+ +

Abstract

+The following document will detail GPU Support for SR-IOV, SIOV, and VFIO-Mdev functionality.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

Overview

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Feature Matrix +
Hardware +Drivers +Virtual I/O Assistance Modes +Userspace +
Vendor +Architecture +Model +Libre Drivers +Blob Drivers +'Merged' Host+Guest Acceleration +Manufacturer Support +Mdev Support +SR-IOV Support +SIOV Support +mdev management CLI Support + Support +
Intel +6th Generation (Skylake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +7th Generation (Kaby Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +8th Generation (Coffee Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +9th Generation (Cannon Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +10th Generation (Ice Lake) + +i915 + +No +Yes (Legacy) +No +No +No +No +No +
Intel +11th Generation (Tiger Lake) +Xe* +i915 + +Yes +Yes + +Yes + +Yes +Yes +
Intel +12th Generation (Alder Lake) +Xe* +i915 + +Yes +Yes + +Yes +In Development +Yes +Yes +
Nvidia +Maxell +*(see exceptions below) +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Pascal +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Turing +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Ampere +A* +Nouveau (Development), OpenRM +RM +No (DisplayModeSelector) +Yes +Yes +Yes +In Development +Yes +Yes +
Nvidia +Ampere +RTX 30** +Nouveau (Development), OpenRM +RM +In Development +Yes +Yes +No +In Development +In Development +In Development +
Nvidia +Ada Lovelace +* +OpenRM + + +Yes +Yes +Yes +In Development +In Development +In Development +
Nvidia +Hopper +* +OpenRM + + +Yes +Yes +Yes +In Development + + +
AMD +Tonga +W7100 +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +

(patched) +

+		No +No +Yes +
AMD +Tonga +S71** +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +No +No +Yes +
AMD +Vega +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
AMD +Navi +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
+

Intel

+

This section will cover Mdev support on Intel GPUs. +

+

Hardware

+

GPUs supporting GVT-g (software based mediation)[1]: +

+
  • Intel HD Graphics 5500
    • +
  • Intel HD Graphics 6000
    • +
  • Intel HD Graphics 510
    • +
  • Intel HD Graphics 520
    • +
  • Intel HD Graphics 530
    • +
  • Intel HD Graphics 620
    • +
  • Intel HD Graphics 630
    • +
  • Intel UHD Graphics 620
    • +
  • Intel UHD Graphics 630
+

GPUs supporting SR-IOV (hardware based mediation): +

+
  • Intel Iris Xe Graphics [2][3]
    • +
  • Intel Iris Xe MAX Graphics
+

Drivers

+

Drivers with GVT-g support (6th - 9th gen): +

+ +

Drivers with SR-IOV support (11th gen+): +

+ +

Nvidia

+

This section will cover Mdev support on Nvidia GPUs. +

+

Hardware

+
  • All(?) Volta based GPUs (V-series)
    • +
  • All(?) Turing based GPUs (20-series)
    • +
  • All(?) Pascal based GPUs (10-series)
    • +
  • Most Maxwell based GPUs (9-series) with the following notable exceptions: +
    • GTX 970 (mixed FB regions)
      • +
    • Quadro M2000 (mixed FB regions)
      • +
    • Tesla M40 [4]
+
  • NVIDIA A100 HGX 80GB
    • +
  • NVIDIA A100 PCIe 80GB (SR-IOV: 20VF [5])
    • +
  • NVIDIA A100X
    • +
  • NVIDIA A100 HGX 40GB
    • +
  • NVIDIA A100 PCIe 40GB (SR-IOV: 16VF [6])
    • +
  • NVIDIA A40 (SR-IOV: 32VF [7])
    • +
  • NVIDIA A30 (SR-IOV: 8VF [8])
    • +
  • NVIDIA A30X
    • +
  • NVIDIA A16 (SR-IOV: 16VF [9])
    • +
  • NVIDIA A10 (SR-IOV: 32VF [10])
    • +
  • NVIDIA A2 (SR-IOV: 16VF [11])
    • +
  • NVIDIA RTX A6000
    • +
  • NVIDIA RTX A5000
    • +
  • Quadro RTX 8000 (SR-IOV: 24 VF [12])
    • +
  • Quadro RTX 8000 passive
    • +
  • Quadro RTX 6000 (SR-IOV: 24 VF [13])
    • +
  • Quadro RTX 6000 passive
    • +
  • Tesla V100
    • +
  • Tesla T4 (SR-IOV: 16VF [14])
    • +
  • Tesla P100
    • +
  • Tesla P40
    • +
  • Tesla P6
    • +
  • Tesla P4
    • +
  • Tesla M60
    • +
  • Tesla M10
    • +
  • Tesla M6
    • +
  • GRID K2 (Citrix XenServer and VMware ESXi only)
    • +
  • GRID K1 (Citrix XenServer and VMware ESXi only)
+

Drivers

+

The most widely used method of enabling Mdev functionality on Nvidia GPUs is via the use of Nvidia's proprietary driver package. +

Nvidia's proprietary Mdev driver supports both SR-IOV as well as software based mediation. The appropriate mode is chosen between the two methods based on hardware architecture. +

+

AMD

+

This section will cover Mdev support on AMD GPUs. +

+

Hardware

+

Supported GPUs: +

+
  • AMD FirePro S7150
    • +
  • AMD Radeon Pro V520 [15]
    • +
  • AMD FirePro W7100 [15]
+

Drivers

+

The open source GIM driver supports AMD Tonga architecture GPUs such as the FirePro S7150 & W7100. +

To make use of the MxGPU GIM driver on modern kernel versions you will require pull request 24. +

Virtualization driver support beyond AMD's Tonga architecture is unclear. +

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Glossary

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From Open-IOV
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Definitions

+

This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +

If you have suggestions on how to improve the glossary you can contribute or join our community discussion thread to make suggestions. +

+

VFIO

+

Kernel.org defines VFIO or Virtual Function Input Output as "an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." [1]

+
A diagram depicting direct VFIO passthrough of a GPU adapter.
+

Mdev

+

Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: "an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." [2]

+
A diagram depicting VFIO Mediated Device interacting with two vGPU guests.
+

Virtual CPU (vCPU)

+

A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.

+

Virtual GPU (vGPU)

+

A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to EUs, or SMs) and/or a partition of the device's Video Random Access Memory (VRAM).

+

IVSHMEM

+

According to QEMU's GitHub repo: "The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR." [3]

+
A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.
+

KVMFR (Looking Glass)

+

looking-glass.io defines Looking Glass as: "an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse." [4]

+
A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.
+

NUMA Node

+

Infogalactic defines NUMA as: "Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." [5]

+
A diagram depicting Non-Uniform Memory Access (NUMA) nodes.
+

Application Binary Interface (ABI)

+

Infogalactic defines an ABI as "the interface between two program modules, one of which is often a library or operating system, at the level of machine code." [6]

+
A diagram contrasting API and ABI as well as their respective roles in software compatibility.
+

SR-IOV

+

docs.microsoft.com defines SR-IOV as "The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." [7]

+
A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.
+

GVT-g

+

wiki.archlinux.org defines Intel GVT-g as "a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." [8]

+
A diagram of Intel's GVT-g (Graphics Virtualization Technology g).
+

VirGL

+
A diagram depicting GPU instruction redirects to a single host graphics driver.

lwn.net defines Virgl as: "a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host." [9]

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Platform Hypervisor +Virtual GPU support +Memory Sharing APIs +IOMMU Groups support +PCI forwarding +Mdev Support +SR-IOV Support +SIOV Support +
KVM +Yes +IVSHMEM +Yes +Yes (via VFIO) +Yes +Yes +In Development +
Xen +Yes +Grant Tables +No +Yes (via xen-pciback) +No +Yes +Unknown +
NVMM +Unknown +Unknown +No +Unknown +No +Unknown +No +
+ + +

KVM

+

This section will cover existing support in KVM for VFIO-Mdev and ongoing issues with it's existing implementation. +

+

Missing Functionality

+

Nested SR-IOV. +

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Xen

+

This section will cover efforts to support the Xen hypervisor with open device mediation software. +

XAPI docs for virtual GPUs can be read here. +

+

Mdev drivers outside Dom0

+

Xen Hyperlaunch aims to disaggregate Dom0's monolithic functions. This includes a discrete domain for device drivers. +

+

Missing Functionality

+

IOMMU Groups (discussions around extending or reworking Xen's IOMMU to include IOMMU Groups is ongoing). +

+

Additional Documentation

+

For additional documentation check the XenProject Wiki. +

+

NVMM

+

This section will cover NetBSD's NVMM. +

+

Missing Functionality

+

VFIO. +

+

Additional Documentation

+

For additional documentation read From Zero to NVMM. +

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Intel

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This page will document points of integration for virtualization in the Intel i915 driver. +

The i915 added SR-IOV feature enablement in this commit (April 26th 2022). Work is ongoing to upstream this code to i915 in the mainline Linux kernel. +

Driver API documentation can be read here: https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html +

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Intel

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This page will document points of integration for virtualization in the Intel i915 driver. +

The i915 added SR-IOV feature enablement in this commit (April 26th 2022). Work is ongoing to upstream this code to i915 in the mainline Linux kernel. +

Driver API documentation can be read here: https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html +

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Introduction

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This page will provide introductory context on where to begin reading. It will aim to give you a sense of primitives or foundational concepts used for GPU Virtualization. +

+ + +

Terminology

+

To get started with basic terminology around IO Virtualization read the Glossary page. This will get you familiar with a few terms and concepts used in IO Virtualization documentation. +

+

Primitives

+

The primitives section will cover a few notes on the basics of virtualizing a GPU or IO device. +

+

PCI BAR

+

PCI-e devices such as GPUs are used for input and output to and from a computer system. This input and output occurs using TLPs or Transaction Layer Packets over the PCI-e packet network. The IO device is presented to the host operating system as BARs or Base Address Registers. +

+

GPU Drivers

+

GPUs need software to communicate from a host computer system to the device - this software is called a GPU Driver and it typically interacts with the device using MMIO or Memory Mapped IO. MMIO is a set of operations used to allow normal CPU instructions to address registers in RAM in order to communicate with the PCI-e device. In the context of virtualization these registers must be presented into the device in a way that the guest operating system expects. Typically this is accomplished using VFIO or Virtual Function IO. VFIO is used for many methods of virtualizing the device including discrete assignment of a physical device, or virtual (partitioned) device assignment created with or without hardware assistance. +

+

IOMMU

+

MMU or Memory Management Units handle hardware enforced access to memory paging in computer systems. In the context of virtualized MMIO (Memory Mapped Input Output) devices an MMU is required to hardware enforce access to virtual devices (a Memory Management Unit for Input Output is known as an IOMMU). In the case of VFIO, groups of IOMMU devices (IOMMU Groups) are used to control access to the device. These IOMMU Groups often represent individual devices or sub-devices (in the context of Unassisted Virtualization (VFIO-Mdev), Hardware-Assisted Virtualization (SR-IOV), or Hardware-Assisted Paravirtualization) which may be bound to a VFIO bus driver (such as vfio-pci) which results in a VFIO Group (unit of ownership). +

+

Virtualization vs. Paravirtualization

+

Virtualization provides support for unmodified guest software or drivers in the context of GPUs. +

Paravirtualization provides support for "enlightened" guests or modified software which is aware of virtualization. +

+

Unassisted vs. Assisted

+

Similar to virtualization on CPUs with tools like Xen, IO devices can be virtualized on different kinds of computer hardware. Some devices provide hardware virtualization assistance (such as HVM mode in Xen) and some do not (such as PV mode in Xen), as a result an appropriate mode should be used depending on the availability of assistance. +

+

Further Reading

+

This section will cover what you should read to obtain more information about virtualization. +

+

Virtualization Fundamentals

+

The Virtualization Fundamentals article provides links to some of the foundational work which underly modern virtualization industry and development today. If you'd like to understand both the theories on which virtualization builds as well as the history of industry you should read several articles here. Notable Popek and Goldberg Virtualization Requirements as well as Xen and the Art of Virtualization provide a great foundations-first approach to learning about virtualization. +

+

Virtual I/O Internals

+

The Virtual I/O Internals article provides a detailed look into the interface layers between IO driver internals, the hypervisor, and the guest OS. This is a great article to read if you'd like to better understand how virtual machines can interact with both discretely assigned devices as well as those which have been partitioned using software or firmware. +

+

GPU Driver Internals

+

The GPU Driver Internals article provides information on how GPU drivers are structured internally as well as how they achieve virtualization. This includes high level architecture, device initialization, as well as memory mapping, and scheduling. +

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Glossary

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From Open-IOV
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Definitions

+

This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +

If you have suggestions on how to improve the glossary you can contribute or join our community discussion thread to make suggestions. +

+

VFIO

+

Kernel.org defines VFIO or Virtual Function Input Output as "an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." [1]

+
A diagram depicting direct VFIO passthrough of a GPU adapter.
+

Mdev

+

Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: "an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." [2]

+
A diagram depicting VFIO Mediated Device interacting with two vGPU guests.
+

Virtual CPU (vCPU)

+

A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.

+

Virtual GPU (vGPU)

+

A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to EUs, or SMs) and/or a partition of the device's Video Random Access Memory (VRAM).

+

IVSHMEM

+

According to QEMU's GitHub repo: "The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR." [3]

+
A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.
+

KVMFR (Looking Glass)

+

looking-glass.io defines Looking Glass as: "an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse." [4]

+
A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.
+

NUMA Node

+

Infogalactic defines NUMA as: "Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." [5]

+
A diagram depicting Non-Uniform Memory Access (NUMA) nodes.
+

Application Binary Interface (ABI)

+

Infogalactic defines an ABI as "the interface between two program modules, one of which is often a library or operating system, at the level of machine code." [6]

+
A diagram contrasting API and ABI as well as their respective roles in software compatibility.
+

SR-IOV

+

docs.microsoft.com defines SR-IOV as "The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." [7]

+
A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.
+

GVT-g

+

wiki.archlinux.org defines Intel GVT-g as "a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." [8]

+
A diagram of Intel's GVT-g (Graphics Virtualization Technology g).
+

VirGL

+
A diagram depicting GPU instruction redirects to a single host graphics driver.

lwn.net defines Virgl as: "a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host." [9]

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LIME Is Mediated Emulation

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LIME Is Mediated Emulation is an in-development feature in which enables the execution of full performance Win64 binaries with full compatibility for all current and future software making use of the Windows ABI. An initial demo of this technology can be viewed here. +

+ + +

Design Goals

+

LIME aims to provide similar functionality to WINE Is Not Emulation, Valve's Proton / DXVK but with the use of graphics virtualization (vGPU/SR-IOV on consumer GPUs), a shared filesystem between host/guest, and KVM Frame Relay (high performance graphics buffer sharing via Inter-VM Shared Memory Device / IVSHMEM). +

Compared to WINE, and Proton the benefits of this approach are that Win64 binaries execute without the incompatibilities introduced in new games taking advantage of the latest version of DirectX, or when changes are introduced to the latest version of the Win64 ABI. +

This functionality is enabled via the use of GPU Virtual Machine (for consumer GPU Virtualization), VirtIO-FS (for host <-> guest filesystem sharing), Looking Glass (for host <-> guest shared frame buffer), and (for orchestration). +

+

Use-Cases

+

Win64 Subsystem

+

LIME's most immediate use case is around ABI compatibility with Win64 programs in environments without native support. +

A blog post detailing the problems which lead to this work can be read here. A summary of this post is traditional models for backwards compatibility with Application Binary Interfaces (ABIs) lock-in existing models for kernel/userland development and stagnate architectural innovation. On the other hand consumer oriented systems like those based on Darwin/XNU break backwards compatibility with user programs version to version of the system in order to introduce architectural improvements in the kernel / userland (for instance micro-service device drivers which may recover from faults at OS runtime). +

These two approaches might be considered two discretely separable models for software development 'enterprise' /'consumer' - LIME might then be considered a third approach which preserves the functions of both prior approaches (continual innovation afforded in the kernel-space and backwards compatibility with existing software libraries). +

ie: A method by which programs "import" a particular explicitly versioned ABI similar to how Docker provisions chroot resources like configuration files and support libraries, but extended to drivers, and the kernel. +

+

Win64 Orchestration

+

Because LIME necessarily provisions application data, program files, and NUMA-aware vCPU/vGPU resources (in the context of multi-GPU, multi-socket CPU systems) through for automatic execution by one or more VM guests LIME might provide an ideal architecture for orchestration of Win64 applications at scale. This could include execution of programs for game streaming in a server environment, or multiple applications in a single user environment for 'seamless-mode' execution of guest programs similar to that of QubesOS with hardware GPU acceleration added. +

+

Compatibility With Other ABIs

+

To solve the problems of 'ABI lock-in' discussed in the "Why Computers Suck" post it may be possible to port LIME support to multiple different guest operating systems allowing execution of any program with any ABI with near indistinguishable performance compared to native execution. +

+

Quality of Service (QoS)

+

VFIO-Mdev functionality like that used in GPU Virtual Machine (GVM) provides granular GPU resource allocation and load balancing functions similar to those seen in control groups (cgroups) as they are commonly applied today to RAM and CPU resources. In the context LIME VFIO-Mdev could be applied for load balancing of individual processes running in a virtualized state to ensure individual processes making use of the GPU cannot deny service to others on the system. +

+

Development Status

+

Development of this functionality is ongoing. Efforts to improve LIME are primarily focused on stabilization of shared filesystem functions. +

+

VirtIO-FS

+

VirtIO-FS provides shared filesystem functionality between host and guest using FUSE which is ideal for LIME, however in the context of Windows guests the C version of virtiofsd appears unstable (seen in virtio-win issue 550 [closed], 723 [closed], 724 [open]). Testing has been performed by members of the Open-IOV community which have shown initial signs of increased filesystem stability under continuous read/write loads using the Rust version of virtiofsd (virtiofsd-rs). +

While many programs can be stored in the VirtIO-FS shared directory some programs such as Steam don't want to install programs into the VirtIO-FS drive (seen as a secondary drive in Windows - in often as disk D:/ if no additional media is attached). This game installation behaviour (which drive the user may place their programs in) may not be in common with other game stores such as the Epic Games Store, or Good Old Games (GOG). +

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Looking Glass KVMFR

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Looking Glass is an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse. +

+

Looking Glass Memory Protocol (LGMP)

+

LGMP is an Inter-VM Shared Memory Device (IVHSMEM) based memory sharing protocol for the KVM Frame Relay use-case (sharing of MMIO memory for use by GPU drivers between host and guest). +

+

Xen Support

+

It may be possible to port the Looking Glass Memory Protocol to Xen by substituting the use of the Grant Table memory sharing primitive in place of the IVSHMEM memory sharing primitive. +

+
A diagram depicting how Looking Glass memory device may be redirected over the network via Remote Direct Memory Access (RDMA).
+

Telescope

+

The LGMP protocol may also be extended over a high bandwidth network using the Telescope Looking Glass Proxy. +

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Mdev-GPU

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This page makes use of terms that are defined in the Open-IOV Glossary. If you're curious what a given term means you can check there for a definition. +


+

This page will be used to document the Mdev-GPU API as well as provide an overview of the internals of the Mdev-GPU package. +

Mdev-GPU's source code can be found here. +

+Module docs can be found here.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Compilation

+

Compiling Mdev-GPU from source is very simple however it can take a long time to complete (10 minutes for existing sources). +

If you'd like to compile Mdev-GPU yourself you can do so by cloning the repo and running the following two commands from within the repository directory: +

curl -sSL https://get.haskellstack.org/ | sh +

stack install +

These commands will generate all binaries provided by Mdev-GPU under the path ~/.local/bin/. +

If you would prefer not to wait for the program to compile you can find pre-compiled x86_64 binaries under the Releases section of the repository on GitHub. +

+

Installation

+

The binaries compiled on your local machine by Stack in the ~/.local/bin/ path or downloaded from Releases on GitHub should be copied to /usr/bin/. This can be accomplished both via install script (currently testing in ) or via management layer-agnostic package. +

+

Mdev-GPU Configuration

+

The Mdev-GPU repository provides Systemd service and example configurations for Mdev-CLI in the /etc/ folder. On installation the directories & files contained in the repository's /etc/ folder should be copied to the absolute path /etc/ on the user's computer. +

+

Systemd

+

GVM/Mdev-GPU exposes several of it's functions as Systemd services. +

As of the 0.1.0.0 release the following Systemd services are available: +

+
  • mdev-post.service
+
mdev-post.service
+

As the name would suggest mdev-post.service posts the GPU(s) in a state where they are ready to be virtualized. When the service is invoked the mdev-cli util registers Mdev callbacks and supported mediated device (Mdev) types with the Mediated Core according to the user's specified configuration at /etc/gvm/mdev-gpu/generate-vgpu-types.yaml. If you'd like to place your configuration file elsewhere and still have your configuration invoked on boot you can edit the systemd service ExecStart= line to specify an alternative path. +

+

Mdev-CLI

+

Configuration for Mdev-GPU can be found in the path /etc/gvm/mdev-gpu/. This path will by default contain several vendor-specific folders which may include configuration examples for various devices/architectures as well as the file generate-vgpu-types.yaml which you can configure to specify your desired Virtual GPU (vGPU) / VFIO-Mdev topologies as they are presented in the sysfsdev mdev_bus path and as seen by tools such as mdevctl. Once you have configured the available types your liking you can refresh the supported types registered with the Mediated Core by rebooting your machine or reloading the vendor driver kernel module then restarting mdev-post.service or by invoking mdev-cli. +


+The available yaml properties which may be specified in /etc/gvm/mdev-gpu/generate-vgpu-types.yaml are shown below. Note that fields with the [required] tag must be specified in the yaml file whereas fields with the [optional] tag may be omitted from configuration if you would prefer to rely upon default parameters instead. +

+
num
+

[required] +

num refers to the Mediated Device (Mdev) type number. This value specifies the profile's numerical identifier in the sysfsdev mdev_bus path. +

+
vDevId
+

[optional] +

The vGPU (Virtual GPU) PCI Device ID which should be presented to the guest. +

+
pDevId
+

[optional] +

The pGPU (Physical GPU) PCI Device ID which should be presented to the host. +

+
name
+

[optional] +

The GPU name presented to the guest. +

+
gpuClass
+

[optional] +

The class of GPU to use. +

available strings: +

"Compute" +

"Graphics" +

+
maxInstances
+

[required] +

maxInstances refers to the maximum number of instances available of any given Mediated Device (Mdev) profile. This number can be configured arbitrarily however it should ideally not be set to a value which allows for fbLen/fbRes values that allow a number of Mdev devices to be created which would exceed your device's available VRAM. +

+
virtDisplay
+

[optional] +

virtDisplay controls the topologies of virtual displays. virtDisplay exposes the following user configurable properties: +

+
numHeads
+

[optional] +

Number of heads [virtual monitors] available for each Mediated Device (Mdev). +

+
maxResX
+

[optional] +

Maximum width of the mediated display. +

+
maxResY
+

[optional] +

Maximum height of the mediated display. +

+
frlConfig
+

[optional] +

Frame rate limiter for the mediated display. +

+
frlEnable
+

[optional] +

Do we enable frame rate limiting or not? +

+
ecc
+

[optional] +

ecc refers to if error correcting memory should be used. +

+
fbLen
+

[required] +

fbLen is the framebuffer length (in megabytes). +

+
fbRes
+

[required] +

fbRes is the framebuffer reserved by the hypervisor (in megabytes). In most circumstances this value should scale to around 1/7th the size of your chosen fbLen value. +

+
mapVideoSize
+

[optional] +

Mappable video size in MBs, 24 by default. +

+
encCap
+

[optional] +

Percentage we use the NvEnc hardware. +

+
bar1Len
+

[optional] +

bar1Len refers to the size of the Base Address Registers for BAR1 (MSI) as presented by the VFIO File Descriptor. +

+ + + + +
+
Retrieved from "https://open-iov.org/index.php?title=Mdev-GPU&oldid=23740"
+ +
+
+ +
+

Navigation menu

+
+ + +
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+ + + +
+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Mediated_Device_Internals.html b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html new file mode 100644 index 0000000..fb28c2e --- /dev/null +++ b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html @@ -0,0 +1,1014 @@ + + + + +Virtual I/O Internals - Open-IOV + + + + + + + + + + + + +
+
+
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+
+
+

Virtual I/O Internals

+
+
From Open-IOV
+
(Redirected from Mediated Device Internals)
+
+ +
+ Jump to navigation + Jump to search +

The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
    • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
    2. +
  2. mdpy-fb.c
    3. +
  3. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
    2. +
  2. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
    3. +
  3. [2017] Scalable I/O Virtualization by Kevin Tian
    4. +
  4. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
    5. +
  5. Scalable I/O Virtualization Revision 1.0
    6. +
  6. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
    7. +
  7. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
    8. +
  8. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
    9. +
  9. IOCTL
    10. +
  10. eventfd - root/virt/kvm/eventfd.c
    11. +
  11. (kernel diff:: KVM: irqfd)
    12. +
  12. (kernel diff:: KVM: add ioeventfd support)
    13. +
  13. KVM irqfd & ioeventfd
    14. +
  14. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
    15. +
  15. VFIO Mediated Devices
    16. +
  16. IOMMU Aware Mediated Device
    17. +
  17. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
    18. +
  18. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
    19. +
  19. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
    20. +
  20. Auxiliary Bus
    21. +
  21. Shared Virtual Addressing
    22. +
  22. vfio.blogspot.com
    23. +
  23. XenGT by Kevin Tian
    24. +
  24. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
    25. +
  25. PCI SIG I/O Virtualization
    26. +
  26. VMGL by the University of Toronto Computer Science Department
    27. +
  27. Kepler VGX Hypervisor
    28. +
  28. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
    29. +
  29. DMA-Mapping.txt (Dynamic DMA Mapping)
    30. +
  30. KVM MMU Virtualization by Xiao Guangrong
    31. +
  31. OSDEV: PCI
    32. +
  32. Down to the TLP: How PCI express devices talk (Part I)
    33. +
  33. Down to the TLP: How PCI express devices talk (Part II)
    34. +
  34. Intel ACRN: Enabling SR-IOV Virtualization
    35. +
  35. Kernel.org sysfs-bus-pci
    36. +
  36. Linux Kernel Labs: Memory Mapping
    37. +
  37. Inside Windows Page Frame Number (PFN) - Part 1
    38. +
  38. Direct Rendering Infrastructure (DRI)
    39. +
  39. DRI User Guide
    40. +
  40. Linux Kernel Labs: IO Virtualization
    41. +
  41. Gallium3D: Main Page
    42. +
  42. Gallium3D Wiki
    43. +
  43. Gallium3D talk from XDS 2007
    44. +
  44. Memory Management High Level Design (ARCN)
    45. +
  45. Block Architecture Diagrams for Geforce series
    46. +
  46. Block diagrams for 40 series instruction format
    47. +
  47. PCI Configuration Space
    48. +
  48. GPU virtual memory in WDDM 2.0
    49. +
  49. Intel Graphics Programmer's Reference Manuals (PRM)
    50. +
  50. i915: Hardware Contexts (and some bits about batchbuffers)
    51. +
  51. i915: The Global GTT Part 1
    52. +
  52. i915: Aliasing PPGTT Part 2
    53. +
  53. i915: True PPGTT Part 3
    54. +
  54. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    55. +
  55. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    56. +
  56. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    57. +
  57. A deep dive into QEMU: PCI slave devices
    58. +
  58. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
    59. +
  59. IOMMU Introduction
    60. +
  60. Arch Wiki: Intel Graphics
    61. +
  61. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
    62. +
  62. Kernel.org: vfio iommu type1: Add support for mediated devices
    63. +
  63. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    64. +
  64. More Shadow Walker: The Progression of TLB-Splitting on x86
    65. +
  65. MMU Virtualization Via Intel EPT: Technical Details
    66. +
  66. Alex Williamson Github: VFIO Development (tree next)
    67. +
  67. GPU PMU: performance monitoring with perf event
    68. +
  68. Remote Procedure Call (RPC)
    69. +
  69. Virtual Open Systems: API Remoting
    70. +
  70. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
    71. +
  71. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
    72. +
  72. docs.kernel.org: DRM Memory Management
    73. +
  73. docs.kernel.org: PCI Bus Subsystem
    74. +
  74. openglbook.com: What is OpenGL?
    75. +
  75. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
    76. +
  76. Dynamic Mediation for Live Migration VFIO-PCI
    77. +
  77. DRM Management Via CGroups
    78. +
  78. DRM: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
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Merged Drivers

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From Open-IOV
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The following page will provide specifications and details on the current state of host DRM + VFIO-Mdev drivers in support of various vendors. +

In the context of this page the term "Merged Driver" refers to drivers which allow simultaneous acceleration of the host using a device's PF (Physical Function) and acceleration of guests using one or more VFs (Virtual Functions) created using the same device. +

+Merged functionality is currently supported for drivers which both make use of VFIO-Mdev and SR-IOV functionality depending on the vendor and driver implementation.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel i915

+
Intel's slides mention the ability to accelerate up to '8 VMs plus DOM0'. Source: https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf
+

Intel currently supports host DRM and VFIO-Mdev/SR-IOV functionality in it's current i915 driver sources (VFIO-Mdev/GVT-g) and upstreaming i915 driver sources (VFIO-Mdev/SR-IOV). +

+

Known Issues

+
  1. SR-IOV functionality is undocumented in the i915 driver API documentation.
    Confirmed affected versions: *
    A diagram depicting i915's shared host + VFIO-Mdev driver model.
+

Resolved Issues

+
  1. Multiplexing functionality requires use modified KVM and Xen hypervisors (KVMGT/XenGT).
    Confirmed affected versions:     current i915 driver sources (GVT-g)
    Fixed in:     upstreaming i915 driver sources (SR-IOV)
+

Nvidia

+

Known Issues

+
  1. Power management on laptops running mediated graphics functionality may causes graphical errors when not plugged in to AC power.
    Confirmed affected versions: 460.32.01, 460.73.04
    Possible mitigation: lore.kernel.org: "vfio/pci: Change the PF power state to D0 before enabling VFs"
    2. +
  2. VFIO-vmalloc errors may occur as a result of page collisions between host & guest on GPUs with smaller VRAM frame buffer sizes.
    Confirmed affected versions: 460.32.01, 460.73.04
    3. +
  3. Mdev service daemons may crash or load incorrectly requiring a service restart or reboot during host runtime.
    Confirmed affected versions: 460.32.01, 460.73.04, 510.xx.xx
    4. +
  4. Guest drivers fail to initialize correctly when VFIO-Mdev devices are mixed with some VFIO passthrough'd USB hubs.
    Confirmed affected versions: 460.73.01
+

Resolved Issues

+
  1. Upon executing QEMU mdev device initialization for a second Mdev an IOMMU group binding error occurs in QEMU preventing the device from being brought up.
    Confirmed affected versions: 460.32.01, 460.73.04
    Fixed in: 510.xx.xx
+

Module Configuration

+

Depending on your use-case the use of some additional parameters when booting the system may be helpful. +

Here is a list of some parameters which may be used when loading the module via GRUB or Systemd-boot. +

+ + + + + + + + + + + + + +
Module Parameters +
Parameter +Description +Side-Effects +
cudahost=1 +Allows use of CUDA on the host system. +Windows guests may fail. +
nvidia.vgpukvm=0 +Disables GPU virtualization on the host. + +
+

AMDGPU

+

At this time AMDGPU does not currently support VFIO-Mdev functionality. It may be possible to incorporate Mdev Mode mediated device support similar to those functions in nvidia.ko and i915.ko in the Linux kernel's AMDGPU driver sources to produce a driver suitable for merged host+guest DRM for use with AMD GPU devices. +

+

Known Issues

+
  1. Host DRM does not work alongside guest VFIO-Mdev.
    Confirmed affected versions: *
    2. +
  2. The amdgpu kernel module doesn't contain hooks for guest signalling via irqfd & ioeventfd used for VFIO-mdev callbacks.
    Confirmed affected versions: *
+ + + + +
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Open-IOV:About

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From Open-IOV
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization.  +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility. +

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OpenRM

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OpenRM refers to the open sourcing of the NVIDIA kernel module for Linux, specifically the RM Core or the internal resource manager. +

+Through the open sourced code (located here) we have been able to deduce 7 top level APIs that are being exposed to the Linux developers.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Interaction With OpenRM

+

All of OpenRM is a high scale object oriented abstraction layer for the GPU, all resources are internally classes which have control definitions (methods) on how you can use them. These classes can also represent physical resources or engines. +

+

Alloc (Client)

+

This is analogous to calling an object constructor in a higher level programming language, such as C#. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
    2. +
  2. hObjectParent - Parent of the resource we are allocating.
    3. +
  3. hObjectNew - New object to allocate.
    4. +
  4. hClass - Class of the object we are dealing with.
    5. +
  5. pAllocParams - Pointer to values passed into the constructor call.
    6. +
  6. status - Status of the constructor call (did it succeed or fail)
+

Alloc Memory 64

+

This creates a CPU's mapping to a resource. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
    2. +
  2. hObjectParent - Parent of the resource we create the CPU mapping to.
    3. +
  3. hObjectNew - Mapping object resource id.
    4. +
  4. hClass - Class of the mapped object.
    5. +
  5. flags - Flags to use on the mapped object.
    6. +
  6. pMemory - pointer for the memory to map.
    7. +
  7. pLimit - Edge of memory map.
    8. +
  8. status - Status of the constructor call.
+

NOTE: Seems to be deprecated. +

+

Control

+

This is a control command which is analogous to calling a method on a class. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
    2. +
  2. hObject - Object id.
    3. +
  3. cmd - Method to call.
    4. +
  4. params - Parameters into this method.
    5. +
  5. paramsSize - Size of the params.
    6. +
  6. status - Status of the control call.
+

NOTE: The control will overwrite the object we pass in over the params pointer. +

+

Dup Object

+

Duplicates the object, or clones the object, which is a deep copy. This procedure can be used across processes in order to produce shared memory. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
    2. +
  2. hParent - Parent of the object.
    3. +
  3. hObject - Object destination for duplicating.
    4. +
  4. hClientSrc - Client source id.
    5. +
  5. hObjectSrc - Object source.
    6. +
  6. flags - Flags to use.
    7. +
  7. status - Status of the duplication.
+

Free

+

Frees an object from the object tree. +

The data for this call requires the following components: +

+
  1. hRoot - Client Id.
    2. +
  2. hObjectParent - Parent of the object.
    3. +
  3. hObjectOld - Object to call the destructor on.
    4. +
  4. status - Status of the free.
+

Vid Heap Control

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Map Memory

+

This seems to be the same as alloc memory but seems to be used more often. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device id.
    3. +
  3. hMemory - Memory resource.
    4. +
  4. offset - Offset of the memory.
    5. +
  5. length - Length of the memory.
    6. +
  6. pLinearAddress - Pointer for returned address.
    7. +
  7. status - Status of the map memory.
    8. +
  8. flags - Flags to use.
+

Unmap Memory

+

This unmaps the CPU memory mapping from the resource. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hMemory - Memory Id.
    4. +
  4. pLinearAddress - pointer to virtual address.
    5. +
  5. status - Status of the unmap command.
    6. +
  6. flags - Flags to use.
+

Alloc Context DMA 2

+

Allocates a context for DMA. +

The data for this call requires the following components: +

+
  1. hObjectParent - Object parent.
    2. +
  2. hSubDevice - Sub device to allocate on.
    3. +
  3. hObjectNew - Context id.
    4. +
  4. hClass - Type of class.
    5. +
  5. flags - Flags to use.
    6. +
  6. selector - UNKNOWN.
    7. +
  7. hMemory - Handle for Memory resource to DMA map.
    8. +
  8. offset - Offset for the DMA mapping.
    9. +
  9. limit - Limit of the DMA map.
    10. +
  10. status - Status of the allocation.
+

NOTE: Seems to be deprecated. +

+

Map Memory DMA

+

Map a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hDma - DMA Id.
    4. +
  4. hMemory - Memory Id.
    5. +
  5. offset - Offset of the region.
    6. +
  6. limit - Limit of the region.
    7. +
  7. flags - flags to use.
    8. +
  8. dmaOffset - Offset of the mapping.
    9. +
  9. status - Status of the map Memory DMA.
+

Un-map Memory DMA

+

Unmaps a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hDma - DMA handle.
    4. +
  4. hMemory - Memory handle.
    5. +
  5. flags - Flags to use.
    6. +
  6. dmaOffset - DMA Offset to unmap.
    7. +
  7. status - Status of the unmap Memory DMA.
+

Bind Context DMA

+

Binds a context for DMA interaction to a channel. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hChannel - Channel Id.
    3. +
  3. hCtxDma - Context for DMA Id.
    4. +
  4. status - Status of the bind context DMA.
+

NOTE: Seems to be deprecated. +

+

Share

+

Sharing of a resource between multiple clients. +

TODO: Understand this sharing more. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hObject - Resource Id.
    3. +
  3. sharePolicy - Share policy.
    4. +
  4. status - Status of sharing.
+

Add VBlank Callback

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Engines

+

There are engines which internally act as classes inside the OpenRM driver. +

These classes have a few key components that make them unique. +

+

Table of Engines

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Engines +
Engine +Description +
Invalid +Does not exist. +
Software +Abstraction layer for software processes inside the OS Software. +
GPU +Interaction layer with the GPU. +
Falcon +Interaction with the Falcon on the GPU. +
Master Control +Unknown. +
Kernel Master Control +Interaction with the PMC.[1] +
Private Ring +Interaction with a private messaging ring. +
Software Interrupt +Interaction with software interrupts. +
Memory System +Interaction with the memory system. +
Kernel Memory System +Interaction with the kernel memory system. +
Memory Manager +Interaction with the memory management system. +
FBFlcn +Interaction with the FBFlcn subsystem. +
TMR +Interaction with the TMR on specific chips. +
DMA +Interaction with a GPU's DMA access. +
Kernel FIFO +First in First out queue in the GPU driver. +
FIFO +Interaction with a generic FIFO. +
OS +Interaction with the OS. +
BUS +PCI Bus interaction +
Kernel BUS +Internal module BUS. +
INFOROM +Interaction with the INFOROM Region on the GPU. +
PERF +Unknown. +
Kernel PERF +Unknown. +
BIF +Unknown. +
Kernel BIF +Unknown. +
SF +Unknown. +
GPIO +Interaction with GPIO. +
CLK +Clock manager system. +
Kernel Display +Kernel Display system. +
DISP +Display system. +
DPU +Data Processing Unit. +
+ +
+ +
+ + + + +
+
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The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
    • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
    2. +
  2. mdpy-fb.c
    3. +
  3. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
    2. +
  2. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
    3. +
  3. [2017] Scalable I/O Virtualization by Kevin Tian
    4. +
  4. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
    5. +
  5. Scalable I/O Virtualization Revision 1.0
    6. +
  6. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
    7. +
  7. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
    8. +
  8. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
    9. +
  9. IOCTL
    10. +
  10. eventfd - root/virt/kvm/eventfd.c
    11. +
  11. (kernel diff:: KVM: irqfd)
    12. +
  12. (kernel diff:: KVM: add ioeventfd support)
    13. +
  13. KVM irqfd & ioeventfd
    14. +
  14. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
    15. +
  15. VFIO Mediated Devices
    16. +
  16. IOMMU Aware Mediated Device
    17. +
  17. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
    18. +
  18. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
    19. +
  19. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
    20. +
  20. Auxiliary Bus
    21. +
  21. Shared Virtual Addressing
    22. +
  22. vfio.blogspot.com
    23. +
  23. XenGT by Kevin Tian
    24. +
  24. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
    25. +
  25. PCI SIG I/O Virtualization
    26. +
  26. VMGL by the University of Toronto Computer Science Department
    27. +
  27. Kepler VGX Hypervisor
    28. +
  28. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
    29. +
  29. DMA-Mapping.txt (Dynamic DMA Mapping)
    30. +
  30. KVM MMU Virtualization by Xiao Guangrong
    31. +
  31. OSDEV: PCI
    32. +
  32. Down to the TLP: How PCI express devices talk (Part I)
    33. +
  33. Down to the TLP: How PCI express devices talk (Part II)
    34. +
  34. Intel ACRN: Enabling SR-IOV Virtualization
    35. +
  35. Kernel.org sysfs-bus-pci
    36. +
  36. Linux Kernel Labs: Memory Mapping
    37. +
  37. Inside Windows Page Frame Number (PFN) - Part 1
    38. +
  38. Direct Rendering Infrastructure (DRI)
    39. +
  39. DRI User Guide
    40. +
  40. Linux Kernel Labs: IO Virtualization
    41. +
  41. Gallium3D: Main Page
    42. +
  42. Gallium3D Wiki
    43. +
  43. Gallium3D talk from XDS 2007
    44. +
  44. Memory Management High Level Design (ARCN)
    45. +
  45. Block Architecture Diagrams for Geforce series
    46. +
  46. Block diagrams for 40 series instruction format
    47. +
  47. PCI Configuration Space
    48. +
  48. GPU virtual memory in WDDM 2.0
    49. +
  49. Intel Graphics Programmer's Reference Manuals (PRM)
    50. +
  50. i915: Hardware Contexts (and some bits about batchbuffers)
    51. +
  51. i915: The Global GTT Part 1
    52. +
  52. i915: Aliasing PPGTT Part 2
    53. +
  53. i915: True PPGTT Part 3
    54. +
  54. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    55. +
  55. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    56. +
  56. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    57. +
  57. A deep dive into QEMU: PCI slave devices
    58. +
  58. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
    59. +
  59. IOMMU Introduction
    60. +
  60. Arch Wiki: Intel Graphics
    61. +
  61. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
    62. +
  62. Kernel.org: vfio iommu type1: Add support for mediated devices
    63. +
  63. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    64. +
  64. More Shadow Walker: The Progression of TLB-Splitting on x86
    65. +
  65. MMU Virtualization Via Intel EPT: Technical Details
    66. +
  66. Alex Williamson Github: VFIO Development (tree next)
    67. +
  67. GPU PMU: performance monitoring with perf event
    68. +
  68. Remote Procedure Call (RPC)
    69. +
  69. Virtual Open Systems: API Remoting
    70. +
  70. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
    71. +
  71. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
    72. +
  72. docs.kernel.org: DRM Memory Management
    73. +
  73. docs.kernel.org: PCI Bus Subsystem
    74. +
  74. openglbook.com: What is OpenGL?
    75. +
  75. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
    76. +
  76. Dynamic Mediation for Live Migration VFIO-PCI
    77. +
  77. DRM Management Via CGroups
    78. +
  78. DRM: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
+
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Virtual I/O Internals

+
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From Open-IOV
+
(Redirected from Virtual IO Internals)
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The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
    • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
    2. +
  2. mdpy-fb.c
    3. +
  3. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
    2. +
  2. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
    3. +
  3. [2017] Scalable I/O Virtualization by Kevin Tian
    4. +
  4. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
    5. +
  5. Scalable I/O Virtualization Revision 1.0
    6. +
  6. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
    7. +
  7. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
    8. +
  8. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
    9. +
  9. IOCTL
    10. +
  10. eventfd - root/virt/kvm/eventfd.c
    11. +
  11. (kernel diff:: KVM: irqfd)
    12. +
  12. (kernel diff:: KVM: add ioeventfd support)
    13. +
  13. KVM irqfd & ioeventfd
    14. +
  14. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
    15. +
  15. VFIO Mediated Devices
    16. +
  16. IOMMU Aware Mediated Device
    17. +
  17. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
    18. +
  18. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
    19. +
  19. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
    20. +
  20. Auxiliary Bus
    21. +
  21. Shared Virtual Addressing
    22. +
  22. vfio.blogspot.com
    23. +
  23. XenGT by Kevin Tian
    24. +
  24. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
    25. +
  25. PCI SIG I/O Virtualization
    26. +
  26. VMGL by the University of Toronto Computer Science Department
    27. +
  27. Kepler VGX Hypervisor
    28. +
  28. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
    29. +
  29. DMA-Mapping.txt (Dynamic DMA Mapping)
    30. +
  30. KVM MMU Virtualization by Xiao Guangrong
    31. +
  31. OSDEV: PCI
    32. +
  32. Down to the TLP: How PCI express devices talk (Part I)
    33. +
  33. Down to the TLP: How PCI express devices talk (Part II)
    34. +
  34. Intel ACRN: Enabling SR-IOV Virtualization
    35. +
  35. Kernel.org sysfs-bus-pci
    36. +
  36. Linux Kernel Labs: Memory Mapping
    37. +
  37. Inside Windows Page Frame Number (PFN) - Part 1
    38. +
  38. Direct Rendering Infrastructure (DRI)
    39. +
  39. DRI User Guide
    40. +
  40. Linux Kernel Labs: IO Virtualization
    41. +
  41. Gallium3D: Main Page
    42. +
  42. Gallium3D Wiki
    43. +
  43. Gallium3D talk from XDS 2007
    44. +
  44. Memory Management High Level Design (ARCN)
    45. +
  45. Block Architecture Diagrams for Geforce series
    46. +
  46. Block diagrams for 40 series instruction format
    47. +
  47. PCI Configuration Space
    48. +
  48. GPU virtual memory in WDDM 2.0
    49. +
  49. Intel Graphics Programmer's Reference Manuals (PRM)
    50. +
  50. i915: Hardware Contexts (and some bits about batchbuffers)
    51. +
  51. i915: The Global GTT Part 1
    52. +
  52. i915: Aliasing PPGTT Part 2
    53. +
  53. i915: True PPGTT Part 3
    54. +
  54. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    55. +
  55. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    56. +
  56. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    57. +
  57. A deep dive into QEMU: PCI slave devices
    58. +
  58. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
    59. +
  59. IOMMU Introduction
    60. +
  60. Arch Wiki: Intel Graphics
    61. +
  61. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
    62. +
  62. Kernel.org: vfio iommu type1: Add support for mediated devices
    63. +
  63. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    64. +
  64. More Shadow Walker: The Progression of TLB-Splitting on x86
    65. +
  65. MMU Virtualization Via Intel EPT: Technical Details
    66. +
  66. Alex Williamson Github: VFIO Development (tree next)
    67. +
  67. GPU PMU: performance monitoring with perf event
    68. +
  68. Remote Procedure Call (RPC)
    69. +
  69. Virtual Open Systems: API Remoting
    70. +
  70. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
    71. +
  71. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
    72. +
  72. docs.kernel.org: DRM Memory Management
    73. +
  73. docs.kernel.org: PCI Bus Subsystem
    74. +
  74. openglbook.com: What is OpenGL?
    75. +
  75. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
    76. +
  76. Dynamic Mediation for Live Migration VFIO-PCI
    77. +
  77. DRM Management Via CGroups
    78. +
  78. DRM: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
+
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Virtualization Fundamentals

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From Open-IOV
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This following page is intended to index and summarize information related to the fundamentals of virtualization of computer systems.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Popek and Goldberg Virtualization Requirements

+

The Popek and Goldberg virtualization requirements are a set of conditions sufficient for a computer architecture to support system virtualization efficiently. They were introduced by Gerald J. Popek and Robert P. Goldberg in their 1974 article "Formal Requirements for Virtualizable Third Generation Architectures". Even though the requirements are derived under simplifying assumptions, they still represent a convenient way of determining whether a computer architecture supports efficient virtualization and provide guidelines for the design of virtualized computer architectures. +

+

Goldberg Survey of Virtual Machine Research

+

The complete instruction-by-instruction simulation of one computer system on a different system is a well-known computing technique. It is often used for software development when a hardware base is being altered. For example, if a programmer is developing software for some new special purpose (e.g., aerospace) computer X which is under construction and as yet unavailable, he will likely begin by writing a simulator for that computer on some available general-purpose machine G. The simulator will provide a detailed simulation of the special-purpose environment X, including its processor, memory, and I/O devices. Except for possible timing dependencies, programs which run on the “simulated machine X” can later run on the “real machine X” (when it is finally built and checked out) with identical effect. The programs running on X can be arbitrary — including code to exercise simulated I/O devices, move data and instructions anywhere in simulated memory, or execute any instruction of the simulated machine. The simulator provides a layer of software filtering which protects the resources of the machine G from being misused by programs on X. +

+

Microkernels Meet Recursive Virtual Machines

+

This paper describes a novel approach to providing mod- ular and extensible operating system functionality and en- capsulated environments based on a synthesis of micro- kernel and virtual machine concepts. We have developed a software-based virtualizable architecture called Fluke that allows recursive virtual machines (virtual machines running on other virtual machines) to be implemented ef- ficiently by a microkernel running on generic hardware. A complete virtual machine interface is provided at each level; efficiency derives from needing to implement only new functionality at each level. This infrastructure allows common OS functionality, such as process management, demand paging, fault tolerance, and debugging support, to be provided by cleanly modularized, independent, stack- able virtual machine monitors, implemented as user pro- cesses. It can also provide uncommon or unique OS fea- tures, including the above features specialized for particu- lar applications’ needs, virtual machines transparently dis- tributed cross-node, or security monitors that allow arbi- trary untrusted binaries to be executed safely. Our proto- type implementation of this model indicates that it is prac- tical to modularize operating systems this way. Some types of virtual machine layers impose almost no overhead at all, while others impose some overhead (typically 0–35%), but only on certain classes of applications. +

+

A Comparison of Software and Hardware Techniques for x86 Virtualization

+

Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMwareR Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization. We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution. We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization. +

+

Virtualizing I/O Devices on VMware Workstation’s Hosted Virtual Machine Monitor

+

Virtual machines were developed by IBM in the 1960’s to provide concurrent, interactive access to a mainframe computer. Each virtual machine is a replica of the underlying physical machine and users are given the illusion of running directly on the physical machine. Virtual machines also provide benefits like isolation and resource sharing, and the ability to run multiple flavors and configurations of operating systems. VMware tmWorkstation brings such mainframe-class virtual machine technology to PC-based desktop and workstation computers. This paper focuses on VMware Workstation’s approach to virtualizing I/O devices. PCs have a staggering variety of hardware, and are usually pre-installed with an operating system. Instead of replacing the pre-installed OS, VMware Workstation uses it to host a user-level application (VMApp) component, as well as to schedule a privileged virtual machine monitor (VMM) component. The VMM directly provides high-performance CPU virtualization while the VMApp uses the host OS to virtualize I/O devices and shield the VMM from the variety of devices. A crucial question is whether virtualizing devices via such a hosted architecture can meet the performance required of high throughput, low latency devices. To this end, this paper studies the virtualization and performance of an Ethernet adapter on VMware Workstation. Results indicate that with optimizations, VMware Workstation’s hosted virtualization architecture can match native I/O throughput on standard PCs. Although a straightforward hosted implementation is CPU-limited due to virtualization overhead on a 733 MHz PentiumR III system on a 100 Mb/s Ethernet, a series of optimizations targeted at reducing CPU utilization allows the system to match native network throughput. Further optimizations are discussed both within and outside a hosted architecture. +

+

Dynamic binary translation and optimization

+

We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach o�ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime pro�le information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system, and their impact on �nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage. Keywords| dynamic compilation, binary translation, dynamic optimization, just-in-time compilation, adaptive code generation, pro�le-directed feedback, instruction-level parallelism, very long instruction word architectures, virtual machines, instruction set architectures, instruction set layering. +

+

Xen and the Art of Virtualization

+

Numerous systems have been designed which use virtualization to subdivide the ample resources of a modern computer. Some require specialized hardware, or cannot support commodity operating systems. Some target 100% binary compatibility at the expense of performance. Others sacrifice security or functionality for speed. Few offer resource isolation or performance guarantees; most provide only best-effort provisioning, risking denial of service. This paper presents Xen, an x86 virtual machine monitor which allows multiple commodity operating systemsto share conventional hardware in a safe and resource managed fashion, but without sacrificing either performance or functionality. This is achieved by providing an idealized virtual machine abstraction to which operating systems such as Linux, BSD and Windows XP, can be ported with minimal effort. Our design is targeted at hosting up to 100 virtual machine instances simultaneously on a modern server. The virtualization approach taken by Xen is extremely efficient: we allow operating systems such as Linux and Windows XP to be hosted simultaneously for a negligible performance overhead — at most a few percent compared with the unvirtualized case. We considerably outperform competing commercial and freely available solutions in a range of microbenchmarks and system-wide tests. +

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The AMDGPU driver is AMD's open source GPU driver which comes included with the Linux kernel.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

This software's source code can be viewed here. +


+

This Open-IOV page should aim to provide similar insights about APIs exposed to Linux developers to those documented on the OpenRM Driver API page. +


+This page may provide some of the required information from which details immediately relevant to graphics mediation can be consolidated: +

https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html +

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This page indexes the articles contained within Open-IOV. +

If you're new to GPU Virtualization start by reading the Introduction article. +

+ + +

Start Here

+

Introduction +

About Open-IOV (CC-BY-4.0) +

+

Abstract

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Glossary +

Virtualization Fundamentals +

Merged Drivers +

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Design Documents

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Virtual I/O Internals +

GPU Driver Internals +

+

Driver Integration Documents

+

Nvidia +

Intel +

AMD +

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Projects

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LIME Is Mediated Emulation +

Looking Glass +

OpenXT +

OpenXT: vGlass +

OpenXT: Surfman (legacy DRM) +

Bromium/uXen +

Xen Project +

Qubes OS +

Intel Celadon +

vGPU_Unlock +

+

Device Support

+

GPU Support +

CPU Support +

GPU Firmware +

+

Software Support

+

Hypervisor Support +

GPU Software Bill Of Materials (SBOM) +

+

API Documentation

+

Kernel APIs

+

Kernel.org Driver Core Documentation +

NT Kernel (Windows) IOMMU-based GPU Isolation +

VFIO - vfio.h - mdev.h +

VFIO Mediated Device +

+

Driver APIs

+

i915 GVT-g API +

Nouveau Tools & API +

+

Sample Code

+

GPLv2 sources mirrored from elixir.bootlin.com with simple makefile changes. +

mtty.c - mdpy.c - mdpy-fb.c - mdpy-defs.h - mbochs.c +

+

Virtualization APIs

+

GVM/Mdev-CLI API +

QEMU Machine Protocol (QMP) Reference Manual +

Inter-VM Shared Memory (IVSHMEM) +

+

User Guides

+

Setup Guide +

Looking Glass Quickstart Guide +

Intel GVT-g Setup Guide +

AMD GPU-IOV Module Docs +

PCI passthrough via OVMF +

RedHat Virtualization Guide +

+

Developer Guides

+

Hypervisor From Scratch +

Linux Device Drivers (3rd Edition) +

GPU Driver Developer's Guide +

How To Write PCI Drivers +

Data Plane Development Kit: IVSHMEM Programming Guide +

+

Specifications

+

Hyper-V Hypervisor Top Level Functional Specification (TLFS) +

+

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+

Open-IOV Discord +

Intel-gfx Mailing List +

Nouveau Mailing List +

AMD-gfx Mailing List +

VFIO-users Mailing List +

Level1Techs Forum [VFIO Topic] +

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In order to use mediated device functionality you may need to set some or all of the following settings in your machine's UEFI.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

UEFI Setup

+

Intel CPUs (VT-d)

+

Optimal UEFI Settings +

IOMMU >> Enabled +

SR-IOV Support >> Enabled +

VT-x >> Enabled +

ARI Mode >> Enabled +

+

AMD CPUs (AMD-v)

+

Optimal UEFI Settings +

SVM Mode >> Enabled +

SR-IOV Support >> Enabled +

ACS Enable >> Enabled +

IOMMU >> Enabled +

PCI AER Support >> Enabled +

ACS Enable >> Enabled +

ARI Mode >> Enabled +

Note to AMD CPU users: If you are using a first generation Ryzen or ThreadRipper platform you may need to update your motherboard UEFI to make proper use of IOMMU Groups. If your motherboard manufacturer has not made an update available you may need to apply an ACS override patch. Successive AMD CPU platforms are unaffected. +

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Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. +

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File:I915 Scheduling Events and Requests.png

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I915 Scheduling Events and Requests +

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File:IOCTL set VFIO container.png

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Placing a VFIO binding into a VFIO Container. +

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IVSHMEM +

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File:Intel GVT-g Capabilities.png

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"Accelerate up to 8 VMs plus DOM0." +

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File:Intel i915 Host DRM + VFIO-Mdev..png

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Intel's i915 driver provides host and guest GPU acceleration via host DRM + VFIO-Mdev in the same driver. +

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File:Ioctl-VFIO GROUP GET FD.png

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Original file ‎(1,782 × 1,210 pixels, file size: 110 KB, MIME type: image/png) +

Using an interrupt routine to obtain the VFIO Group file descriptor. +

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File:Ioctl-VFIO IOMMU MAP-UNMAP DMA.png

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Original file ‎(1,748 × 1,246 pixels, file size: 109 KB, MIME type: image/png) +

Using interrupts VFIO_IOMMU_MAP/UNMAP_DMA to pin/map regions of memory. +

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"A very simple" diagram of ioeventfd and irqfd. +

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File:KVM services EPT violation and forwards to QEMU VFIO PCI driver..png

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KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

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Peer-to-Peer DMA Isolation under IOMMU +

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File:Type 1 IOMMU Tracks VA-GFN.png

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Type 1 IOMMU Tracks VA-GFN +

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File:VFIO-Mdev Diagram.png

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A diagram of VFIO-Mdev. +

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VFIO_Diagram.png ‎(398 × 527 pixels, file size: 62 KB, MIME type: image/png) +

A VFIO diagram. +

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GPU Driver Internals

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Revision as of 17:53, 19 June 2023 by Arthur (talk | contribs) (→‎References (Talks & Reading Material))
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This page will detail the internals of various GPU drivers for use with I/O Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Article Structure

+

This article will aim to provide information about the following details of GPU drivers: +

+

High Level Architecture

+

This section will detail high level architectures of each driver. +

+

Initialization

+

This section will cover how the GPU's embedded components, the GPU driver, and virtualization functions are initialized. +

+

Scheduling

+

This section will detail how the device schedules instructions for execution. +

This will attempt to provide a comprehensive view of scheduling from virtualized processes down to execution within the device. +

+

In-VM Scheduling

+

The In-VM Scheduling section will detail how instructions scheduled within the virtual machine's GPU device driver. +

+

Between-VM Scheduling

+

The Between-VM Scheduling section will detail how the host kernel module and/or virtual GPU helper functions handle scheduling / context swaps between virtual machines on a computer system. +

+

Firmware Scheduling (if applicable)

+

The Firmware Scheduling section will cover the GPU's internal scheduling model if a deferred execution pathway is used (like i915's GuC or OpenRM's GSP). +

In the case an intermediate scheduling microcontroller is not used this section may be less applicable (ie: vExeclist scheduling under Intel vGPUs). +

+

Memory Management

+

The Memory Management section will cover how the GPU driver manages memory for virtual GPUs and host processes. +

This will aim detail paging abstractions used for global memory translation, and per-process memory translation. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will cover methods provided by the GPU driver suitable for high performance graphics sharing. +

+

Vendor Neutral

+

This section will detail functions in common between GPU drivers. +

Also see Display Virtualization for Windows OS. +

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Satyeshwar Singh. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will deal with graphics buffer sharing for vendor neutral GPUs. +

+
Display Flow in Linux
+

Userspace applications provide their buffers to compositor. +

Compositor asks Mesa to create a framebuffer. +

Framebuffer is allocated through vendor driver. +

Vendor driver flips the framebuffer on the screen. +

+
SR-IOV and Mdev
+

SR-IOV VFs don't have access to the display controller (only PF does). +

Known issue is displaying a VF's framebuffer on the screen. +

+
VFs in QEMU Hypervisor (VirtIO-GPU)
+

SR-IOV and Mdev VFs run in QEMU Hypervisor. +

QEMU has full access to all pages in VF's address space. +

VirtIO-GPU allows for allocating buffers (not API remoting in this case). +

Mesa's KMSRO allocates framebuffer via virtio-gpu. +

Mesa's KMSRO asks vendor driver to import framebuffer (no specific compositor dependancy). +

+
Transport
+

A Scatter Gather List (SGL) of physical pages is constructed by VirtIO-GPU of VF. +

+
QEMU Host-Side u-dma-buf
+

Host QEMU uses u-dma-buf driver to reconstruct a virtual memory pointer from the SGL shared by VF. +

u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers. +

+
QEMU Host-Side Modules
+

Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI. +

QEMU UI has several toolkits to support like GTK, SDL, etc. with GTK. being the default. +

GTK uses EGL and passes it the DMABUF as a texture. +

+
Windows VFs
+

Windows OS doesn't support DMABUF capability so we can't allocate buffers from VirtIO-GPU and share them with the Windows Kernel Mode Driver (KMD). +

Windows OS is different in the way that the FB is allocated via the OS rather than the miniport driver. +

Modified version of RedHat virtio-gpu-do (short for Display Only) driver used. +

+
Windows Driver Stack
+

OS (DWM) allocates frame buffers and asks GPU to write to them through Miniport. +

DVServer UMD (IDD) asks the OS for the FB copy. +

DVServer UMD (IDD) passes the virtual memory address to DVServer KMD. +

+
DVServer KMD
+

DVServer KMD finds the SGL (Scatter Gather List) of physical pages for this virtual memory address. +

This SGL is passed via virt-queue from the VF to the host QEMU. +

+
Android VFs
+

Android uses Linux kernel underneath. VirtIO-GPU is present in Android's kernel. +

KMSRO patch to allocate framebuffer via VirtIO-GPU also ported over to Android. +

Need modifications in the minigbm lib of Android to connect with KMSRO part. +

Rest of stack looks identical to Linux VF/PF. +

+

i915

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Zhi Wang, Ben Widawsky, and Igor Bogdanov. +

See references 2, 3, 4, 5, 6, 7, 8, and 9 in the References (Talks & Reading Material) section. +

+

High Level Architecture

+

i915 Clients

+

Processes which make use of the Intel i915 driver receive an i915 Client ID. +

+

Initialization

+

During initialization of the i915 driver the GuC binary blob is offloaded into the Graphics Translation Table (GTT). This allows the GuC to read GTT-loaded binary blob from shared framebuffer memory so that it may boot. +

+

Scheduling

+
Figure 0: i915 vGPU Scheduling
Figure 0: i915 vGPU high-level Scheduling. See slides from: [9]
+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (i915.ko)
    • +
  • Host kernel (i915.ko)
    • +
  • Device Firmware (GuC)
+
In-VM Scheduling
+
Guest kernel (i915.ko)
+
vExeclist
+

The vExeclist is a method to submit commands directly to the GPU without the use of an intermediate microcontroller. +

+
vGuC
+

vGuC is a command submission interface used to process commands to the Intel Graphics Microcontroller (GuC). +

+

Between-VM Scheduling

+
Figure 1: i915 vGPU Scheduling Requests & Events
Figure 1: i915 vGPU Scheduling Requests & Events. See slides from: [9]
+
Host kernel (i915.ko)
+

Submitting commands to the GPU under i915 can take several paths. One pathway makes use of direct command submission without an intermediate micro-controller whereas the other uses an intermediate micro-controller. The intermediate micro-controller approach increases the amount of binary-blob code used and abstracts the kernel module from the device's internal scheduling model. +

+
Execlist
+

Execlist executes commands synchronously on the device without an intermediate microcontroller. This is the preferred method of executing commands by some driver developers because of it's stability and transparency under current i915 development. +

+
GuC
+

GuC provides an execution pathway with an intermediate microcontroller providing a scheduling abstraction for Intel's preferred internal scheduling model. +

+
Figure 2: Intel vGPU Scheduler request flow.
Figure 2: i915 vGPU Scheduler request flow. See slides from: [9]
+
Device Firmware (GuC)
+

Memory Management

+
Translation Tables
+
GTT (Graphics Translation Table)
+

GPU Memory on-device is a part of a GTT or Graphics Translation Table. This table stores information globally for all graphics processes within the system. Some processes access the Global Graphics Translation Table (GGTT) such as DRI while other's receive a Per Process Graphics Translation Table (PPGTT) buffer based on their i915 Client ID. +

+
GGTT (Global Graphics Translation Table)
+
PPGTT (Per Process Graphics Translation Table)
+

Process-specific memory buffers are stored inside a Per Process Graphics Translation Table or PPGTT. This is a GPU MMU translated subregion or IOVA of global GPU memory specific to a GPU process's client ID. +

+
Aliasing PPGTT
+

Aliasing PPGTT (Per Process Graphics Translation Table) refers to partially separated GPU resources (process context). +

+
Real PPGTT
+

Real PPGTT (Per Process Graphics Translation Table) refers to fully separated GPU resources (process context). +

+

Display Surface Virtualization

+

The Intel vGPU makes use of two modes for Display Surface Virtualization. +

+
  • VirtIO-GPU (Linux)
    • +
  • Indirect Display Driver (Windows)
+

VirtIO-GPU

+

IDD (Indirect Display Driver)

+

The IDD (Indirect Display Driver) provides virtual display functions with arbitrary resolutions to any rendering device virtual or physical. +

Intel's IDD can be found in their Display Virtualization for Windows OS repository. +

+

Graphics Buffer Sharing

+

Intel's i915 driver provides functionality to directly map display memory from a guest vGPU Virtual Function (either SR-IOV or VFIO-Mdev) into the host GPU's Physical Function without slow memory copies or graphics compression. For users running GPU virtualization on their local device this results in a significant performance uplift compared to traditional graphics sharing functionality built for remote access use-cases such as VDI. +

Intel's 0copy display virtualization tools are simple to implement as sharing does not rely upon an added IVSHMEM (Inter-VM Shared Memory device) - rather the host directly maps the guest's display memory via udmabuf as the buffer sharing functions are provided within the i915 open source driver. +

+

OpenRM

+
Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO
Figure 3: GPU BAR to Timeshared Scheduling via Channel IO.
+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Andy Currid, Neo Jia, John Fanelli, and Neha Joshi. +

+

High Level Architecture

+

The Open Resource Manager (RM driver) makes use of a highly object oriented paradigm comprised of multiple "engines" which act as micro-services for servicing driver requests. +

The Open Resource Manager driver (also known as OpenRM) refers to Nvidia's open-kernel-modules. +

Broadly speaking the OpenRM driver consists of two parts. +

+
  • The Platform RM (OpenRM)
    • +
  • The Firmware RM (GSP RM / RM Core)
+

The Platform RM is loaded into the Linux Kernel as nvidia.ko. This module communicates with the GSP RM for via Remote Procedure Calls (RPCs) to communicate with engines from the RM Core. +

+
RM Clients
+

Processes (local, remote, or virtualized) which make use of the RM driver receive an RM Client ID. +

+

RM Server

+

The RM Server (or Resource Server) tracks RM Clients as well as the hardware and software resources they control, allocate, and free. +

+

RM API

+

API to control the Resource Manager Server. +

+

RM Core

+

Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors. Under OpenRM the RM Core runs within the GPU System Processor (GSP micro-controller) while in pre-open source versions of the Resource Manager the RM Core ran within the nvidia.ko kernel module +

+

Initialization

+

During bring up of the hardware several binary blobs are loaded from embedded Boot ROM memory to bootstrap embedded controller bring up from which point additional software is loaded from onboard SPI flash memory. +

Software loaded from SPI flash is necessary for the full initialization of the Falcon/NvRISC processor as well as a cached version of the software necessary to run the GPU System Processor (GSP). +

Once the platform is posted it is ready to communicate with the host platform's RM driver. The OpenRM driver offloads a binary blob containing the RM Core to the GPU System Processor (GSP) which is likely to contain a more recent version than the cached version contained in on-board SPI flash. +

+

Scheduling

+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (nvidia.ko)
    • +
  • Host kernel (nvidia.ko)
    • +
  • Host usermode (gpu-mgr / libnvidiavgpu.so)
    • +
  • Device Firmware (GSP)
+

Command Submission

+
Runlist
+

In-VM Scheduling

+

Virtual machines contain their own GPU scheduling within the Nvidia kernel module in the guest OS. +

+
Guest kernel (nvidia.ko)
+

Within a virtual machine running the Nvidia driver messages to the GPU are first sent to the guest nvidia.ko kernel module. +

+The guest then determines whether a vRPC (virtual Remote Procedure Call) or a pRPC (physical Remote Procedure Call) should be sent. Both pRPCs and vRPCs are sent through the host RM driver (Resource Manager).

Note: Unclear on execution pathway for pRPCs vs vRPCs. pRPCs may go directly to device.

+

Between-VM Scheduling

+

In addition to scheduling which occurs within the virtual machine the Resource Manager driver also schedules messages to the GPU between GPU-accelerated virtual machines and host processes. +

+
Host kernel (nvidia.ko)
+

Messages sent by the guest (via vRPC or pRPC) are received by the host Nvidia.ko driver. +

Nvidia.ko contains a virtual GPU state machine which contains status information for the virtual GPU. +

Nvidia.ko also contains a virtual GPU kernel scheduler which interacts with virtual GPU objects. +

Nvidia.ko also contains an RM Call scheduler which schedules calls on an RM class. +

The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin). +

+
Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)
+

After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and it's library libnvidia-vgpu.so) are executed to schedule VM-exits described below. +

+
nvidia-vgpu-mgr
+

The nvidia-vgpu-mgr is a process which provides the spawning of virtual GPU stubs and population with capability information. +

This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components. +

This process and the libnvidia-vgpu.so contain, and execute the VMIOP. +

This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the RM Core. +

+
vmiop
+

VMIOP (Virtual Machine Input Output Plugin) handles presenting virtualized functionality into the guest. +

The Virtual Machine Input Output Plugin software handles virtual displays, compute API offload, and most importantly BAR (Base Address Register) quirks. +

The VMIOP is an SDK (Software Development Kit) provided in binary format split between the libnvidiavgpu.so and nvidia-vgpu-mgr which provides userland helper functions for GPU virtualization. +

Messages to the VMIOP are scheduled by Linux kernel niceness (scheduling abstraction). +

+
Device Firmware (GSP)
+

Messages received by the host RM driver (Resource Manager) are then scheduled by the RM Core contained within the GSP (GPU System Processor). The GSP handles the device's internal scheduling model. +

+

Memory Management

+

Managing virtual machine memory is very important to the security of virtualization. +

This section will cover the method by which secure memory "enclaves" or IO Virtual Addresses (IOVAs) may be provisioned and separation enforced by hardware constructs within the GPU. +

+
Programming the MMU
+

In order to hardware enforce separation between memory allocated to Virtual Machines (VMs) virtualization software must program the GPU's MMU (GMMU controller) to create IO Virtual Addresses (IOVAs). +

In order to create such configurations several abstractions are used to translate high level representations of virtualization programmed via the vmiop and gpu-mgr into practical, architecture specific instructions. +

+
AMAPLibrary
+

The AMAPLibrary acts as a device abstraction framework for GPU driver software to program using high level representations of MMU configuration. +

The AMAPLibrary translates high level representations of GPU virtualization into graphics architecture-specific logic contained within architecture HALs (Hardware Abstraction Layers). +

+
Architecture HALs
+

GPU Hardware Abstraction Layers (HALs) contain logic specific to graphics architectures, for instance the precise method by which the GPU driver may interact with the Falcon to provision MMU protected memory. +

+
DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)
+

The Falcon (FAst Logic CONtroller) / NvRISC-V embedded controller emits DMAs to the Frame Buffer Interface (FBIF) in order to interact with the device's GMMU controller. +

User programs and VMs have their memory translated through the GMMU. +

Once created memory translations within a virtual machine's IO Virtual Address (IOVA) will be protected by the device's GMMU controller. +

+
Translation Tables
+
vmiop_gva
+

Display Surface Virtualization

+

amdgpu

+

References (Talks & Reading Material)

+
  1. Intel Graphics Programmer's Reference Manuals (PRM)
    2. +
  2. i915: Hardware Contexts (and some bits about batchbuffers)
    3. +
  3. i915: The Global GTT Part 1
    4. +
  4. i915: Aliasing PPGTT Part 2
    5. +
  5. i915: True PPGTT Part 3
    6. +
  6. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    7. +
  7. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    8. +
  8. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    9. +
  9. i915: An Introduction to Intel GVT-g (with new architecture)
    10. +
  10. lwn.net: Add udmabuf misc device
    11. +
  11. Nvidia RISC-v Story
    12. +
  12. IOMMU Introduction
    13. +
  13. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    14. +
  14. nVidia GPU Introduction (envytools)
    15. +
  15. Delivering High Performance Remote Graphics With Nvidia GRID Virtual GPU
    16. +
  16. NVIDIA Multi-Instance GPU
    17. +
  17. i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]
    18. +
  18. Lifecycle of a Triangle - Nvidia's logical pipeline
    19. +
  19. Nvidia Parallel Thread Execution (PTX)
    20. +
  20. i915/GEM Crashcourse
    21. +
  21. drm: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
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GPU Firmware

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Revision as of 17:13, 9 April 2023 by Arthur (talk | contribs) (→‎Firmware Images)
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GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel

+

Firmware Images

+This section will cover firmware images used in Intel GPUs.

Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.
Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. Source
+

Intel Firmware Support Package (FSP)

+

Much like CPUs Intel's GPUs also contain a Firmware Support Package (FSP). +

The Coreboot project provides public domain information on the FSP here. +

+
FSP Configuration
+

In the context of GPUs the FSP configures several functions of the device. +

Those functions are as follows: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
GPU Firmware Support Package +
FSP Parameter +Possible Values +
GFSP Status +0x00 +
FIVR SSC Value +*.*% +
FIVR RFI Value +*.*MHz +
GT Subsystem Vendor ID +0x8086 +
GT Subsystem Device ID +0x** +
HDA Subsystem Vendor ID +0x0000 +
HDA Subsystem Device ID +0x0000 +
P2SB Enable +Yes/No +
LMEBAR +Max +
GTMMADDR Prefetch Capability +Prefetch Enabled +
Display Present +Enabled/Disabled +
I2C For Third Party Devices +Enabled/Disabled +
I2C Device Address 1 +0x0000 +
I2C Device Address 2 +0x0000 +
I2C Bus Speed +Standard mode (0 to 100Kbps) +
+
Editing FSP Configuration
+

The FSP configuration editor can be downloaded here and it's user manual is available here. +

+
FSP Binary Format
+

The FSP's binary layout is detailed within the Intel® FSP External Architecture Specification v2.4 on page 14. +

+

Known Firmware Package Variations

+

Some firmware packages may include an **End of Manufacturing Flash Protection Mode** status of Protected or Unprotected. +

+
Figure 2: Firmware status information for an Intel DG2 device.
Figure 2: Firmware status information for an Intel DG2 device.
+

Similar SPI Write Protection functionality is made available through Intel CPUs under System Management Mode (SMM). +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Intel GPU. +

+

GuC

+

The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs. +

+
Hardware Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The GuC - an embedded i486 core that supports graphics scheduling, power management and firmware attestation." +

+
Software Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services." +

"It runs a single process - which initializes the system and then waits for interrupts/events in a loop." +

+
GuC Blob Checksum & Code Signing
+

"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing." +

+

Nvidia

+

Firmware Images

+

This section will cover firmware images used in Nvidia GPUs. +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU. +

+

Falcon / NV-RISCV

+

The Fast Logic CONtroller (Falcon) and Nvidia RISC-V (NV-RISCV) processors run the NvOS. +

+

GSP

+

The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core. +

The GSP runs Library Operating System (LibOS). +

+
GSP Initialization & Offload
+

The GSP is initialized multiple times during the system's bring up and runtime. +

GSP offload may occur during: +

+
  • Hardware bring up when a cached version of the RM Core is loaded from SPI flash
+
  • During host driver bring up when the RM Core is offloaded by the OpenRM driver.
    • +
  • During guest driver bring up when the RM Core is offloaded.
+ + + + + + + + + + + + + + + + + +
Possible GSP Offloads +
Load Source +Payload +Notes +
SPI Flash +Cached RM Core +Used as a fallback in case of no rm offload. +
OpenRM +RM Core +This is the RM Core which was traditionally contained in the proprietary RM driver. +
VGX Guest +Guest RM Core +Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via gspHeapSize?). +
+

CMU

+

AMD

+

References (Talks & Reading Material)

+
  1. Security of the Intel Graphics Stack - Part 1 - Introduction
    2. +
  2. Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    3. +
  3. Firmware Security Realizations Part 3: SPI Write Protections
    4. +
  4. Intel® FSP: Firmware Solutions for the Internet of Things
+ + + + +
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Revision as of 14:58, 13 June 2023 by Arthur (talk | contribs) (Updated Nvidia VGX vGPU version to 15.2 in GPU SBOM.)
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This page will keep a running list of components used to achieve GPU Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Component Table +
Vendor +Component +Description +Version +OSS or Blob +Filesize +Vendor Docs +Release Date +Interfaces / APIs +Notes +
Microsoft +Indirect Display Driver (IDD) +Driver + +OSS + +Indirect Display Driver Overview + +UMDF, KMDF +The Indirect Display Driver (IDD) enables GPUs to render graphics at arbitrary resolutions without a physical display connected on Windows OS systems. +
RedHat +vfio_pci +Driver +6.2-rc1 +OSS +in-kernel +RedHat, kernel.org +2022.12.15 +irqfd, ioeventfd, IOCTL +Reference VFIO Stub driver used for discrete assignment of IO, and assignment of some SR-IOV-backed vGPU devices into virtual machines. This driver is commonly replaced with a vendor built VFIO interface with differing memory management and/or page pinning mechanisms which are specific to the vGPU software internals. +
Mediated Core (mdev.ko) +Driver +6.2-rc1 +OSS +0.044 MB +kernel.org +2016.xx.xx +irqfd, ioeventfd, IOCTL, Type 1 IOMMU +The Mediated Core driver provides a common interface for mediated device management that can be used by drivers of different devices. It is an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment (based on VFIO). +
+guest communication daemon +Daemon +0.1.0 +OSS + + +2023.02.08 +Virtio-Serial, CLI +Handles IO to and from guests and the host using Virtio-Serial to handle multiple different guest modules. +
mdev management CLI +1.0 +OSS +0.084 MB + +2023.01.06 +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
Intel +i915 SR-IOV +Driver +5.15 +OSS +in-kernel + + + +Intel's open source GPU driver for GuC-equipped graphics accelerators. +
GuC μOS +Firmware +Blob + + + +IOMMU Interrupts, Power Management Interrupts, GTT +Handles scheduling, and power management. +
HuC + + + +GTT +Handles video encoding/decoding. +
Display Virtualization for Windows OS +Driver +791 +OSS + +github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt + +udmabuf, UMDF, KMDF +Intel's 'Display Virtualization for Windows OS' provides a virtual pixel surface used for hardware graphics rendering using Microsoft's open source 'Indirect Display Driver (IDD)'. Display virtualization for Windows OS makes use of display memory sharing primitives provided in-driver by the i915 host. +
Nvidia +OpenRM +Driver +525.85.12 +OSS + +github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md +2023.01.31 + +Nvidia's open source GPU driver for GSP-equipped graphics accelerators. +
GSP RM (uproc) +Firmware +Blob + + +2023.01.31 +RPC +Embedded firmware based on LibOS containing the RM Core. +
Falcon/NvRISC (uproc) + + + + +FBIF (Frame Buffer Interface) / GMMU +Embedded firmware which handles many aspects of the device including configuring the GPU's GMMU controller. +
nvidia-vgpud +Daemon +v15.2 +Blob +0.108 MB +docs.nvidia.com/grid +2023.01.xx +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
nvidia-vgpu-mgr +0.132 MB +2023.01.xx +vmiop, IOCTL, RMAPI, vRPC, pRPC, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. +
libnvidia-vgpu.so +Library +3.1 MB +2023.01.xx +vmiop, RMAPI, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. Contains circular dependancies with nvidia-vgpu-mgr. +
nvidia-vgpu-vfio.ko +Driver +0.108 MB +2023.01.xx +Type 1 IOMMU, irqfd, ioeventfd, IOCTL, Mediated Core +Handles incremental memory mapping (non-page pinning per the standard vfio-pci driver). +
+

More Information

+
  1. Nvidia RISC-V Story
    2. +
    3. +
  3. Intel Graphics Programmer's Reference Manuals (PRM)
    4. +
  4. i915: Hardware Contexts (and some bits about batchbuffers)
    5. +
  5. i915: The Global GTT Part 1
    6. +
  6. i915: Aliasing PPGTT Part 2
    7. +
  7. i915: True PPGTT Part 3
    8. +
  8. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    9. +
  9. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    10. +
  10. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    11. +
  11. i915: An Introduction to Intel GVT-g (with new architecture)
+ + + + +
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GPU Support

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Abstract

+The following document will detail GPU Support for SR-IOV, SIOV, and VFIO-Mdev functionality.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

Overview

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Feature Matrix +
Hardware +Drivers +Virtual I/O Assistance Modes +Userspace +
Vendor +Architecture +Model +Libre Drivers +Blob Drivers +'Merged' Host+Guest Acceleration +Manufacturer Support +Mdev Support +SR-IOV Support +SIOV Support +mdev management CLI Support + Support +
Intel +6th Generation (Skylake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +7th Generation (Kaby Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +8th Generation (Coffee Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +9th Generation (Cannon Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +10th Generation (Ice Lake) + +i915 + +No +Yes (Legacy) +No +No +No +No +No +
Intel +11th Generation (Tiger Lake) +Xe* +i915 + +Yes +Yes + +Yes + +Yes +Yes +
Intel +12th Generation (Alder Lake) +Xe* +i915 + +Yes +Yes + +Yes +In Development +Yes +Yes +
Nvidia +Maxell +*(see exceptions below) +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Pascal +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Turing +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Ampere +A* +Nouveau (Development), OpenRM +RM +No (DisplayModeSelector) +Yes +Yes +Yes +In Development +Yes +Yes +
Nvidia +Ampere +RTX 30** +Nouveau (Development), OpenRM +RM +In Development +Yes +Yes +No +In Development +In Development +In Development +
Nvidia +Ada Lovelace +* +OpenRM + + +Yes +Yes +Yes +In Development +In Development +In Development +
Nvidia +Hopper +* +OpenRM + + +Yes +Yes +Yes +In Development + + +
AMD +Tonga +W7100 +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +

(patched) +

+		No +No +Yes +
AMD +Tonga +S71** +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +No +No +Yes +
AMD +Vega +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
AMD +Navi +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
+

Intel

+

This section will cover Mdev support on Intel GPUs. +

+

Hardware

+

GPUs supporting GVT-g (software based mediation)[1]: +

+
  • Intel HD Graphics 5500
    • +
  • Intel HD Graphics 6000
    • +
  • Intel HD Graphics 510
    • +
  • Intel HD Graphics 520
    • +
  • Intel HD Graphics 530
    • +
  • Intel HD Graphics 620
    • +
  • Intel HD Graphics 630
    • +
  • Intel UHD Graphics 620
    • +
  • Intel UHD Graphics 630
+

GPUs supporting SR-IOV (hardware based mediation): +

+
  • Intel Iris Xe Graphics [2][3]
    • +
  • Intel Iris Xe MAX Graphics
+

Drivers

+

Drivers with GVT-g support (6th - 9th gen): +

+ +

Drivers with SR-IOV support (11th gen+): +

+ +

Nvidia

+

This section will cover Mdev support on Nvidia GPUs. +

+

Hardware

+
  • All(?) Volta based GPUs (V-series)
    • +
  • All(?) Turing based GPUs (20-series)
    • +
  • All(?) Pascal based GPUs (10-series)
    • +
  • Most Maxwell based GPUs (9-series) with the following notable exceptions: +
    • GTX 970 (mixed FB regions)
      • +
    • Quadro M2000 (mixed FB regions)
      • +
    • Tesla M40 [4]
+
  • NVIDIA A100 HGX 80GB
    • +
  • NVIDIA A100 PCIe 80GB (SR-IOV: 20VF [5])
    • +
  • NVIDIA A100X
    • +
  • NVIDIA A100 HGX 40GB
    • +
  • NVIDIA A100 PCIe 40GB (SR-IOV: 16VF [6])
    • +
  • NVIDIA A40 (SR-IOV: 32VF [7])
    • +
  • NVIDIA A30 (SR-IOV: 8VF [8])
    • +
  • NVIDIA A30X
    • +
  • NVIDIA A16 (SR-IOV: 16VF [9])
    • +
  • NVIDIA A10 (SR-IOV: 32VF [10])
    • +
  • NVIDIA A2 (SR-IOV: 16VF [11])
    • +
  • NVIDIA RTX A6000
    • +
  • NVIDIA RTX A5000
    • +
  • Quadro RTX 8000 (SR-IOV: 24 VF [12])
    • +
  • Quadro RTX 8000 passive
    • +
  • Quadro RTX 6000 (SR-IOV: 24 VF [13])
    • +
  • Quadro RTX 6000 passive
    • +
  • Tesla V100
    • +
  • Tesla T4 (SR-IOV: 16VF [14])
    • +
  • Tesla P100
    • +
  • Tesla P40
    • +
  • Tesla P6
    • +
  • Tesla P4
    • +
  • Tesla M60
    • +
  • Tesla M10
    • +
  • Tesla M6
    • +
  • GRID K2 (Citrix XenServer and VMware ESXi only)
    • +
  • GRID K1 (Citrix XenServer and VMware ESXi only)
+

Drivers

+

The most widely used method of enabling Mdev functionality on Nvidia GPUs is via the use of Nvidia's proprietary driver package. +

Nvidia's proprietary Mdev driver supports both SR-IOV as well as software based mediation. The appropriate mode is chosen between the two methods based on hardware architecture. +

+

AMD

+

This section will cover Mdev support on AMD GPUs. +

+

Hardware

+

Supported GPUs: +

+
  • AMD FirePro S7150
    • +
  • AMD Radeon Pro V520 [15]
    • +
  • AMD FirePro W7100 [15]
+

Drivers

+

The open source GIM driver supports AMD Tonga architecture GPUs such as the FirePro S7150 & W7100. +

To make use of the MxGPU GIM driver on modern kernel versions you will require pull request 24. +

Virtualization driver support beyond AMD's Tonga architecture is unclear. +

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Glossary

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Revision as of 19:24, 27 March 2023 by Arthur (talk | contribs) (→‎Virtual GPU (vGPU))
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Definitions

+

This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +

If you have suggestions on how to improve the glossary you can contribute or join our community discussion thread to make suggestions. +

+

VFIO

+

Kernel.org defines VFIO or Virtual Function Input Output as "an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." [1]

+
A diagram depicting direct VFIO passthrough of a GPU adapter.
+

Mdev

+

Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: "an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." [2]

+
A diagram depicting VFIO Mediated Device interacting with two vGPU guests.
+

Virtual CPU (vCPU)

+

A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.

+

Virtual GPU (vGPU)

+

A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to EUs, or SMs) and/or a partition of the device's Video Random Access Memory (VRAM).

+

IVSHMEM

+

According to QEMU's GitHub repo: "The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR." [3]

+
A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.
+

KVMFR (Looking Glass)

+

looking-glass.io defines Looking Glass as: "an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse." [4]

+
A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.
+

NUMA Node

+

Infogalactic defines NUMA as: "Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." [5]

+
A diagram depicting Non-Uniform Memory Access (NUMA) nodes.
+

Application Binary Interface (ABI)

+

Infogalactic defines an ABI as "the interface between two program modules, one of which is often a library or operating system, at the level of machine code." [6]

+
A diagram contrasting API and ABI as well as their respective roles in software compatibility.
+

SR-IOV

+

docs.microsoft.com defines SR-IOV as "The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." [7]

+
A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.
+

GVT-g

+

wiki.archlinux.org defines Intel GVT-g as "a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." [8]

+
A diagram of Intel's GVT-g (Graphics Virtualization Technology g).
+

VirGL

+
A diagram depicting GPU instruction redirects to a single host graphics driver.

lwn.net defines Virgl as: "a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host." [9]

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Platform Hypervisor +Virtual GPU support +Memory Sharing APIs +IOMMU Groups support +PCI forwarding +Mdev Support +SR-IOV Support +SIOV Support +
KVM +Yes +IVSHMEM +Yes +Yes (via VFIO) +Yes +Yes +In Development +
Xen +Yes +Grant Tables +No +Yes (via xen-pciback) +No +Yes +Unknown +
NVMM +Unknown +Unknown +No +Unknown +No +Unknown +No +
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KVM

+

This section will cover existing support in KVM for VFIO-Mdev and ongoing issues with it's existing implementation. +

+

Missing Functionality

+

Nested SR-IOV. +

+

Xen

+

This section will cover efforts to support the Xen hypervisor with open device mediation software. +

XAPI docs for virtual GPUs can be read here. +

+

Mdev drivers outside Dom0

+

Xen Hyperlaunch aims to disaggregate Dom0's monolithic functions. This includes a discrete domain for device drivers. +

+

Missing Functionality

+

IOMMU Groups (discussions around extending or reworking Xen's IOMMU to include IOMMU Groups is ongoing). +

+

Additional Documentation

+

For additional documentation check the XenProject Wiki. +

+

NVMM

+

This section will cover NetBSD's NVMM. +

+

Missing Functionality

+

VFIO. +

+

Additional Documentation

+

For additional documentation read From Zero to NVMM. +

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Intel

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This page will document points of integration for virtualization in the Intel i915 driver. +

The i915 added SR-IOV feature enablement in this commit (April 26th 2022). Work is ongoing to upstream this code to i915 in the mainline Linux kernel. +

Driver API documentation can be read here: https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html +

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Introduction

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This page will provide introductory context on where to begin reading. It will aim to give you a sense of primitives or foundational concepts used for GPU Virtualization. +

+ + +

Terminology

+

To get started with basic terminology around IO Virtualization read the Glossary page. This will get you familiar with a few terms and concepts used in IO Virtualization documentation. +

+

Primitives

+

The primitives section will cover a few notes on the basics of virtualizing a GPU or IO device. +

+

PCI BAR

+

PCI-e devices such as GPUs are used for input and output to and from a computer system. This input and output occurs using TLPs or Transaction Layer Packets over the PCI-e packet network. The IO device is presented to the host operating system as BARs or Base Address Registers. +

+

GPU Drivers

+

GPUs need software to communicate from a host computer system to the device - this software is called a GPU Driver and it typically interacts with the device using MMIO or Memory Mapped IO. MMIO is a set of operations used to allow normal CPU instructions to address registers in RAM in order to communicate with the PCI-e device. In the context of virtualization these registers must be presented into the device in a way that the guest operating system expects. Typically this is accomplished using VFIO or Virtual Function IO. VFIO is used for many methods of virtualizing the device including discrete assignment of a physical device, or virtual (partitioned) device assignment created with or without hardware assistance. +

+

IOMMU

+

MMU or Memory Management Units handle hardware enforced access to memory paging in computer systems. In the context of virtualized MMIO (Memory Mapped Input Output) devices an MMU is required to hardware enforce access to virtual devices (a Memory Management Unit for Input Output is known as an IOMMU). In the case of VFIO, groups of IOMMU devices (IOMMU Groups) are used to control access to the device. These IOMMU Groups often represent individual devices or sub-devices (in the context of Unassisted Virtualization (VFIO-Mdev), Hardware-Assisted Virtualization (SR-IOV), or Hardware-Assisted Paravirtualization) which may be bound to a VFIO bus driver (such as vfio-pci) which results in a VFIO Group (unit of ownership). +

+

Virtualization vs. Paravirtualization

+

Virtualization provides support for unmodified guest software or drivers in the context of GPUs. +

Paravirtualization provides support for "enlightened" guests or modified software which is aware of virtualization. +

+

Unassisted vs. Assisted

+

Similar to virtualization on CPUs with tools like Xen, IO devices can be virtualized on different kinds of computer hardware. Some devices provide hardware virtualization assistance (such as HVM mode in Xen) and some do not (such as PV mode in Xen), as a result an appropriate mode should be used depending on the availability of assistance. +

+

Further Reading

+

This section will cover what you should read to obtain more information about virtualization. +

+

Virtualization Fundamentals

+

The Virtualization Fundamentals article provides links to some of the foundational work which underly modern virtualization industry and development today. If you'd like to understand both the theories on which virtualization builds as well as the history of industry you should read several articles here. Notable Popek and Goldberg Virtualization Requirements as well as Xen and the Art of Virtualization provide a great foundations-first approach to learning about virtualization. +

+

Virtual I/O Internals

+

The Virtual I/O Internals article provides a detailed look into the interface layers between IO driver internals, the hypervisor, and the guest OS. This is a great article to read if you'd like to better understand how virtual machines can interact with both discretely assigned devices as well as those which have been partitioned using software or firmware. +

+

GPU Driver Internals

+

The GPU Driver Internals article provides information on how GPU drivers are structured internally as well as how they achieve virtualization. This includes high level architecture, device initialization, as well as memory mapping, and scheduling. +

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LIME Is Mediated Emulation

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LIME Is Mediated Emulation is an in-development feature in which enables the execution of full performance Win64 binaries with full compatibility for all current and future software making use of the Windows ABI. An initial demo of this technology can be viewed here. +

+ + +

Design Goals

+

LIME aims to provide similar functionality to WINE Is Not Emulation, Valve's Proton / DXVK but with the use of graphics virtualization (vGPU/SR-IOV on consumer GPUs), a shared filesystem between host/guest, and KVM Frame Relay (high performance graphics buffer sharing via Inter-VM Shared Memory Device / IVSHMEM). +

Compared to WINE, and Proton the benefits of this approach are that Win64 binaries execute without the incompatibilities introduced in new games taking advantage of the latest version of DirectX, or when changes are introduced to the latest version of the Win64 ABI. +

This functionality is enabled via the use of GPU Virtual Machine (for consumer GPU Virtualization), VirtIO-FS (for host <-> guest filesystem sharing), Looking Glass (for host <-> guest shared frame buffer), and (for orchestration). +

+

Use-Cases

+

Win64 Subsystem

+

LIME's most immediate use case is around ABI compatibility with Win64 programs in environments without native support. +

A blog post detailing the problems which lead to this work can be read here. A summary of this post is traditional models for backwards compatibility with Application Binary Interfaces (ABIs) lock-in existing models for kernel/userland development and stagnate architectural innovation. On the other hand consumer oriented systems like those based on Darwin/XNU break backwards compatibility with user programs version to version of the system in order to introduce architectural improvements in the kernel / userland (for instance micro-service device drivers which may recover from faults at OS runtime). +

These two approaches might be considered two discretely separable models for software development 'enterprise' /'consumer' - LIME might then be considered a third approach which preserves the functions of both prior approaches (continual innovation afforded in the kernel-space and backwards compatibility with existing software libraries). +

ie: A method by which programs "import" a particular explicitly versioned ABI similar to how Docker provisions chroot resources like configuration files and support libraries, but extended to drivers, and the kernel. +

+

Win64 Orchestration

+

Because LIME necessarily provisions application data, program files, and NUMA-aware vCPU/vGPU resources (in the context of multi-GPU, multi-socket CPU systems) through for automatic execution by one or more VM guests LIME might provide an ideal architecture for orchestration of Win64 applications at scale. This could include execution of programs for game streaming in a server environment, or multiple applications in a single user environment for 'seamless-mode' execution of guest programs similar to that of QubesOS with hardware GPU acceleration added. +

+

Compatibility With Other ABIs

+

To solve the problems of 'ABI lock-in' discussed in the "Why Computers Suck" post it may be possible to port LIME support to multiple different guest operating systems allowing execution of any program with any ABI with near indistinguishable performance compared to native execution. +

+

Quality of Service (QoS)

+

VFIO-Mdev functionality like that used in GPU Virtual Machine (GVM) provides granular GPU resource allocation and load balancing functions similar to those seen in control groups (cgroups) as they are commonly applied today to RAM and CPU resources. In the context LIME VFIO-Mdev could be applied for load balancing of individual processes running in a virtualized state to ensure individual processes making use of the GPU cannot deny service to others on the system. +

+

Development Status

+

Development of this functionality is ongoing. Efforts to improve LIME are primarily focused on stabilization of shared filesystem functions. +

+

VirtIO-FS

+

VirtIO-FS provides shared filesystem functionality between host and guest using FUSE which is ideal for LIME, however in the context of Windows guests the C version of virtiofsd appears unstable (seen in virtio-win issue 550 [closed], 723 [closed], 724 [open]). Testing has been performed by members of the Open-IOV community which have shown initial signs of increased filesystem stability under continuous read/write loads using the Rust version of virtiofsd (virtiofsd-rs). +

While many programs can be stored in the VirtIO-FS shared directory some programs such as Steam don't want to install programs into the VirtIO-FS drive (seen as a secondary drive in Windows - in often as disk D:/ if no additional media is attached). This game installation behaviour (which drive the user may place their programs in) may not be in common with other game stores such as the Epic Games Store, or Good Old Games (GOG). +

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Looking Glass KVMFR

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Looking Glass is an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse. +

+

Looking Glass Memory Protocol (LGMP)

+

LGMP is an Inter-VM Shared Memory Device (IVHSMEM) based memory sharing protocol for the KVM Frame Relay use-case (sharing of MMIO memory for use by GPU drivers between host and guest). +

+

Xen Support

+

It may be possible to port the Looking Glass Memory Protocol to Xen by substituting the use of the Grant Table memory sharing primitive in place of the IVSHMEM memory sharing primitive. +

+
A diagram depicting how Looking Glass memory device may be redirected over the network via Remote Direct Memory Access (RDMA).
+

Telescope

+

The LGMP protocol may also be extended over a high bandwidth network using the Telescope Looking Glass Proxy. +

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Mdev-GPU

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This page makes use of terms that are defined in the Open-IOV Glossary. If you're curious what a given term means you can check there for a definition. +


+

This page will be used to document the Mdev-GPU API as well as provide an overview of the internals of the Mdev-GPU package. +

Mdev-GPU's source code can be found here. +

+Module docs can be found here.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Compilation

+

Compiling Mdev-GPU from source is very simple however it can take a long time to complete (10 minutes for existing sources). +

If you'd like to compile Mdev-GPU yourself you can do so by cloning the repo and running the following two commands from within the repository directory: +

curl -sSL https://get.haskellstack.org/ | sh +

stack install +

These commands will generate all binaries provided by Mdev-GPU under the path ~/.local/bin/. +

If you would prefer not to wait for the program to compile you can find pre-compiled x86_64 binaries under the Releases section of the repository on GitHub. +

+

Installation

+

The binaries compiled on your local machine by Stack in the ~/.local/bin/ path or downloaded from Releases on GitHub should be copied to /usr/bin/. This can be accomplished both via install script (currently testing in ) or via management layer-agnostic package. +

+

Mdev-GPU Configuration

+

The Mdev-GPU repository provides Systemd service and example configurations for Mdev-CLI in the /etc/ folder. On installation the directories & files contained in the repository's /etc/ folder should be copied to the absolute path /etc/ on the user's computer. +

+

Systemd

+

GVM/Mdev-GPU exposes several of it's functions as Systemd services. +

As of the 0.1.0.0 release the following Systemd services are available: +

+
  • mdev-post.service
+
mdev-post.service
+

As the name would suggest mdev-post.service posts the GPU(s) in a state where they are ready to be virtualized. When the service is invoked the mdev-cli util registers Mdev callbacks and supported mediated device (Mdev) types with the Mediated Core according to the user's specified configuration at /etc/gvm/mdev-gpu/generate-vgpu-types.yaml. If you'd like to place your configuration file elsewhere and still have your configuration invoked on boot you can edit the systemd service ExecStart= line to specify an alternative path. +

+

Mdev-CLI

+

Configuration for Mdev-GPU can be found in the path /etc/gvm/mdev-gpu/. This path will by default contain several vendor-specific folders which may include configuration examples for various devices/architectures as well as the file generate-vgpu-types.yaml which you can configure to specify your desired Virtual GPU (vGPU) / VFIO-Mdev topologies as they are presented in the sysfsdev mdev_bus path and as seen by tools such as mdevctl. Once you have configured the available types your liking you can refresh the supported types registered with the Mediated Core by rebooting your machine or reloading the vendor driver kernel module then restarting mdev-post.service or by invoking mdev-cli. +


+The available yaml properties which may be specified in /etc/gvm/mdev-gpu/generate-vgpu-types.yaml are shown below. Note that fields with the [required] tag must be specified in the yaml file whereas fields with the [optional] tag may be omitted from configuration if you would prefer to rely upon default parameters instead. +

+
num
+

[required] +

num refers to the Mediated Device (Mdev) type number. This value specifies the profile's numerical identifier in the sysfsdev mdev_bus path. +

+
vDevId
+

[optional] +

The vGPU (Virtual GPU) PCI Device ID which should be presented to the guest. +

+
pDevId
+

[optional] +

The pGPU (Physical GPU) PCI Device ID which should be presented to the host. +

+
name
+

[optional] +

The GPU name presented to the guest. +

+
gpuClass
+

[optional] +

The class of GPU to use. +

available strings: +

"Compute" +

"Graphics" +

+
maxInstances
+

[required] +

maxInstances refers to the maximum number of instances available of any given Mediated Device (Mdev) profile. This number can be configured arbitrarily however it should ideally not be set to a value which allows for fbLen/fbRes values that allow a number of Mdev devices to be created which would exceed your device's available VRAM. +

+
virtDisplay
+

[optional] +

virtDisplay controls the topologies of virtual displays. virtDisplay exposes the following user configurable properties: +

+
numHeads
+

[optional] +

Number of heads [virtual monitors] available for each Mediated Device (Mdev). +

+
maxResX
+

[optional] +

Maximum width of the mediated display. +

+
maxResY
+

[optional] +

Maximum height of the mediated display. +

+
frlConfig
+

[optional] +

Frame rate limiter for the mediated display. +

+
frlEnable
+

[optional] +

Do we enable frame rate limiting or not? +

+
ecc
+

[optional] +

ecc refers to if error correcting memory should be used. +

+
fbLen
+

[required] +

fbLen is the framebuffer length (in megabytes). +

+
fbRes
+

[required] +

fbRes is the framebuffer reserved by the hypervisor (in megabytes). In most circumstances this value should scale to around 1/7th the size of your chosen fbLen value. +

+
mapVideoSize
+

[optional] +

Mappable video size in MBs, 24 by default. +

+
encCap
+

[optional] +

Percentage we use the NvEnc hardware. +

+
bar1Len
+

[optional] +

bar1Len refers to the size of the Base Address Registers for BAR1 (MSI) as presented by the VFIO File Descriptor. +

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Merged Drivers

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The following page will provide specifications and details on the current state of host DRM + VFIO-Mdev drivers in support of various vendors. +

In the context of this page the term "Merged Driver" refers to drivers which allow simultaneous acceleration of the host using a device's PF (Physical Function) and acceleration of guests using one or more VFs (Virtual Functions) created using the same device. +

+Merged functionality is currently supported for drivers which both make use of VFIO-Mdev and SR-IOV functionality depending on the vendor and driver implementation.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel i915

+
Intel's slides mention the ability to accelerate up to '8 VMs plus DOM0'. Source: https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf
+

Intel currently supports host DRM and VFIO-Mdev/SR-IOV functionality in it's current i915 driver sources (VFIO-Mdev/GVT-g) and upstreaming i915 driver sources (VFIO-Mdev/SR-IOV). +

+

Known Issues

+
  1. SR-IOV functionality is undocumented in the i915 driver API documentation.
    Confirmed affected versions: *
    A diagram depicting i915's shared host + VFIO-Mdev driver model.
+

Resolved Issues

+
  1. Multiplexing functionality requires use modified KVM and Xen hypervisors (KVMGT/XenGT).
    Confirmed affected versions:     current i915 driver sources (GVT-g)
    Fixed in:     upstreaming i915 driver sources (SR-IOV)
+

Nvidia

+

Known Issues

+
  1. Power management on laptops running mediated graphics functionality may causes graphical errors when not plugged in to AC power.
    Confirmed affected versions: 460.32.01, 460.73.04
    Possible mitigation: lore.kernel.org: "vfio/pci: Change the PF power state to D0 before enabling VFs"
    2. +
  2. VFIO-vmalloc errors may occur as a result of page collisions between host & guest on GPUs with smaller VRAM frame buffer sizes.
    Confirmed affected versions: 460.32.01, 460.73.04
    3. +
  3. Mdev service daemons may crash or load incorrectly requiring a service restart or reboot during host runtime.
    Confirmed affected versions: 460.32.01, 460.73.04, 510.xx.xx
    4. +
  4. Guest drivers fail to initialize correctly when VFIO-Mdev devices are mixed with some VFIO passthrough'd USB hubs.
    Confirmed affected versions: 460.73.01
+

Resolved Issues

+
  1. Upon executing QEMU mdev device initialization for a second Mdev an IOMMU group binding error occurs in QEMU preventing the device from being brought up.
    Confirmed affected versions: 460.32.01, 460.73.04
    Fixed in: 510.xx.xx
+

Module Configuration

+

Depending on your use-case the use of some additional parameters when booting the system may be helpful. +

Here is a list of some parameters which may be used when loading the module via GRUB or Systemd-boot. +

+ + + + + + + + + + + + + +
Module Parameters +
Parameter +Description +Side-Effects +
cudahost=1 +Allows use of CUDA on the host system. +Windows guests may fail. +
nvidia.vgpukvm=0 +Disables GPU virtualization on the host. + +
+

AMDGPU

+

At this time AMDGPU does not currently support VFIO-Mdev functionality. It may be possible to incorporate Mdev Mode mediated device support similar to those functions in nvidia.ko and i915.ko in the Linux kernel's AMDGPU driver sources to produce a driver suitable for merged host+guest DRM for use with AMD GPU devices. +

+

Known Issues

+
  1. Host DRM does not work alongside guest VFIO-Mdev.
    Confirmed affected versions: *
    2. +
  2. The amdgpu kernel module doesn't contain hooks for guest signalling via irqfd & ioeventfd used for VFIO-mdev callbacks.
    Confirmed affected versions: *
+ + + + +
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization.  +

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OpenRM

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OpenRM refers to the open sourcing of the NVIDIA kernel module for Linux, specifically the RM Core or the internal resource manager. +

+Through the open sourced code (located here) we have been able to deduce 7 top level APIs that are being exposed to the Linux developers.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Interaction With OpenRM

+

All of OpenRM is a high scale object oriented abstraction layer for the GPU, all resources are internally classes which have control definitions (methods) on how you can use them. These classes can also represent physical resources or engines. +

+

Alloc (Client)

+

This is analogous to calling an object constructor in a higher level programming language, such as C#. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
    2. +
  2. hObjectParent - Parent of the resource we are allocating.
    3. +
  3. hObjectNew - New object to allocate.
    4. +
  4. hClass - Class of the object we are dealing with.
    5. +
  5. pAllocParams - Pointer to values passed into the constructor call.
    6. +
  6. status - Status of the constructor call (did it succeed or fail)
+

Alloc Memory 64

+

This creates a CPU's mapping to a resource. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
    2. +
  2. hObjectParent - Parent of the resource we create the CPU mapping to.
    3. +
  3. hObjectNew - Mapping object resource id.
    4. +
  4. hClass - Class of the mapped object.
    5. +
  5. flags - Flags to use on the mapped object.
    6. +
  6. pMemory - pointer for the memory to map.
    7. +
  7. pLimit - Edge of memory map.
    8. +
  8. status - Status of the constructor call.
+

NOTE: Seems to be deprecated. +

+

Control

+

This is a control command which is analogous to calling a method on a class. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
    2. +
  2. hObject - Object id.
    3. +
  3. cmd - Method to call.
    4. +
  4. params - Parameters into this method.
    5. +
  5. paramsSize - Size of the params.
    6. +
  6. status - Status of the control call.
+

NOTE: The control will overwrite the object we pass in over the params pointer. +

+

Dup Object

+

Duplicates the object, or clones the object, which is a deep copy. This procedure can be used across processes in order to produce shared memory. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
    2. +
  2. hParent - Parent of the object.
    3. +
  3. hObject - Object destination for duplicating.
    4. +
  4. hClientSrc - Client source id.
    5. +
  5. hObjectSrc - Object source.
    6. +
  6. flags - Flags to use.
    7. +
  7. status - Status of the duplication.
+

Free

+

Frees an object from the object tree. +

The data for this call requires the following components: +

+
  1. hRoot - Client Id.
    2. +
  2. hObjectParent - Parent of the object.
    3. +
  3. hObjectOld - Object to call the destructor on.
    4. +
  4. status - Status of the free.
+

Vid Heap Control

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Map Memory

+

This seems to be the same as alloc memory but seems to be used more often. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device id.
    3. +
  3. hMemory - Memory resource.
    4. +
  4. offset - Offset of the memory.
    5. +
  5. length - Length of the memory.
    6. +
  6. pLinearAddress - Pointer for returned address.
    7. +
  7. status - Status of the map memory.
    8. +
  8. flags - Flags to use.
+

Unmap Memory

+

This unmaps the CPU memory mapping from the resource. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hMemory - Memory Id.
    4. +
  4. pLinearAddress - pointer to virtual address.
    5. +
  5. status - Status of the unmap command.
    6. +
  6. flags - Flags to use.
+

Alloc Context DMA 2

+

Allocates a context for DMA. +

The data for this call requires the following components: +

+
  1. hObjectParent - Object parent.
    2. +
  2. hSubDevice - Sub device to allocate on.
    3. +
  3. hObjectNew - Context id.
    4. +
  4. hClass - Type of class.
    5. +
  5. flags - Flags to use.
    6. +
  6. selector - UNKNOWN.
    7. +
  7. hMemory - Handle for Memory resource to DMA map.
    8. +
  8. offset - Offset for the DMA mapping.
    9. +
  9. limit - Limit of the DMA map.
    10. +
  10. status - Status of the allocation.
+

NOTE: Seems to be deprecated. +

+

Map Memory DMA

+

Map a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hDma - DMA Id.
    4. +
  4. hMemory - Memory Id.
    5. +
  5. offset - Offset of the region.
    6. +
  6. limit - Limit of the region.
    7. +
  7. flags - flags to use.
    8. +
  8. dmaOffset - Offset of the mapping.
    9. +
  9. status - Status of the map Memory DMA.
+

Un-map Memory DMA

+

Unmaps a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hDevice - Device Id.
    3. +
  3. hDma - DMA handle.
    4. +
  4. hMemory - Memory handle.
    5. +
  5. flags - Flags to use.
    6. +
  6. dmaOffset - DMA Offset to unmap.
    7. +
  7. status - Status of the unmap Memory DMA.
+

Bind Context DMA

+

Binds a context for DMA interaction to a channel. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hChannel - Channel Id.
    3. +
  3. hCtxDma - Context for DMA Id.
    4. +
  4. status - Status of the bind context DMA.
+

NOTE: Seems to be deprecated. +

+

Share

+

Sharing of a resource between multiple clients. +

TODO: Understand this sharing more. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
    2. +
  2. hObject - Resource Id.
    3. +
  3. sharePolicy - Share policy.
    4. +
  4. status - Status of sharing.
+

Add VBlank Callback

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Engines

+

There are engines which internally act as classes inside the OpenRM driver. +

These classes have a few key components that make them unique. +

+

Table of Engines

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Engines +
Engine +Description +
Invalid +Does not exist. +
Software +Abstraction layer for software processes inside the OS Software. +
GPU +Interaction layer with the GPU. +
Falcon +Interaction with the Falcon on the GPU. +
Master Control +Unknown. +
Kernel Master Control +Interaction with the PMC.[1] +
Private Ring +Interaction with a private messaging ring. +
Software Interrupt +Interaction with software interrupts. +
Memory System +Interaction with the memory system. +
Kernel Memory System +Interaction with the kernel memory system. +
Memory Manager +Interaction with the memory management system. +
FBFlcn +Interaction with the FBFlcn subsystem. +
TMR +Interaction with the TMR on specific chips. +
DMA +Interaction with a GPU's DMA access. +
Kernel FIFO +First in First out queue in the GPU driver. +
FIFO +Interaction with a generic FIFO. +
OS +Interaction with the OS. +
BUS +PCI Bus interaction +
Kernel BUS +Internal module BUS. +
INFOROM +Interaction with the INFOROM Region on the GPU. +
PERF +Unknown. +
Kernel PERF +Unknown. +
BIF +Unknown. +
Kernel BIF +Unknown. +
SF +Unknown. +
GPIO +Interaction with GPIO. +
CLK +Clock manager system. +
Kernel Display +Kernel Display system. +
DISP +Display system. +
DPU +Data Processing Unit. +
+ +
+ +
+ + + + +
+
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vGPU_Unlock is a project created by Jonathan Johansson, available on GitHub. +

The project is designed to allow Nvidia's enterprise GPU virtualization technology to run on consumer Nvidia graphics cards (ex: GeForce GTX series). +

Since its inception, there have been several forks of the project that are more up to date and more performant (ex: Rust version). +

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The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
    • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
    2. +
  2. mdpy-fb.c
    3. +
  3. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
    2. +
  2. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
    3. +
  3. [2017] Scalable I/O Virtualization by Kevin Tian
    4. +
  4. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
    5. +
  5. Scalable I/O Virtualization Revision 1.0
    6. +
  6. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
    7. +
  7. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
    8. +
  8. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
    9. +
  9. IOCTL
    10. +
  10. eventfd - root/virt/kvm/eventfd.c
    11. +
  11. (kernel diff:: KVM: irqfd)
    12. +
  12. (kernel diff:: KVM: add ioeventfd support)
    13. +
  13. KVM irqfd & ioeventfd
    14. +
  14. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
    15. +
  15. VFIO Mediated Devices
    16. +
  16. IOMMU Aware Mediated Device
    17. +
  17. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
    18. +
  18. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
    19. +
  19. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
    20. +
  20. Auxiliary Bus
    21. +
  21. Shared Virtual Addressing
    22. +
  22. vfio.blogspot.com
    23. +
  23. XenGT by Kevin Tian
    24. +
  24. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
    25. +
  25. PCI SIG I/O Virtualization
    26. +
  26. VMGL by the University of Toronto Computer Science Department
    27. +
  27. Kepler VGX Hypervisor
    28. +
  28. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
    29. +
  29. DMA-Mapping.txt (Dynamic DMA Mapping)
    30. +
  30. KVM MMU Virtualization by Xiao Guangrong
    31. +
  31. OSDEV: PCI
    32. +
  32. Down to the TLP: How PCI express devices talk (Part I)
    33. +
  33. Down to the TLP: How PCI express devices talk (Part II)
    34. +
  34. Intel ACRN: Enabling SR-IOV Virtualization
    35. +
  35. Kernel.org sysfs-bus-pci
    36. +
  36. Linux Kernel Labs: Memory Mapping
    37. +
  37. Inside Windows Page Frame Number (PFN) - Part 1
    38. +
  38. Direct Rendering Infrastructure (DRI)
    39. +
  39. DRI User Guide
    40. +
  40. Linux Kernel Labs: IO Virtualization
    41. +
  41. Gallium3D: Main Page
    42. +
  42. Gallium3D Wiki
    43. +
  43. Gallium3D talk from XDS 2007
    44. +
  44. Memory Management High Level Design (ARCN)
    45. +
  45. Block Architecture Diagrams for Geforce series
    46. +
  46. Block diagrams for 40 series instruction format
    47. +
  47. PCI Configuration Space
    48. +
  48. GPU virtual memory in WDDM 2.0
    49. +
  49. Intel Graphics Programmer's Reference Manuals (PRM)
    50. +
  50. i915: Hardware Contexts (and some bits about batchbuffers)
    51. +
  51. i915: The Global GTT Part 1
    52. +
  52. i915: Aliasing PPGTT Part 2
    53. +
  53. i915: True PPGTT Part 3
    54. +
  54. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
    55. +
  55. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
    56. +
  56. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
    57. +
  57. A deep dive into QEMU: PCI slave devices
    58. +
  58. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
    59. +
  59. IOMMU Introduction
    60. +
  60. Arch Wiki: Intel Graphics
    61. +
  61. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
    62. +
  62. Kernel.org: vfio iommu type1: Add support for mediated devices
    63. +
  63. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
    64. +
  64. More Shadow Walker: The Progression of TLB-Splitting on x86
    65. +
  65. MMU Virtualization Via Intel EPT: Technical Details
    66. +
  66. Alex Williamson Github: VFIO Development (tree next)
    67. +
  67. GPU PMU: performance monitoring with perf event
    68. +
  68. Remote Procedure Call (RPC)
    69. +
  69. Virtual Open Systems: API Remoting
    70. +
  70. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
    71. +
  71. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
    72. +
  72. docs.kernel.org: DRM Memory Management
    73. +
  73. docs.kernel.org: PCI Bus Subsystem
    74. +
  74. openglbook.com: What is OpenGL?
    75. +
  75. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
    76. +
  76. Dynamic Mediation for Live Migration VFIO-PCI
    77. +
  77. DRM Management Via CGroups
    78. +
  78. DRM: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
+
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This following page is intended to index and summarize information related to the fundamentals of virtualization of computer systems.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Popek and Goldberg Virtualization Requirements

+

The Popek and Goldberg virtualization requirements are a set of conditions sufficient for a computer architecture to support system virtualization efficiently. They were introduced by Gerald J. Popek and Robert P. Goldberg in their 1974 article "Formal Requirements for Virtualizable Third Generation Architectures". Even though the requirements are derived under simplifying assumptions, they still represent a convenient way of determining whether a computer architecture supports efficient virtualization and provide guidelines for the design of virtualized computer architectures. +

+

Goldberg Survey of Virtual Machine Research

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The complete instruction-by-instruction simulation of one computer system on a different system is a well-known computing technique. It is often used for software development when a hardware base is being altered. For example, if a programmer is developing software for some new special purpose (e.g., aerospace) computer X which is under construction and as yet unavailable, he will likely begin by writing a simulator for that computer on some available general-purpose machine G. The simulator will provide a detailed simulation of the special-purpose environment X, including its processor, memory, and I/O devices. Except for possible timing dependencies, programs which run on the “simulated machine X” can later run on the “real machine X” (when it is finally built and checked out) with identical effect. The programs running on X can be arbitrary — including code to exercise simulated I/O devices, move data and instructions anywhere in simulated memory, or execute any instruction of the simulated machine. The simulator provides a layer of software filtering which protects the resources of the machine G from being misused by programs on X. +

+

Microkernels Meet Recursive Virtual Machines

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This paper describes a novel approach to providing mod- ular and extensible operating system functionality and en- capsulated environments based on a synthesis of micro- kernel and virtual machine concepts. We have developed a software-based virtualizable architecture called Fluke that allows recursive virtual machines (virtual machines running on other virtual machines) to be implemented ef- ficiently by a microkernel running on generic hardware. A complete virtual machine interface is provided at each level; efficiency derives from needing to implement only new functionality at each level. This infrastructure allows common OS functionality, such as process management, demand paging, fault tolerance, and debugging support, to be provided by cleanly modularized, independent, stack- able virtual machine monitors, implemented as user pro- cesses. It can also provide uncommon or unique OS fea- tures, including the above features specialized for particu- lar applications’ needs, virtual machines transparently dis- tributed cross-node, or security monitors that allow arbi- trary untrusted binaries to be executed safely. Our proto- type implementation of this model indicates that it is prac- tical to modularize operating systems this way. Some types of virtual machine layers impose almost no overhead at all, while others impose some overhead (typically 0–35%), but only on certain classes of applications. +

+

A Comparison of Software and Hardware Techniques for x86 Virtualization

+

Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMwareR Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization. We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution. We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization. +

+

Virtualizing I/O Devices on VMware Workstation’s Hosted Virtual Machine Monitor

+

Virtual machines were developed by IBM in the 1960’s to provide concurrent, interactive access to a mainframe computer. Each virtual machine is a replica of the underlying physical machine and users are given the illusion of running directly on the physical machine. Virtual machines also provide benefits like isolation and resource sharing, and the ability to run multiple flavors and configurations of operating systems. VMware tmWorkstation brings such mainframe-class virtual machine technology to PC-based desktop and workstation computers. This paper focuses on VMware Workstation’s approach to virtualizing I/O devices. PCs have a staggering variety of hardware, and are usually pre-installed with an operating system. Instead of replacing the pre-installed OS, VMware Workstation uses it to host a user-level application (VMApp) component, as well as to schedule a privileged virtual machine monitor (VMM) component. The VMM directly provides high-performance CPU virtualization while the VMApp uses the host OS to virtualize I/O devices and shield the VMM from the variety of devices. A crucial question is whether virtualizing devices via such a hosted architecture can meet the performance required of high throughput, low latency devices. To this end, this paper studies the virtualization and performance of an Ethernet adapter on VMware Workstation. Results indicate that with optimizations, VMware Workstation’s hosted virtualization architecture can match native I/O throughput on standard PCs. Although a straightforward hosted implementation is CPU-limited due to virtualization overhead on a 733 MHz PentiumR III system on a 100 Mb/s Ethernet, a series of optimizations targeted at reducing CPU utilization allows the system to match native network throughput. Further optimizations are discussed both within and outside a hosted architecture. +

+

Dynamic binary translation and optimization

+

We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach o�ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime pro�le information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system, and their impact on �nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage. Keywords| dynamic compilation, binary translation, dynamic optimization, just-in-time compilation, adaptive code generation, pro�le-directed feedback, instruction-level parallelism, very long instruction word architectures, virtual machines, instruction set architectures, instruction set layering. +

+

Xen and the Art of Virtualization

+

Numerous systems have been designed which use virtualization to subdivide the ample resources of a modern computer. Some require specialized hardware, or cannot support commodity operating systems. Some target 100% binary compatibility at the expense of performance. Others sacrifice security or functionality for speed. Few offer resource isolation or performance guarantees; most provide only best-effort provisioning, risking denial of service. This paper presents Xen, an x86 virtual machine monitor which allows multiple commodity operating systemsto share conventional hardware in a safe and resource managed fashion, but without sacrificing either performance or functionality. This is achieved by providing an idealized virtual machine abstraction to which operating systems such as Linux, BSD and Windows XP, can be ported with minimal effort. Our design is targeted at hosting up to 100 virtual machine instances simultaneously on a modern server. The virtualization approach taken by Xen is extremely efficient: we allow operating systems such as Linux and Windows XP to be hosted simultaneously for a negligible performance overhead — at most a few percent compared with the unvirtualized case. We considerably outperform competing commercial and freely available solutions in a range of microbenchmarks and system-wide tests. +

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b/wiki/open-iov.org/skins/Vector/resources/skins.vector.styles.legacy/images/user-avatar.svg?b7f58 @@ -0,0 +1,7 @@ + + + + + + + diff --git a/wiki/vGPU-IO-Integration-Guide.md b/wiki/vGPU-IO-Integration-Guide.md new file mode 100644 index 0000000..6e248c9 --- /dev/null +++ b/wiki/vGPU-IO-Integration-Guide.md @@ -0,0 +1,480 @@ +# vGPU-IO Integration Guide + +## Overview +This guide covers implementing a Linux kernel driver for vGPU-IO using the GSP 570.144W firmware RPC interface. + +## Architecture + +``` +┌─────────────────────────────────────────────────────────────┐ +│ vGPU-IO Kernel Driver │ +├─────────────────────────────────────────────────────────────┤ +│ gsp_core.c │ gsp_rpc.c │ gsp_vf.c │ +│ - Device probe │ - RPC client │ - VF lifecycle │ +│ - BAR mapping │ - Doorbell │ - Migration │ +│ - IRQ/MSI-X │ - Completion │ - WPR/BAR integration │ +├─────────────────────────────────────────────────────────────┤ +│ GSP Firmware (570.144W) │ +│ Primary Dispatcher (0x057A1AC0) │ Secondary (0x04ED39DC) │ +│ BAR Handler (0x04CB8188) │ WPR Handlers │ +│ Migration (0x04179ED8/0x04179FBC)│ SCHED/ALLOC/PIN │ +└─────────────────────────────────────────────────────────────┘ +``` + +## Module Structure + +``` +drivers/gpu/nvidia/gsp/ +├── gsp.h # Core definitions +├── gsp_rpc.h # RPC message formats +├── gsp_vf.h # VF definitions +├── gsp_bar.h # BAR emulation +├── gsp_wpr.h # WPR management +├── gsp_migration.h # Migration protocol +├── gsp_core.c # Probe/remove, BAR/IRQ +├── gsp_rpc.c # RPC client implementation +├── gsp_vf.c # VF create/destroy +├── gsp_bar.c # BAR trap handler +├── gsp_wpr.c # WPR protect/unprotect +├── gsp_migration.c # Live migration +└── gsp_debugfs.c # Debug interface +``` + +## Core Data Structures + +### GSP Device +```c +struct gsp_device { + struct pci_dev *pdev; + void __iomem *bar0; // PCIe BAR0 mapping + void __iomem *bar1; // PCIe BAR1 (GSP FW) + struct gsp_firmware *fw; // Firmware image + struct gsp_rpc_client *rpc; // RPC client + struct mutex vf_lock; + struct idr vf_idr; // VF ID allocator + struct list_head vf_list; + struct gsp_debugfs *debugfs; + spinlock_t doorbell_lock; + uint32_t doorbell_seq; +}; +``` + +### VF (Virtual Function) +```c +struct gsp_vf { + struct gsp_device *gsp; + uint32_t id; // VF ID (1-7) + struct kref ref; + struct mutex lock; + mig_state_t mig_state; + struct gsp_migration *migration; + uint64_t bar1_offset; // BAR1 aperture offset + uint64_t bar1_size; // BAR1 aperture size + uint64_t pt_base; // Page table base + uint64_t pt_size; // Page table size + uint64_t cmd_base; // Command buffer base + uint64_t cmd_size; // Command buffer size + struct gsp_wpr_region *wpr_regions; + struct list_head wpr_list; + struct gsp_bar_state bar_state; + atomic_t refcount; + bool active; +}; +``` + +## Initialization Sequence + +### 1. PCI Probe +```c +static int gsp_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + struct gsp_device *gsp; + int ret; + + gsp = devm_kzalloc(&pdev->dev, sizeof(*gsp), GFP_KERNEL); + gsp->pdev = pdev; + pci_set_drvdata(pdev, gsp); + + // Enable PCI device + ret = pcim_enable_device(pdev); + if (ret) return ret; + + // Map BARs + gsp->bar0 = pcim_iomap(pdev, 0, 0); + gsp->bar1 = pcim_iomap(pdev, 1, 0); + if (!gsp->bar0 || !gsp->bar1) return -ENOMEM; + + // Load firmware + ret = gsp_firmware_load(gsp, "gsp-570.144.fwimage.bin"); + if (ret) return ret; + + // Initialize RPC client + gsp->rpc = gsp_rpc_client_init(gsp); + if (IS_ERR(gsp->rpc)) return PTR_ERR(gsp->rpc); + + // Setup IRQ/MSI-X + ret = gsp_setup_irq(gsp); + if (ret) return ret; + + // Initialize debugfs + gsp_debugfs_init(gsp); + + return 0; +} +``` + +### 2. Firmware Loading +```c +int gsp_firmware_load(struct gsp_device *gsp, const char *name) { + const struct firmware *fw; + int ret; + + ret = request_firmware(&fw, name, &gsp->pdev->dev); + if (ret) return ret; + + // Verify MD5: 13ce12a392a31eeb79a2e6ebd3a4a93a + if (!gsp_firmware_verify(fw->data, fw->size)) { + release_firmware(fw); + return -EINVAL; + } + + // Load to GSP memory (via BAR1) + ret = gsp_firmware_upload(gsp, fw->data, fw->size); + release_firmware(fw); + + return ret; +} +``` + +### 3. GSP Boot +```c +int gsp_boot(struct gsp_device *gsp) { + // 1. Reset GSP + writel(1, gsp->bar0 + GSP_RESET_REG); + msleep(10); + writel(0, gsp->bar0 + GSP_RESET_REG); + + // 2. Wait for entry point (0x04009000) to signal ready + ret = gsp_wait_for_ready(gsp, 5000); // 5s timeout + if (ret) return ret; + + // 3. Initialize RPC dispatchers + ret = gsp_rpc_init_dispatchers(gsp); + if (ret) return ret; + + return 0; +} +``` + +## RPC Client Implementation + +### Doorbell Mechanism +```c +#define GSP_DOORBELL_OFFSET 0x1000 +#define GSP_MSG_RING_SIZE 256 +#define GSP_MSG_MAX_SIZE 256 + +struct gsp_rpc_client { + struct gsp_device *gsp; + struct mutex lock; + uint32_t seq; + wait_queue_head_t wq; + struct gsp_msg_ring *ring; + struct completion *pending[GSP_MAX_PENDING]; +}; + +static int gsp_rpc_send_sync(struct gsp_rpc_client *rpc, + uint32_t rpc_type, + void *payload, size_t payload_size, + void *response, size_t *response_size) { + struct gsp_msg msg = { + .hdr = { + .magic = 0x47535052, + .version = 1, + .rpc_type = rpc_type, + .sequence = atomic_inc_return(&rpc->seq), + .timestamp_ns = ktime_get_ns(), + .payload_size = payload_size, + .flags = MSG_SYNC, + } + }; + + struct completion done; + init_completion(&done); + + mutex_lock(&rpc->lock); + rpc->pending[msg.hdr.sequence % GSP_MAX_PENDING] = &done; + + // Copy message to ring buffer + memcpy(msg.hdr.payload, payload, payload_size); + gsp_ring_write(rpc->ring, &msg, GSP_MSG_MAX_SIZE); + + // Ring doorbell + writel(1, rpc->gsp->bar0 + GSP_DOORBELL_OFFSET); + + mutex_unlock(&rpc->lock); + + // Wait for completion + if (!wait_for_completion_timeout(&done, msecs_to_jiffies(5000))) + return -ETIMEDOUT; + + // Copy response + if (response && response_size) { + *response_size = min(*response_size, done.payload_size); + memcpy(response, done.payload, *response_size); + } + + return done.status; +} +``` + +### Completion Handler (ISR) +```c +static irqreturn_t gsp_isr(int irq, void *data) { + struct gsp_device *gsp = data; + struct gsp_msg msg; + + while (gsp_ring_read(gsp->rpc->ring, &msg)) { + if (msg.hdr.flags & MSG_SYNC) { + struct completion *done = + gsp->rpc->pending[msg.hdr.sequence % GSP_MAX_PENDING]; + if (done) { + done->status = msg.payload.status; + done->payload_size = msg.hdr.payload_size; + memcpy(done->payload, msg.payload.data, msg.hdr.payload_size); + complete(done); + } + } else { + // Async notification + gsp_handle_notification(gsp, &msg); + } + } + + return IRQ_HANDLED; +} +``` + +## VF Lifecycle + +### Create VF +```c +int gsp_vf_create(struct gsp_device *gsp, uint32_t vf_id, + const struct gsp_vf_config *config) { + struct gsp_vf *vf; + int ret; + + mutex_lock(&gsp->vf_lock); + + if (idr_alloc(&gsp->vf_idr, NULL, vf_id, vf_id + 1, GFP_KERNEL) < 0) { + ret = -EBUSY; + goto unlock; + } + + vf = kzalloc(sizeof(*vf), GFP_KERNEL); + vf->gsp = gsp; + vf->id = vf_id; + kref_init(&vf->ref); + mutex_init(&vf->lock); + INIT_LIST_HEAD(&vf->wpr_list); + + // Configure VF resources + vf->bar1_offset = config->bar1_offset; + vf->bar1_size = config->bar1_size; + vf->pt_base = config->pt_base; + vf->pt_size = config->pt_size; + vf->cmd_base = config->cmd_base; + vf->cmd_size = config->cmd_size; + + // Initialize WPR for VF + ret = gsp_vf_wpr_init(vf); + if (ret) goto err_wpr; + + // Initialize BAR for VF + ret = gsp_vf_bar_init(vf); + if (ret) goto err_bar; + + list_add(&vf->list, &gsp->vf_list); + vf->active = true; + + mutex_unlock(&gsp->vf_lock); + return 0; + +err_bar: + gsp_vf_wpr_fini(vf); +err_wpr: + idr_remove(&gsp->vf_idr, vf_id); + kfree(vf); +unlock: + mutex_unlock(&gsp->vf_lock); + return ret; +} +``` + +### Destroy VF +```c +void gsp_vf_destroy(struct gsp_vf *vf) { + struct gsp_device *gsp = vf->gsp; + uint32_t id = vf->id; + + mutex_lock(&gsp->vf_lock); + vf->active = false; + list_del(&vf->list); + mutex_unlock(&gsp->vf_lock); + + gsp_vf_bar_fini(vf); + gsp_vf_wpr_fini(vf); + + if (vf->migration) + gsp_migration_cancel(vf->migration); + + kref_put(&vf->ref, gsp_vf_release); +} + +static void gsp_vf_release(struct kref *ref) { + struct gsp_vf *vf = container_of(ref, struct gsp_vf, ref); + kfree(vf); +} +``` + +## Memory Management (ALLOC/PIN) + +### Allocate VF Memory +```c +int gsp_vf_mem_alloc(struct gsp_vf *vf, + uint64_t size, uint32_t flags, + uint64_t *handle, uint64_t *va) { + struct alloc_payload payload = { + .size = size, + .type = MEM_TYPE_VRAM, + .alignment = 0x1000, + .va_hint = 0, + .flags = flags, + .pid = current->pid, + .vf_id = vf->id, + }; + + struct alloc_response resp; + size_t resp_size = sizeof(resp); + + return gsp_rpc_send_sync(vf->gsp->rpc, RPC_ALLOC, + &payload, sizeof(payload), + &resp, &resp_size); +} +``` + +### Pin Memory for DMA +```c +int gsp_vf_mem_pin(struct gsp_vf *vf, uint64_t handle, + uint64_t offset, uint64_t size, + uint64_t *dma_addr) { + struct pin_payload payload = { + .handle = handle, + .offset = offset, + .size = size, + .vf_id = vf->id, + .flags = PIN_WRITE | PIN_READ, + }; + + struct pin_response resp; + size_t resp_size = sizeof(resp); + + return gsp_rpc_send_sync(vf->gsp->rpc, RPC_PIN, + &payload, sizeof(payload), + &resp, &resp_size); +} +``` + +## Debugging & Testing + +### Debugfs Interface +```bash +# List VFs +cat /sys/kernel/debug/gsp/vfs + +# VF details +cat /sys/kernel/debug/gsp/vf/1/status + +# RPC statistics +cat /sys/kernel/debug/gsp/rpc/stats + +# BAR state +cat /sys/kernel/debug/gsp/vf/1/bar + +# WPR regions +cat /sys/kernel/debug/gsp/vf/1/wpr + +# Migration status +cat /sys/kernel/debug/gsp/vf/1/migration +``` + +### Trace Events +```bash +# Enable tracing +echo 1 > /sys/kernel/debug/tracing/events/gsp/enable + +# Trace migration +trace-cmd record -e gsp_mig_phase -e gsp_mig_transfer + +# Trace WPR +trace-cmd record -e gsp_wpr_event +``` + +### Unit Tests +```c +// kselftest for gsp-rpc +static void test_rpc_alloc(void) { + struct gsp_vf *vf = create_test_vf(); + uint64_t handle, va; + + ASSERT_EQ(gsp_vf_mem_alloc(vf, 4096, 0, &handle, &va), 0); + ASSERT_NE(handle, 0); + ASSERT_NE(va, 0); + + gsp_vf_mem_free(vf, handle); + destroy_test_vf(vf); +} +``` + +## Error Handling Checklist + +| Scenario | Detection | Recovery | +|----------|-----------|----------| +| GSP firmware crash | Watchdog timeout | Reset GSP, reload FW | +| RPC timeout | Doorbell no response | Retry, then VF reset | +| BAR trap storm | Rate limit exceeded | Throttle VF | +| WPR violation | Callback storm | Quarantine VF | +| Migration fail | Commit verify fail | Rollback to source | + +## Performance Tuning + +### RPC Batching +```c +// Batch multiple ALLOCs in single RPC +struct batch_alloc_payload { + uint32_t count; + struct alloc_payload allocs[MAX_BATCH]; +}; +``` + +### Async Completion +```c +// Use async RPC for non-critical paths +gsp_rpc_send_async(rpc, RPC_NOTIFY, payload, size, callback, ctx); +``` + +### Memory Pool +```c +// Pre-allocate bounce buffers +struct gsp_bounce_pool { + struct page **pages; + int count; + spinlock_t lock; +}; +``` + +--- + +## Reference +- GSP Firmware: gsp-570.144.fwimage.bin +- Base Address: 0x04000000 +- Primary Dispatcher: 0x057A1AC0 +- Secondary Dispatcher: 0x04ED39DC \ No newline at end of file -- cgit v1.2.3