From 2302fc09080bad51c73f293294e19fd4db464eb0 Mon Sep 17 00:00:00 2001 From: Open-IOV Date: Wed, 23 Sep 2026 05:44:08 -0400 Subject: Open-IOV: initial public release Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with real GPU functionality - CUDA first, 3D and video to follow - on unmodified hosts, without a proprietary vGPU license and without patching any driver, firmware or hypervisor. Core principle: emulate the interface, pass through the work. kernel/ open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device (PCI config space, BAR shadows, MSI-X), GSP boot emulation, GSP-RM message-queue/RPC emulation, memory model (GPU-VA to guest-PA discovery) and the semaphore-completion service that advances guest UVM progress. userspace/ libiov.so management API and examples. tools/ guest diagnostics, firmware analysis wrappers, RM probes. scripts/ stack manager, VM harness, build/load/test automation. config/ hardware/version profiles (the portability surface). docs/ documentation tree - start at docs/README.md. wiki/ long-form firmware and protocol deep dives. Status: initialization works end to end for a stock 570.144 Linux guest on Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery, object creation and the early CUDA/UVM start-up path. GPU work forwarding - the step that makes CUDA kernels execute on real hardware - is the active work item; see docs/04-implementation/01-known-knowns-and-unknowns.md. License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md. --- wiki/open-iov.org/index.php/AMDGPU.html | 220 +++++ wiki/open-iov.org/index.php/Articles.html | 323 +++++++ wiki/open-iov.org/index.php/CPU_Support.html | 233 +++++ ...ile:Application_Binary_Interface_(ABI).png.html | 233 +++++ ...e_Decomposure_and_Recomposure_via_VFIO.png.html | 233 +++++ ...e:Echoing_a_UUID_into_the_sysfsdev_API.png.html | 233 +++++ ...re_0-_Approches_to_GPU_Virtualization..png.html | 233 +++++ .../File:Figure_0-_i915_vGPU_Scheduling.png.html | 233 +++++ ...s_information_for_an_Intel_DG2_device..png.html | 233 +++++ .../File:Figure_2-_Intel_vGPU_Scheduler.png.html | 233 +++++ ...Timeshared_Syhededuling_via_Channel_IO.png.html | 233 +++++ ...MMU_-_GMMU_IOVA_translation-isolation..png.html | 233 +++++ ...verlays_within_a_VFIO_file_descriptor..png.html | 233 +++++ ...ile_descriptor_triggers_EPT_violation..png.html | 233 +++++ ...le:I915_Scheduling_Events_and_Requests.png.html | 234 +++++ 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a/wiki/open-iov.org/index.php/AMDGPU.html b/wiki/open-iov.org/index.php/AMDGPU.html new file mode 100644 index 0000000..47c05f6 --- /dev/null +++ b/wiki/open-iov.org/index.php/AMDGPU.html @@ -0,0 +1,220 @@ + + + + +AMDGPU - Open-IOV + + + + + + + + + + + +
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AMDGPU

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The AMDGPU driver is AMD's open source GPU driver which comes included with the Linux kernel.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

This software's source code can be viewed here. +


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This Open-IOV page should aim to provide similar insights about APIs exposed to Linux developers to those documented on the OpenRM Driver API page. +


+This page may provide some of the required information from which details immediately relevant to graphics mediation can be consolidated: +

https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html +

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Articles

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This page indexes the articles contained within Open-IOV. +

If you're new to GPU Virtualization start by reading the Introduction article. +

+ + +

Start Here

+

Introduction +

About Open-IOV (CC-BY-4.0) +

+

Abstract

+

Glossary +

Virtualization Fundamentals +

Merged Drivers +

+

Design Documents

+

Virtual I/O Internals +

GPU Driver Internals +

+

Driver Integration Documents

+

Nvidia +

Intel +

AMD +

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Projects

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LIME Is Mediated Emulation +

Looking Glass +

OpenXT +

OpenXT: vGlass +

OpenXT: Surfman (legacy DRM) +

Bromium/uXen +

Xen Project +

Qubes OS +

Intel Celadon +

vGPU_Unlock +

+

Device Support

+

GPU Support +

CPU Support +

GPU Firmware +

+

Software Support

+

Hypervisor Support +

GPU Software Bill Of Materials (SBOM) +

+

API Documentation

+

Kernel APIs

+

Kernel.org Driver Core Documentation +

NT Kernel (Windows) IOMMU-based GPU Isolation +

VFIO - vfio.h - mdev.h +

VFIO Mediated Device +

+

Driver APIs

+

i915 GVT-g API +

Nouveau Tools & API +

+

Sample Code

+

GPLv2 sources mirrored from elixir.bootlin.com with simple makefile changes. +

mtty.c - mdpy.c - mdpy-fb.c - mdpy-defs.h - mbochs.c +

+

Virtualization APIs

+

GVM/Mdev-CLI API +

QEMU Machine Protocol (QMP) Reference Manual +

Inter-VM Shared Memory (IVSHMEM) +

+

User Guides

+

Setup Guide +

Looking Glass Quickstart Guide +

Intel GVT-g Setup Guide +

AMD GPU-IOV Module Docs +

PCI passthrough via OVMF +

RedHat Virtualization Guide +

+

Developer Guides

+

Hypervisor From Scratch +

Linux Device Drivers (3rd Edition) +

GPU Driver Developer's Guide +

How To Write PCI Drivers +

Data Plane Development Kit: IVSHMEM Programming Guide +

+

Specifications

+

Hyper-V Hypervisor Top Level Functional Specification (TLFS) +

+

Communities & Mailing Lists

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Open-IOV Discord +

Intel-gfx Mailing List +

Nouveau Mailing List +

AMD-gfx Mailing List +

VFIO-users Mailing List +

Level1Techs Forum [VFIO Topic] +

VFIO Subreddit +

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CPU Support

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In order to use mediated device functionality you may need to set some or all of the following settings in your machine's UEFI.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

UEFI Setup

+

Intel CPUs (VT-d)

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Optimal UEFI Settings +

IOMMU >> Enabled +

SR-IOV Support >> Enabled +

VT-x >> Enabled +

ARI Mode >> Enabled +

+

AMD CPUs (AMD-v)

+

Optimal UEFI Settings +

SVM Mode >> Enabled +

SR-IOV Support >> Enabled +

ACS Enable >> Enabled +

IOMMU >> Enabled +

PCI AER Support >> Enabled +

ACS Enable >> Enabled +

ARI Mode >> Enabled +

Note to AMD CPU users: If you are using a first generation Ryzen or ThreadRipper platform you may need to update your motherboard UEFI to make proper use of IOMMU Groups. If your motherboard manufacturer has not made an update available you may need to apply an ACS override patch. Successive AMD CPU platforms are unaffected. +

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Application Binary Interface (ABI) +

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File:Device Decomposure and Recomposure via VFIO.png

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Device Decomposure and Recomposure via VFIO +

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Echoing a UUID into the sysfsdev API +

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File:Figure 0- Approches to GPU Virtualization..png

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Figure 0: Approches to GPU Virtualization. +

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File:Figure 0- i915 vGPU Scheduling.png

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Figure 0: i915 vGPU Scheduling +

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File:Figure 2- Firmware status information for an Intel DG2 device..png

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Figure 2: Firmware status information for an Intel DG2 device. +

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Figure 2: Intel vGPU Scheduler +

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File:Figure 3- GPU BAR to Timeshared Syhededuling via Channel IO.png

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Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO +

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Figure 6: MMU - GMMU IOVA translation/isolation. +

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Figure 7: A depiction of region overlays within a VFIO file descriptor. +

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Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. +

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I915 Scheduling Events and Requests +

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Placing a VFIO binding into a VFIO Container. +

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File:IVSHMEM.png

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IVSHMEM +

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File:Intel GVT-g Capabilities.png

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"Accelerate up to 8 VMs plus DOM0." +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html b/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html new file mode 100644 index 0000000..72dfbda --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html @@ -0,0 +1,233 @@ + + + + +File:Intel i915 Host DRM + VFIO-Mdev..png - Open-IOV + + + + + + + + + + + +
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File:Intel i915 Host DRM + VFIO-Mdev..png

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Intel's i915 driver provides host and guest GPU acceleration via host DRM + VFIO-Mdev in the same driver. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Ioctl-VFIO_GROUP_GET_FD.png.html b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_GROUP_GET_FD.png.html new file mode 100644 index 0000000..8658593 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_GROUP_GET_FD.png.html @@ -0,0 +1,233 @@ + + + + +File:Ioctl-VFIO GROUP GET FD.png - Open-IOV + + + + + + + + + + + +
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File:Ioctl-VFIO GROUP GET FD.png

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Using an interrupt routine to obtain the VFIO Group file descriptor. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html new file mode 100644 index 0000000..ec1ed65 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html @@ -0,0 +1,233 @@ + + + + +File:Ioctl-VFIO IOMMU MAP-UNMAP DMA.png - Open-IOV + + + + + + + + + + + +
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File:Ioctl-VFIO IOMMU MAP-UNMAP DMA.png

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Using interrupts VFIO_IOMMU_MAP/UNMAP_DMA to pin/map regions of memory. +

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File:Ioeventfd-and-irqfd.png

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"A very simple" diagram of ioeventfd and irqfd. +

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File:KVMFR Looking Glass.png

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KVMFR Looking Glass +

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File:KVM services EPT violation and forwards to QEMU VFIO PCI driver..png

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KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Mdev-gpu.png.html b/wiki/open-iov.org/index.php/File:Mdev-gpu.png.html new file mode 100644 index 0000000..cf5fb21 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Mdev-gpu.png.html @@ -0,0 +1,233 @@ + + + + +File:Mdev-gpu.png - Open-IOV + + + + + + + + + + + +
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File:Mdev-gpu.png

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Registering the mediated device. +

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current19:40, 19 July 2022Thumbnail for version as of 19:40, 19 July 20222,796 × 1,940 (221 KB)Arthur (talk | contribs)
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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Memory_Regions_Added_by_QEMU.png.html b/wiki/open-iov.org/index.php/File:Memory_Regions_Added_by_QEMU.png.html new file mode 100644 index 0000000..d42443b --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Memory_Regions_Added_by_QEMU.png.html @@ -0,0 +1,233 @@ + + + + +File:Memory Regions Added by QEMU.png - Open-IOV + + + + + + + + + + + +
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File:Memory Regions Added by QEMU.png

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Memory Regions Added by QEMU +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:NUMA_Node.png.html b/wiki/open-iov.org/index.php/File:NUMA_Node.png.html new file mode 100644 index 0000000..8436f5a --- /dev/null +++ b/wiki/open-iov.org/index.php/File:NUMA_Node.png.html @@ -0,0 +1,233 @@ + + + + +File:NUMA Node.png - Open-IOV + + + + + + + + + + + +
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File:NUMA Node.png

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NUMA_Node.png ‎(624 × 314 pixels, file size: 24 KB, MIME type: image/png) +

NUMA Node +

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current00:46, 18 December 2021Thumbnail for version as of 00:46, 18 December 2021624 × 314 (24 KB)Arthur (talk | contribs)
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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html b/wiki/open-iov.org/index.php/File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html new file mode 100644 index 0000000..cc18d14 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html @@ -0,0 +1,233 @@ + + + + +File:QEMU calls VFIO DMA MAP via Memory listener.png - Open-IOV + + + + + + + + + + + +
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File:QEMU calls VFIO DMA MAP via Memory listener.png

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Original file ‎(1,738 × 1,373 pixels, file size: 19 KB, MIME type: image/png) +

QEMU calls VFIO DMA MAP via Memory listener +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html b/wiki/open-iov.org/index.php/File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html new file mode 100644 index 0000000..12d9322 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html @@ -0,0 +1,233 @@ + + + + +File:QEMU convert request from KVM to Read-Write acess to Mdev file descriptor..png - Open-IOV + + + + + + + + + + + +
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File:QEMU convert request from KVM to Read-Write acess to Mdev file descriptor..png

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Original file ‎(1,700 × 1,333 pixels, file size: 57 KB, MIME type: image/png) +

QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html b/wiki/open-iov.org/index.php/File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html new file mode 100644 index 0000000..66c6d1c --- /dev/null +++ b/wiki/open-iov.org/index.php/File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html @@ -0,0 +1,233 @@ + + + + +File:QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor..png - Open-IOV + + + + + + + + + + + +
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File:QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor..png

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Original file ‎(1,738 × 1,341 pixels, file size: 57 KB, MIME type: image/png) +

QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html b/wiki/open-iov.org/index.php/File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html new file mode 100644 index 0000000..8a49589 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html @@ -0,0 +1,233 @@ + + + + +File:QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs.png - Open-IOV + + + + + + + + + + + +
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File:QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs.png

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Original file ‎(1,695 × 1,332 pixels, file size: 57 KB, MIME type: image/png) +

QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs +

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File:QEMU presenting the VFIO file descriptor into the virtual machine..png

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QEMU presenting the VFIO file descriptor into the virtual machine. +

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:SR-IOV-Diagram.png.html b/wiki/open-iov.org/index.php/File:SR-IOV-Diagram.png.html new file mode 100644 index 0000000..3db2769 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:SR-IOV-Diagram.png.html @@ -0,0 +1,233 @@ + + + + +File:SR-IOV-Diagram.png - Open-IOV + + + + + + + + + + + +
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File:SR-IOV-Diagram.png

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SR-IOV-Diagram +

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File:SR-IOV.png

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SR-IOV +

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File:Screen Shot 2022-05-06 at 10.46.59 AM.png

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Screen_Shot_2022-05-06_at_10.46.59_AM.png ‎(584 × 436 pixels, file size: 23 KB, MIME type: image/png) +

Peer-to-Peer DMA Isolation under IOMMU +

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File:Screen Shot 2022-11-18 at 4.14.32 PM.png

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Screen_Shot_2022-11-18_at_4.14.32_PM.png ‎(603 × 525 pixels, file size: 45 KB, MIME type: image/png) +

Pictured: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. +

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File:Telescope LG-Proxy.png

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An RDMA based proxy for the Looking Glass Memory Protocol. +

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File:Type 1 IOMMU Tracks VA-GFN.png

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Type 1 IOMMU Tracks VA-GFN +

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File:VFIO-Mdev Diagram.png

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A diagram of VFIO-Mdev. +

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File:VFIO Diagram.png

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VFIO_Diagram.png ‎(398 × 527 pixels, file size: 62 KB, MIME type: image/png) +

A VFIO diagram. +

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File:Vfio-pci driver bindings.png

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VFIO group nodes are unit of ownership that VFIO uses. +

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Virgl.png ‎(384 × 509 pixels, file size: 66 KB, MIME type: image/png) +

Virgl +

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GPU Driver Internals

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This page will detail the internals of various GPU drivers for use with I/O Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Article Structure

+

This article will aim to provide information about the following details of GPU drivers: +

+

High Level Architecture

+

This section will detail high level architectures of each driver. +

+

Initialization

+

This section will cover how the GPU's embedded components, the GPU driver, and virtualization functions are initialized. +

+

Scheduling

+

This section will detail how the device schedules instructions for execution. +

This will attempt to provide a comprehensive view of scheduling from virtualized processes down to execution within the device. +

+

In-VM Scheduling

+

The In-VM Scheduling section will detail how instructions scheduled within the virtual machine's GPU device driver. +

+

Between-VM Scheduling

+

The Between-VM Scheduling section will detail how the host kernel module and/or virtual GPU helper functions handle scheduling / context swaps between virtual machines on a computer system. +

+

Firmware Scheduling (if applicable)

+

The Firmware Scheduling section will cover the GPU's internal scheduling model if a deferred execution pathway is used (like i915's GuC or OpenRM's GSP). +

In the case an intermediate scheduling microcontroller is not used this section may be less applicable (ie: vExeclist scheduling under Intel vGPUs). +

+

Memory Management

+

The Memory Management section will cover how the GPU driver manages memory for virtual GPUs and host processes. +

This will aim detail paging abstractions used for global memory translation, and per-process memory translation. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will cover methods provided by the GPU driver suitable for high performance graphics sharing. +

+

Vendor Neutral

+

This section will detail functions in common between GPU drivers. +

Also see Display Virtualization for Windows OS. +

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Satyeshwar Singh. +

+

Display Surface Virtualization

+

The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +

+

Graphics Buffer Sharing

+

This section will deal with graphics buffer sharing for vendor neutral GPUs. +

+
Display Flow in Linux
+

Userspace applications provide their buffers to compositor. +

Compositor asks Mesa to create a framebuffer. +

Framebuffer is allocated through vendor driver. +

Vendor driver flips the framebuffer on the screen. +

+
SR-IOV and Mdev
+

SR-IOV VFs don't have access to the display controller (only PF does). +

Known issue is displaying a VF's framebuffer on the screen. +

+
VFs in QEMU Hypervisor (VirtIO-GPU)
+

SR-IOV and Mdev VFs run in QEMU Hypervisor. +

QEMU has full access to all pages in VF's address space. +

VirtIO-GPU allows for allocating buffers (not API remoting in this case). +

Mesa's KMSRO allocates framebuffer via virtio-gpu. +

Mesa's KMSRO asks vendor driver to import framebuffer (no specific compositor dependancy). +

+
Transport
+

A Scatter Gather List (SGL) of physical pages is constructed by VirtIO-GPU of VF. +

+
QEMU Host-Side u-dma-buf
+

Host QEMU uses u-dma-buf driver to reconstruct a virtual memory pointer from the SGL shared by VF. +

u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers. +

+
QEMU Host-Side Modules
+

Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI. +

QEMU UI has several toolkits to support like GTK, SDL, etc. with GTK. being the default. +

GTK uses EGL and passes it the DMABUF as a texture. +

+
Windows VFs
+

Windows OS doesn't support DMABUF capability so we can't allocate buffers from VirtIO-GPU and share them with the Windows Kernel Mode Driver (KMD). +

Windows OS is different in the way that the FB is allocated via the OS rather than the miniport driver. +

Modified version of RedHat virtio-gpu-do (short for Display Only) driver used. +

+
Windows Driver Stack
+

OS (DWM) allocates frame buffers and asks GPU to write to them through Miniport. +

DVServer UMD (IDD) asks the OS for the FB copy. +

DVServer UMD (IDD) passes the virtual memory address to DVServer KMD. +

+
DVServer KMD
+

DVServer KMD finds the SGL (Scatter Gather List) of physical pages for this virtual memory address. +

This SGL is passed via virt-queue from the VF to the host QEMU. +

+
Android VFs
+

Android uses Linux kernel underneath. VirtIO-GPU is present in Android's kernel. +

KMSRO patch to allocate framebuffer via VirtIO-GPU also ported over to Android. +

Need modifications in the minigbm lib of Android to connect with KMSRO part. +

Rest of stack looks identical to Linux VF/PF. +

+

i915

+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Zhi Wang, Ben Widawsky, and Igor Bogdanov. +

See references 2, 3, 4, 5, 6, 7, 8, and 9 in the References (Talks & Reading Material) section. +

+

High Level Architecture

+

i915 Clients

+

Processes which make use of the Intel i915 driver receive an i915 Client ID. +

+

Initialization

+

During initialization of the i915 driver the GuC binary blob is offloaded into the Graphics Translation Table (GTT). This allows the GuC to read GTT-loaded binary blob from shared framebuffer memory so that it may boot. +

+

Scheduling

+
Figure 0: i915 vGPU Scheduling
Figure 0: i915 vGPU high-level Scheduling. See slides from: [9]
+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (i915.ko)
  • +
  • Host kernel (i915.ko)
  • +
  • Device Firmware (GuC)
+
In-VM Scheduling
+
Guest kernel (i915.ko)
+
vExeclist
+

The vExeclist is a method to submit commands directly to the GPU without the use of an intermediate microcontroller. +

+
vGuC
+

vGuC is a command submission interface used to process commands to the Intel Graphics Microcontroller (GuC). +

+

Between-VM Scheduling

+
Figure 1: i915 vGPU Scheduling Requests & Events
Figure 1: i915 vGPU Scheduling Requests & Events. See slides from: [9]
+
Host kernel (i915.ko)
+

Submitting commands to the GPU under i915 can take several paths. One pathway makes use of direct command submission without an intermediate micro-controller whereas the other uses an intermediate micro-controller. The intermediate micro-controller approach increases the amount of binary-blob code used and abstracts the kernel module from the device's internal scheduling model. +

+
Execlist
+

Execlist executes commands synchronously on the device without an intermediate microcontroller. This is the preferred method of executing commands by some driver developers because of it's stability and transparency under current i915 development. +

+
GuC
+

GuC provides an execution pathway with an intermediate microcontroller providing a scheduling abstraction for Intel's preferred internal scheduling model. +

+
Figure 2: Intel vGPU Scheduler request flow.
Figure 2: i915 vGPU Scheduler request flow. See slides from: [9]
+
Device Firmware (GuC)
+

Memory Management

+
Translation Tables
+
GTT (Graphics Translation Table)
+

GPU Memory on-device is a part of a GTT or Graphics Translation Table. This table stores information globally for all graphics processes within the system. Some processes access the Global Graphics Translation Table (GGTT) such as DRI while other's receive a Per Process Graphics Translation Table (PPGTT) buffer based on their i915 Client ID. +

+
GGTT (Global Graphics Translation Table)
+
PPGTT (Per Process Graphics Translation Table)
+

Process-specific memory buffers are stored inside a Per Process Graphics Translation Table or PPGTT. This is a GPU MMU translated subregion or IOVA of global GPU memory specific to a GPU process's client ID. +

+
Aliasing PPGTT
+

Aliasing PPGTT (Per Process Graphics Translation Table) refers to partially separated GPU resources (process context). +

+
Real PPGTT
+

Real PPGTT (Per Process Graphics Translation Table) refers to fully separated GPU resources (process context). +

+

Display Surface Virtualization

+

The Intel vGPU makes use of two modes for Display Surface Virtualization. +

+
  • VirtIO-GPU (Linux)
  • +
  • Indirect Display Driver (Windows)
+

VirtIO-GPU

+

IDD (Indirect Display Driver)

+

The IDD (Indirect Display Driver) provides virtual display functions with arbitrary resolutions to any rendering device virtual or physical. +

Intel's IDD can be found in their Display Virtualization for Windows OS repository. +

+

Graphics Buffer Sharing

+

Intel's i915 driver provides functionality to directly map display memory from a guest vGPU Virtual Function (either SR-IOV or VFIO-Mdev) into the host GPU's Physical Function without slow memory copies or graphics compression. For users running GPU virtualization on their local device this results in a significant performance uplift compared to traditional graphics sharing functionality built for remote access use-cases such as VDI. +

Intel's 0copy display virtualization tools are simple to implement as sharing does not rely upon an added IVSHMEM (Inter-VM Shared Memory device) - rather the host directly maps the guest's display memory via udmabuf as the buffer sharing functions are provided within the i915 open source driver. +

+

OpenRM

+
Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO
Figure 3: GPU BAR to Timeshared Scheduling via Channel IO.
+

Knowledge Resources Used

+

This section is supported by significant contributions to documentation and open source by Andy Currid, Neo Jia, John Fanelli, and Neha Joshi. +

+

High Level Architecture

+

The Open Resource Manager (RM driver) makes use of a highly object oriented paradigm comprised of multiple "engines" which act as micro-services for servicing driver requests. +

The Open Resource Manager driver (also known as OpenRM) refers to Nvidia's open-kernel-modules. +

Broadly speaking the OpenRM driver consists of two parts. +

+
  • The Platform RM (OpenRM)
  • +
  • The Firmware RM (GSP RM / RM Core)
+

The Platform RM is loaded into the Linux Kernel as nvidia.ko. This module communicates with the GSP RM for via Remote Procedure Calls (RPCs) to communicate with engines from the RM Core. +

+
RM Clients
+

Processes (local, remote, or virtualized) which make use of the RM driver receive an RM Client ID. +

+

RM Server

+

The RM Server (or Resource Server) tracks RM Clients as well as the hardware and software resources they control, allocate, and free. +

+

RM API

+

API to control the Resource Manager Server. +

+

RM Core

+

Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors. Under OpenRM the RM Core runs within the GPU System Processor (GSP micro-controller) while in pre-open source versions of the Resource Manager the RM Core ran within the nvidia.ko kernel module +

+

Initialization

+

During bring up of the hardware several binary blobs are loaded from embedded Boot ROM memory to bootstrap embedded controller bring up from which point additional software is loaded from onboard SPI flash memory. +

Software loaded from SPI flash is necessary for the full initialization of the Falcon/NvRISC processor as well as a cached version of the software necessary to run the GPU System Processor (GSP). +

Once the platform is posted it is ready to communicate with the host platform's RM driver. The OpenRM driver offloads a binary blob containing the RM Core to the GPU System Processor (GSP) which is likely to contain a more recent version than the cached version contained in on-board SPI flash. +

+

Scheduling

+

There are several abstractions for GPU virtual machine scheduling. Those are as follows: +

+
  • Guest kernel (nvidia.ko)
  • +
  • Host kernel (nvidia.ko)
  • +
  • Host usermode (gpu-mgr / libnvidiavgpu.so)
  • +
  • Device Firmware (GSP)
+

Command Submission

+
Runlist
+

In-VM Scheduling

+

Virtual machines contain their own GPU scheduling within the Nvidia kernel module in the guest OS. +

+
Guest kernel (nvidia.ko)
+

Within a virtual machine running the Nvidia driver messages to the GPU are first sent to the guest nvidia.ko kernel module. +

+The guest then determines whether a vRPC (virtual Remote Procedure Call) or a pRPC (physical Remote Procedure Call) should be sent. Both pRPCs and vRPCs are sent through the host RM driver (Resource Manager).

Note: Unclear on execution pathway for pRPCs vs vRPCs. pRPCs may go directly to device.

+

Between-VM Scheduling

+

In addition to scheduling which occurs within the virtual machine the Resource Manager driver also schedules messages to the GPU between GPU-accelerated virtual machines and host processes. +

+
Host kernel (nvidia.ko)
+

Messages sent by the guest (via vRPC or pRPC) are received by the host Nvidia.ko driver. +

Nvidia.ko contains a virtual GPU state machine which contains status information for the virtual GPU. +

Nvidia.ko also contains a virtual GPU kernel scheduler which interacts with virtual GPU objects. +

Nvidia.ko also contains an RM Call scheduler which schedules calls on an RM class. +

The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin). +

+
Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)
+

After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and it's library libnvidia-vgpu.so) are executed to schedule VM-exits described below. +

+
nvidia-vgpu-mgr
+

The nvidia-vgpu-mgr is a process which provides the spawning of virtual GPU stubs and population with capability information. +

This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components. +

This process and the libnvidia-vgpu.so contain, and execute the VMIOP. +

This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the RM Core. +

+
vmiop
+

VMIOP (Virtual Machine Input Output Plugin) handles presenting virtualized functionality into the guest. +

The Virtual Machine Input Output Plugin software handles virtual displays, compute API offload, and most importantly BAR (Base Address Register) quirks. +

The VMIOP is an SDK (Software Development Kit) provided in binary format split between the libnvidiavgpu.so and nvidia-vgpu-mgr which provides userland helper functions for GPU virtualization. +

Messages to the VMIOP are scheduled by Linux kernel niceness (scheduling abstraction). +

+
Device Firmware (GSP)
+

Messages received by the host RM driver (Resource Manager) are then scheduled by the RM Core contained within the GSP (GPU System Processor). The GSP handles the device's internal scheduling model. +

+

Memory Management

+

Managing virtual machine memory is very important to the security of virtualization. +

This section will cover the method by which secure memory "enclaves" or IO Virtual Addresses (IOVAs) may be provisioned and separation enforced by hardware constructs within the GPU. +

+
Programming the MMU
+

In order to hardware enforce separation between memory allocated to Virtual Machines (VMs) virtualization software must program the GPU's MMU (GMMU controller) to create IO Virtual Addresses (IOVAs). +

In order to create such configurations several abstractions are used to translate high level representations of virtualization programmed via the vmiop and gpu-mgr into practical, architecture specific instructions. +

+
AMAPLibrary
+

The AMAPLibrary acts as a device abstraction framework for GPU driver software to program using high level representations of MMU configuration. +

The AMAPLibrary translates high level representations of GPU virtualization into graphics architecture-specific logic contained within architecture HALs (Hardware Abstraction Layers). +

+
Architecture HALs
+

GPU Hardware Abstraction Layers (HALs) contain logic specific to graphics architectures, for instance the precise method by which the GPU driver may interact with the Falcon to provision MMU protected memory. +

+
DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)
+

The Falcon (FAst Logic CONtroller) / NvRISC-V embedded controller emits DMAs to the Frame Buffer Interface (FBIF) in order to interact with the device's GMMU controller. +

User programs and VMs have their memory translated through the GMMU. +

Once created memory translations within a virtual machine's IO Virtual Address (IOVA) will be protected by the device's GMMU controller. +

+
Translation Tables
+
vmiop_gva
+

Display Surface Virtualization

+

amdgpu

+

References (Talks & Reading Material)

+
  1. Intel Graphics Programmer's Reference Manuals (PRM)
  2. +
  3. i915: Hardware Contexts (and some bits about batchbuffers)
  4. +
  5. i915: The Global GTT Part 1
  6. +
  7. i915: Aliasing PPGTT Part 2
  8. +
  9. i915: True PPGTT Part 3
  10. +
  11. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
  12. +
  13. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
  14. +
  15. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  16. +
  17. i915: An Introduction to Intel GVT-g (with new architecture)
  18. +
  19. lwn.net: Add udmabuf misc device
  20. +
  21. Nvidia RISC-v Story
  22. +
  23. IOMMU Introduction
  24. +
  25. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
  26. +
  27. nVidia GPU Introduction (envytools)
  28. +
  29. Delivering High Performance Remote Graphics With Nvidia GRID Virtual GPU
  30. +
  31. NVIDIA Multi-Instance GPU
  32. +
  33. i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]
  34. +
  35. Lifecycle of a Triangle - Nvidia's logical pipeline
  36. +
  37. Nvidia Parallel Thread Execution (PTX)
  38. +
  39. i915/GEM Crashcourse
  40. +
  41. drm: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
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GPU Firmware

+
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From Open-IOV
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GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel

+

Firmware Images

+This section will cover firmware images used in Intel GPUs.

Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification.
Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. Source
+

Intel Firmware Support Package (FSP)

+

Much like CPUs Intel's GPUs also contain a Firmware Support Package (FSP). +

The Coreboot project provides public domain information on the FSP here. +

+
FSP Configuration
+

In the context of GPUs the FSP configures several functions of the device. +

Those functions are as follows: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
GPU Firmware Support Package +
FSP Parameter +Possible Values +
GFSP Status +0x00 +
FIVR SSC Value +*.*% +
FIVR RFI Value +*.*MHz +
GT Subsystem Vendor ID +0x8086 +
GT Subsystem Device ID +0x** +
HDA Subsystem Vendor ID +0x0000 +
HDA Subsystem Device ID +0x0000 +
P2SB Enable +Yes/No +
LMEBAR +Max +
GTMMADDR Prefetch Capability +Prefetch Enabled +
Display Present +Enabled/Disabled +
I2C For Third Party Devices +Enabled/Disabled +
I2C Device Address 1 +0x0000 +
I2C Device Address 2 +0x0000 +
I2C Bus Speed +Standard mode (0 to 100Kbps) +
+
Editing FSP Configuration
+

The FSP configuration editor can be downloaded here and it's user manual is available here. +

+
FSP Binary Format
+

The FSP's binary layout is detailed within the Intel® FSP External Architecture Specification v2.4 on page 14. +

+

Known Firmware Package Variations

+

Some firmware packages may include an **End of Manufacturing Flash Protection Mode** status of Protected or Unprotected. +

+
Figure 2: Firmware status information for an Intel DG2 device.
Figure 2: Firmware status information for an Intel DG2 device.
+

Similar SPI Write Protection functionality is made available through Intel CPUs under System Management Mode (SMM). +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Intel GPU. +

+

GuC

+

The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs. +

+
Hardware Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The GuC - an embedded i486 core that supports graphics scheduling, power management and firmware attestation." +

+
Software Architecture
+

The following section is supported by igor-blue.github.io (see reference 1, 2): +

"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services." +

"It runs a single process - which initializes the system and then waits for interrupts/events in a loop." +

+
GuC Blob Checksum & Code Signing
+

"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing." +

+

Nvidia

+

Firmware Images

+

This section will cover firmware images used in Nvidia GPUs. +

+

Embedded Controllers

+

This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU. +

+

Falcon / NV-RISCV

+

The Fast Logic CONtroller (Falcon) and Nvidia RISC-V (NV-RISCV) processors run the NvOS. +

+

GSP

+

The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core. +

The GSP runs Library Operating System (LibOS). +

+
GSP Initialization & Offload
+

The GSP is initialized multiple times during the system's bring up and runtime. +

GSP offload may occur during: +

+
  • Hardware bring up when a cached version of the RM Core is loaded from SPI flash
+
  • During host driver bring up when the RM Core is offloaded by the OpenRM driver.
  • +
  • During guest driver bring up when the RM Core is offloaded.
+ + + + + + + + + + + + + + + + + +
Possible GSP Offloads +
Load Source +Payload +Notes +
SPI Flash +Cached RM Core +Used as a fallback in case of no rm offload. +
OpenRM +RM Core +This is the RM Core which was traditionally contained in the proprietary RM driver. +
VGX Guest +Guest RM Core +Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via gspHeapSize?). +
+

CMU

+

AMD

+

References (Talks & Reading Material)

+
  1. Security of the Intel Graphics Stack - Part 1 - Introduction
  2. +
  3. Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  4. +
  5. Firmware Security Realizations Part 3: SPI Write Protections
  6. +
  7. Intel® FSP: Firmware Solutions for the Internet of Things
+ + + + +
+
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Navigation menu

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+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html b/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html new file mode 100644 index 0000000..ae9ec87 --- /dev/null +++ b/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html @@ -0,0 +1,528 @@ + + + + +GPU Software Bill Of Materials (SBOM) - Open-IOV + + + + + + + + + + + +
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GPU Software Bill Of Materials (SBOM)

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From Open-IOV
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This page will keep a running list of components used to achieve GPU Virtualization.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Component Table +
Vendor +Component +Description +Version +OSS or Blob +Filesize +Vendor Docs +Release Date +Interfaces / APIs +Notes +
Microsoft +Indirect Display Driver (IDD) +Driver + +OSS + +Indirect Display Driver Overview + +UMDF, KMDF +The Indirect Display Driver (IDD) enables GPUs to render graphics at arbitrary resolutions without a physical display connected on Windows OS systems. +
RedHat +vfio_pci +Driver +6.2-rc1 +OSS +in-kernel +RedHat, kernel.org +2022.12.15 +irqfd, ioeventfd, IOCTL +Reference VFIO Stub driver used for discrete assignment of IO, and assignment of some SR-IOV-backed vGPU devices into virtual machines. This driver is commonly replaced with a vendor built VFIO interface with differing memory management and/or page pinning mechanisms which are specific to the vGPU software internals. +
Mediated Core (mdev.ko) +Driver +6.2-rc1 +OSS +0.044 MB +kernel.org +2016.xx.xx +irqfd, ioeventfd, IOCTL, Type 1 IOMMU +The Mediated Core driver provides a common interface for mediated device management that can be used by drivers of different devices. It is an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment (based on VFIO). +
+guest communication daemon +Daemon +0.1.0 +OSS + + +2023.02.08 +Virtio-Serial, CLI +Handles IO to and from guests and the host using Virtio-Serial to handle multiple different guest modules. +
mdev management CLI +1.0 +OSS +0.084 MB + +2023.01.06 +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
Intel +i915 SR-IOV +Driver +5.15 +OSS +in-kernel + + + +Intel's open source GPU driver for GuC-equipped graphics accelerators. +
GuC μOS +Firmware +Blob + + + +IOMMU Interrupts, Power Management Interrupts, GTT +Handles scheduling, and power management. +
HuC + + + +GTT +Handles video encoding/decoding. +
Display Virtualization for Windows OS +Driver +791 +OSS + +github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt + +udmabuf, UMDF, KMDF +Intel's 'Display Virtualization for Windows OS' provides a virtual pixel surface used for hardware graphics rendering using Microsoft's open source 'Indirect Display Driver (IDD)'. Display virtualization for Windows OS makes use of display memory sharing primitives provided in-driver by the i915 host. +
Nvidia +OpenRM +Driver +525.85.12 +OSS + +github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md +2023.01.31 + +Nvidia's open source GPU driver for GSP-equipped graphics accelerators. +
GSP RM (uproc) +Firmware +Blob + + +2023.01.31 +RPC +Embedded firmware based on LibOS containing the RM Core. +
Falcon/NvRISC (uproc) + + + + +FBIF (Frame Buffer Interface) / GMMU +Embedded firmware which handles many aspects of the device including configuring the GPU's GMMU controller. +
nvidia-vgpud +Daemon +v15.2 +Blob +0.108 MB +docs.nvidia.com/grid +2023.01.xx +CLI, IOCTL, RMAPI, Mediated Core +Configures the the nvidia-vgpu-mgr process. +
nvidia-vgpu-mgr +0.132 MB +2023.01.xx +vmiop, IOCTL, RMAPI, vRPC, pRPC, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. +
libnvidia-vgpu.so +Library +3.1 MB +2023.01.xx +vmiop, RMAPI, Mediated Core +Handles IO to and from guest RM, host RM, and hardware. Contains circular dependancies with nvidia-vgpu-mgr. +
nvidia-vgpu-vfio.ko +Driver +0.108 MB +2023.01.xx +Type 1 IOMMU, irqfd, ioeventfd, IOCTL, Mediated Core +Handles incremental memory mapping (non-page pinning per the standard vfio-pci driver). +
+

More Information

+
  1. Nvidia RISC-V Story
  2. +
  3. +
  4. Intel Graphics Programmer's Reference Manuals (PRM)
  5. +
  6. i915: Hardware Contexts (and some bits about batchbuffers)
  7. +
  8. i915: The Global GTT Part 1
  9. +
  10. i915: Aliasing PPGTT Part 2
  11. +
  12. i915: True PPGTT Part 3
  13. +
  14. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
  15. +
  16. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
  17. +
  18. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  19. +
  20. i915: An Introduction to Intel GVT-g (with new architecture)
+ + + + +
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Navigation menu

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GPU Support

+
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From Open-IOV
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+ +

Abstract

+The following document will detail GPU Support for SR-IOV, SIOV, and VFIO-Mdev functionality.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

Overview

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Feature Matrix +
Hardware +Drivers +Virtual I/O Assistance Modes +Userspace +
Vendor +Architecture +Model +Libre Drivers +Blob Drivers +'Merged' Host+Guest Acceleration +Manufacturer Support +Mdev Support +SR-IOV Support +SIOV Support +mdev management CLI Support + Support +
Intel +6th Generation (Skylake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +7th Generation (Kaby Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +8th Generation (Coffee Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +9th Generation (Cannon Lake) +*HD +i915 + +Yes +Yes (Legacy) +Yes +No +No +No +Yes +
Intel +10th Generation (Ice Lake) + +i915 + +No +Yes (Legacy) +No +No +No +No +No +
Intel +11th Generation (Tiger Lake) +Xe* +i915 + +Yes +Yes + +Yes + +Yes +Yes +
Intel +12th Generation (Alder Lake) +Xe* +i915 + +Yes +Yes + +Yes +In Development +Yes +Yes +
Nvidia +Maxell +*(see exceptions below) +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Pascal +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Turing +* +Nouveau, OpenRM +RM +Yes +Yes +Yes +No +No +Yes +Yes +
Nvidia +Ampere +A* +Nouveau (Development), OpenRM +RM +No (DisplayModeSelector) +Yes +Yes +Yes +In Development +Yes +Yes +
Nvidia +Ampere +RTX 30** +Nouveau (Development), OpenRM +RM +In Development +Yes +Yes +No +In Development +In Development +In Development +
Nvidia +Ada Lovelace +* +OpenRM + + +Yes +Yes +Yes +In Development +In Development +In Development +
Nvidia +Hopper +* +OpenRM + + +Yes +Yes +Yes +In Development + + +
AMD +Tonga +W7100 +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +

(patched) +

+
No +No +Yes +
AMD +Tonga +S71** +AMDGPU, MxGPU / GIM / GPU-IOV Module (Deprecated) +AMDGPU-Pro +No +EOL (2017) +No +Yes +No +No +Yes +
AMD +Vega +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
AMD +Navi +* +AMDGPU +AMDGPU-Pro +No +Partial +Unknown +Yes +No +No +No +
+

Intel

+

This section will cover Mdev support on Intel GPUs. +

+

Hardware

+

GPUs supporting GVT-g (software based mediation)[1]: +

+
  • Intel HD Graphics 5500
  • +
  • Intel HD Graphics 6000
  • +
  • Intel HD Graphics 510
  • +
  • Intel HD Graphics 520
  • +
  • Intel HD Graphics 530
  • +
  • Intel HD Graphics 620
  • +
  • Intel HD Graphics 630
  • +
  • Intel UHD Graphics 620
  • +
  • Intel UHD Graphics 630
+

GPUs supporting SR-IOV (hardware based mediation): +

+
  • Intel Iris Xe Graphics [2][3]
  • +
  • Intel Iris Xe MAX Graphics
+

Drivers

+

Drivers with GVT-g support (6th - 9th gen): +

+ +

Drivers with SR-IOV support (11th gen+): +

+ +

Nvidia

+

This section will cover Mdev support on Nvidia GPUs. +

+

Hardware

+
  • All(?) Volta based GPUs (V-series)
  • +
  • All(?) Turing based GPUs (20-series)
  • +
  • All(?) Pascal based GPUs (10-series)
  • +
  • Most Maxwell based GPUs (9-series) with the following notable exceptions: +
    • GTX 970 (mixed FB regions)
    • +
    • Quadro M2000 (mixed FB regions)
    • +
    • Tesla M40 [4]
+
  • NVIDIA A100 HGX 80GB
  • +
  • NVIDIA A100 PCIe 80GB (SR-IOV: 20VF [5])
  • +
  • NVIDIA A100X
  • +
  • NVIDIA A100 HGX 40GB
  • +
  • NVIDIA A100 PCIe 40GB (SR-IOV: 16VF [6])
  • +
  • NVIDIA A40 (SR-IOV: 32VF [7])
  • +
  • NVIDIA A30 (SR-IOV: 8VF [8])
  • +
  • NVIDIA A30X
  • +
  • NVIDIA A16 (SR-IOV: 16VF [9])
  • +
  • NVIDIA A10 (SR-IOV: 32VF [10])
  • +
  • NVIDIA A2 (SR-IOV: 16VF [11])
  • +
  • NVIDIA RTX A6000
  • +
  • NVIDIA RTX A5000
  • +
  • Quadro RTX 8000 (SR-IOV: 24 VF [12])
  • +
  • Quadro RTX 8000 passive
  • +
  • Quadro RTX 6000 (SR-IOV: 24 VF [13])
  • +
  • Quadro RTX 6000 passive
  • +
  • Tesla V100
  • +
  • Tesla T4 (SR-IOV: 16VF [14])
  • +
  • Tesla P100
  • +
  • Tesla P40
  • +
  • Tesla P6
  • +
  • Tesla P4
  • +
  • Tesla M60
  • +
  • Tesla M10
  • +
  • Tesla M6
  • +
  • GRID K2 (Citrix XenServer and VMware ESXi only)
  • +
  • GRID K1 (Citrix XenServer and VMware ESXi only)
+

Drivers

+

The most widely used method of enabling Mdev functionality on Nvidia GPUs is via the use of Nvidia's proprietary driver package. +

Nvidia's proprietary Mdev driver supports both SR-IOV as well as software based mediation. The appropriate mode is chosen between the two methods based on hardware architecture. +

+

AMD

+

This section will cover Mdev support on AMD GPUs. +

+

Hardware

+

Supported GPUs: +

+
  • AMD FirePro S7150
  • +
  • AMD Radeon Pro V520 [15]
  • +
  • AMD FirePro W7100 [15]
+

Drivers

+

The open source GIM driver supports AMD Tonga architecture GPUs such as the FirePro S7150 & W7100. +

To make use of the MxGPU GIM driver on modern kernel versions you will require pull request 24. +

Virtualization driver support beyond AMD's Tonga architecture is unclear. +

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Glossary

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From Open-IOV
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Definitions

+

This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +

If you have suggestions on how to improve the glossary you can contribute or join our community discussion thread to make suggestions. +

+

VFIO

+

Kernel.org defines VFIO or Virtual Function Input Output as "an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." [1]

+
A diagram depicting direct VFIO passthrough of a GPU adapter.
+

Mdev

+

Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: "an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." [2]

+
A diagram depicting VFIO Mediated Device interacting with two vGPU guests.
+

Virtual CPU (vCPU)

+

A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.

+

Virtual GPU (vGPU)

+

A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to EUs, or SMs) and/or a partition of the device's Video Random Access Memory (VRAM).

+

IVSHMEM

+

According to QEMU's GitHub repo: "The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR." [3]

+
A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.
+

KVMFR (Looking Glass)

+

looking-glass.io defines Looking Glass as: "an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse." [4]

+
A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.
+

NUMA Node

+

Infogalactic defines NUMA as: "Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." [5]

+
A diagram depicting Non-Uniform Memory Access (NUMA) nodes.
+

Application Binary Interface (ABI)

+

Infogalactic defines an ABI as "the interface between two program modules, one of which is often a library or operating system, at the level of machine code." [6]

+
A diagram contrasting API and ABI as well as their respective roles in software compatibility.
+

SR-IOV

+

docs.microsoft.com defines SR-IOV as "The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." [7]

+
A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.
+

GVT-g

+

wiki.archlinux.org defines Intel GVT-g as "a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." [8]

+
A diagram of Intel's GVT-g (Graphics Virtualization Technology g).
+

VirGL

+
A diagram depicting GPU instruction redirects to a single host graphics driver.

lwn.net defines Virgl as: "a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host." [9]

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Hypervisor Support

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Platform Hypervisor +Virtual GPU support +Memory Sharing APIs +IOMMU Groups support +PCI forwarding +Mdev Support +SR-IOV Support +SIOV Support +
KVM +Yes +IVSHMEM +Yes +Yes (via VFIO) +Yes +Yes +In Development +
Xen +Yes +Grant Tables +No +Yes (via xen-pciback) +No +Yes +Unknown +
NVMM +Unknown +Unknown +No +Unknown +No +Unknown +No +
+ + +

KVM

+

This section will cover existing support in KVM for VFIO-Mdev and ongoing issues with it's existing implementation. +

+

Missing Functionality

+

Nested SR-IOV. +

+

Xen

+

This section will cover efforts to support the Xen hypervisor with open device mediation software. +

XAPI docs for virtual GPUs can be read here. +

+

Mdev drivers outside Dom0

+

Xen Hyperlaunch aims to disaggregate Dom0's monolithic functions. This includes a discrete domain for device drivers. +

+

Missing Functionality

+

IOMMU Groups (discussions around extending or reworking Xen's IOMMU to include IOMMU Groups is ongoing). +

+

Additional Documentation

+

For additional documentation check the XenProject Wiki. +

+

NVMM

+

This section will cover NetBSD's NVMM. +

+

Missing Functionality

+

VFIO. +

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Additional Documentation

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For additional documentation read From Zero to NVMM. +

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Intel

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This page will document points of integration for virtualization in the Intel i915 driver. +

The i915 added SR-IOV feature enablement in this commit (April 26th 2022). Work is ongoing to upstream this code to i915 in the mainline Linux kernel. +

Driver API documentation can be read here: https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html +

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Intel

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This page will document points of integration for virtualization in the Intel i915 driver. +

The i915 added SR-IOV feature enablement in this commit (April 26th 2022). Work is ongoing to upstream this code to i915 in the mainline Linux kernel. +

Driver API documentation can be read here: https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html +

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Introduction

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From Open-IOV
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This page will provide introductory context on where to begin reading. It will aim to give you a sense of primitives or foundational concepts used for GPU Virtualization. +

+ + +

Terminology

+

To get started with basic terminology around IO Virtualization read the Glossary page. This will get you familiar with a few terms and concepts used in IO Virtualization documentation. +

+

Primitives

+

The primitives section will cover a few notes on the basics of virtualizing a GPU or IO device. +

+

PCI BAR

+

PCI-e devices such as GPUs are used for input and output to and from a computer system. This input and output occurs using TLPs or Transaction Layer Packets over the PCI-e packet network. The IO device is presented to the host operating system as BARs or Base Address Registers. +

+

GPU Drivers

+

GPUs need software to communicate from a host computer system to the device - this software is called a GPU Driver and it typically interacts with the device using MMIO or Memory Mapped IO. MMIO is a set of operations used to allow normal CPU instructions to address registers in RAM in order to communicate with the PCI-e device. In the context of virtualization these registers must be presented into the device in a way that the guest operating system expects. Typically this is accomplished using VFIO or Virtual Function IO. VFIO is used for many methods of virtualizing the device including discrete assignment of a physical device, or virtual (partitioned) device assignment created with or without hardware assistance. +

+

IOMMU

+

MMU or Memory Management Units handle hardware enforced access to memory paging in computer systems. In the context of virtualized MMIO (Memory Mapped Input Output) devices an MMU is required to hardware enforce access to virtual devices (a Memory Management Unit for Input Output is known as an IOMMU). In the case of VFIO, groups of IOMMU devices (IOMMU Groups) are used to control access to the device. These IOMMU Groups often represent individual devices or sub-devices (in the context of Unassisted Virtualization (VFIO-Mdev), Hardware-Assisted Virtualization (SR-IOV), or Hardware-Assisted Paravirtualization) which may be bound to a VFIO bus driver (such as vfio-pci) which results in a VFIO Group (unit of ownership). +

+

Virtualization vs. Paravirtualization

+

Virtualization provides support for unmodified guest software or drivers in the context of GPUs. +

Paravirtualization provides support for "enlightened" guests or modified software which is aware of virtualization. +

+

Unassisted vs. Assisted

+

Similar to virtualization on CPUs with tools like Xen, IO devices can be virtualized on different kinds of computer hardware. Some devices provide hardware virtualization assistance (such as HVM mode in Xen) and some do not (such as PV mode in Xen), as a result an appropriate mode should be used depending on the availability of assistance. +

+

Further Reading

+

This section will cover what you should read to obtain more information about virtualization. +

+

Virtualization Fundamentals

+

The Virtualization Fundamentals article provides links to some of the foundational work which underly modern virtualization industry and development today. If you'd like to understand both the theories on which virtualization builds as well as the history of industry you should read several articles here. Notable Popek and Goldberg Virtualization Requirements as well as Xen and the Art of Virtualization provide a great foundations-first approach to learning about virtualization. +

+

Virtual I/O Internals

+

The Virtual I/O Internals article provides a detailed look into the interface layers between IO driver internals, the hypervisor, and the guest OS. This is a great article to read if you'd like to better understand how virtual machines can interact with both discretely assigned devices as well as those which have been partitioned using software or firmware. +

+

GPU Driver Internals

+

The GPU Driver Internals article provides information on how GPU drivers are structured internally as well as how they achieve virtualization. This includes high level architecture, device initialization, as well as memory mapping, and scheduling. +

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Glossary

+
+
From Open-IOV
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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Definitions

+

This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +

If you have suggestions on how to improve the glossary you can contribute or join our community discussion thread to make suggestions. +

+

VFIO

+

Kernel.org defines VFIO or Virtual Function Input Output as "an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." [1]

+
A diagram depicting direct VFIO passthrough of a GPU adapter.
+

Mdev

+

Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: "an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." [2]

+
A diagram depicting VFIO Mediated Device interacting with two vGPU guests.
+

Virtual CPU (vCPU)

+

A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.

+

Virtual GPU (vGPU)

+

A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to EUs, or SMs) and/or a partition of the device's Video Random Access Memory (VRAM).

+

IVSHMEM

+

According to QEMU's GitHub repo: "The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR." [3]

+
A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.
+

KVMFR (Looking Glass)

+

looking-glass.io defines Looking Glass as: "an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse." [4]

+
A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.
+

NUMA Node

+

Infogalactic defines NUMA as: "Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." [5]

+
A diagram depicting Non-Uniform Memory Access (NUMA) nodes.
+

Application Binary Interface (ABI)

+

Infogalactic defines an ABI as "the interface between two program modules, one of which is often a library or operating system, at the level of machine code." [6]

+
A diagram contrasting API and ABI as well as their respective roles in software compatibility.
+

SR-IOV

+

docs.microsoft.com defines SR-IOV as "The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." [7]

+
A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.
+

GVT-g

+

wiki.archlinux.org defines Intel GVT-g as "a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." [8]

+
A diagram of Intel's GVT-g (Graphics Virtualization Technology g).
+

VirGL

+
A diagram depicting GPU instruction redirects to a single host graphics driver.

lwn.net defines Virgl as: "a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host." [9]

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LIME Is Mediated Emulation

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LIME Is Mediated Emulation is an in-development feature in which enables the execution of full performance Win64 binaries with full compatibility for all current and future software making use of the Windows ABI. An initial demo of this technology can be viewed here. +

+ + +

Design Goals

+

LIME aims to provide similar functionality to WINE Is Not Emulation, Valve's Proton / DXVK but with the use of graphics virtualization (vGPU/SR-IOV on consumer GPUs), a shared filesystem between host/guest, and KVM Frame Relay (high performance graphics buffer sharing via Inter-VM Shared Memory Device / IVSHMEM). +

Compared to WINE, and Proton the benefits of this approach are that Win64 binaries execute without the incompatibilities introduced in new games taking advantage of the latest version of DirectX, or when changes are introduced to the latest version of the Win64 ABI. +

This functionality is enabled via the use of GPU Virtual Machine (for consumer GPU Virtualization), VirtIO-FS (for host <-> guest filesystem sharing), Looking Glass (for host <-> guest shared frame buffer), and (for orchestration). +

+

Use-Cases

+

Win64 Subsystem

+

LIME's most immediate use case is around ABI compatibility with Win64 programs in environments without native support. +

A blog post detailing the problems which lead to this work can be read here. A summary of this post is traditional models for backwards compatibility with Application Binary Interfaces (ABIs) lock-in existing models for kernel/userland development and stagnate architectural innovation. On the other hand consumer oriented systems like those based on Darwin/XNU break backwards compatibility with user programs version to version of the system in order to introduce architectural improvements in the kernel / userland (for instance micro-service device drivers which may recover from faults at OS runtime). +

These two approaches might be considered two discretely separable models for software development 'enterprise' /'consumer' - LIME might then be considered a third approach which preserves the functions of both prior approaches (continual innovation afforded in the kernel-space and backwards compatibility with existing software libraries). +

ie: A method by which programs "import" a particular explicitly versioned ABI similar to how Docker provisions chroot resources like configuration files and support libraries, but extended to drivers, and the kernel. +

+

Win64 Orchestration

+

Because LIME necessarily provisions application data, program files, and NUMA-aware vCPU/vGPU resources (in the context of multi-GPU, multi-socket CPU systems) through for automatic execution by one or more VM guests LIME might provide an ideal architecture for orchestration of Win64 applications at scale. This could include execution of programs for game streaming in a server environment, or multiple applications in a single user environment for 'seamless-mode' execution of guest programs similar to that of QubesOS with hardware GPU acceleration added. +

+

Compatibility With Other ABIs

+

To solve the problems of 'ABI lock-in' discussed in the "Why Computers Suck" post it may be possible to port LIME support to multiple different guest operating systems allowing execution of any program with any ABI with near indistinguishable performance compared to native execution. +

+

Quality of Service (QoS)

+

VFIO-Mdev functionality like that used in GPU Virtual Machine (GVM) provides granular GPU resource allocation and load balancing functions similar to those seen in control groups (cgroups) as they are commonly applied today to RAM and CPU resources. In the context LIME VFIO-Mdev could be applied for load balancing of individual processes running in a virtualized state to ensure individual processes making use of the GPU cannot deny service to others on the system. +

+

Development Status

+

Development of this functionality is ongoing. Efforts to improve LIME are primarily focused on stabilization of shared filesystem functions. +

+

VirtIO-FS

+

VirtIO-FS provides shared filesystem functionality between host and guest using FUSE which is ideal for LIME, however in the context of Windows guests the C version of virtiofsd appears unstable (seen in virtio-win issue 550 [closed], 723 [closed], 724 [open]). Testing has been performed by members of the Open-IOV community which have shown initial signs of increased filesystem stability under continuous read/write loads using the Rust version of virtiofsd (virtiofsd-rs). +

While many programs can be stored in the VirtIO-FS shared directory some programs such as Steam don't want to install programs into the VirtIO-FS drive (seen as a secondary drive in Windows - in often as disk D:/ if no additional media is attached). This game installation behaviour (which drive the user may place their programs in) may not be in common with other game stores such as the Epic Games Store, or Good Old Games (GOG). +

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Looking Glass KVMFR

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Looking Glass is an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse. +

+

Looking Glass Memory Protocol (LGMP)

+

LGMP is an Inter-VM Shared Memory Device (IVHSMEM) based memory sharing protocol for the KVM Frame Relay use-case (sharing of MMIO memory for use by GPU drivers between host and guest). +

+

Xen Support

+

It may be possible to port the Looking Glass Memory Protocol to Xen by substituting the use of the Grant Table memory sharing primitive in place of the IVSHMEM memory sharing primitive. +

+
A diagram depicting how Looking Glass memory device may be redirected over the network via Remote Direct Memory Access (RDMA).
+

Telescope

+

The LGMP protocol may also be extended over a high bandwidth network using the Telescope Looking Glass Proxy. +

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Mdev-GPU

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This page makes use of terms that are defined in the Open-IOV Glossary. If you're curious what a given term means you can check there for a definition. +


+

This page will be used to document the Mdev-GPU API as well as provide an overview of the internals of the Mdev-GPU package. +

Mdev-GPU's source code can be found here. +

+Module docs can be found here.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Compilation

+

Compiling Mdev-GPU from source is very simple however it can take a long time to complete (10 minutes for existing sources). +

If you'd like to compile Mdev-GPU yourself you can do so by cloning the repo and running the following two commands from within the repository directory: +

curl -sSL https://get.haskellstack.org/ | sh +

stack install +

These commands will generate all binaries provided by Mdev-GPU under the path ~/.local/bin/. +

If you would prefer not to wait for the program to compile you can find pre-compiled x86_64 binaries under the Releases section of the repository on GitHub. +

+

Installation

+

The binaries compiled on your local machine by Stack in the ~/.local/bin/ path or downloaded from Releases on GitHub should be copied to /usr/bin/. This can be accomplished both via install script (currently testing in ) or via management layer-agnostic package. +

+

Mdev-GPU Configuration

+

The Mdev-GPU repository provides Systemd service and example configurations for Mdev-CLI in the /etc/ folder. On installation the directories & files contained in the repository's /etc/ folder should be copied to the absolute path /etc/ on the user's computer. +

+

Systemd

+

GVM/Mdev-GPU exposes several of it's functions as Systemd services. +

As of the 0.1.0.0 release the following Systemd services are available: +

+
  • mdev-post.service
+
mdev-post.service
+

As the name would suggest mdev-post.service posts the GPU(s) in a state where they are ready to be virtualized. When the service is invoked the mdev-cli util registers Mdev callbacks and supported mediated device (Mdev) types with the Mediated Core according to the user's specified configuration at /etc/gvm/mdev-gpu/generate-vgpu-types.yaml. If you'd like to place your configuration file elsewhere and still have your configuration invoked on boot you can edit the systemd service ExecStart= line to specify an alternative path. +

+

Mdev-CLI

+

Configuration for Mdev-GPU can be found in the path /etc/gvm/mdev-gpu/. This path will by default contain several vendor-specific folders which may include configuration examples for various devices/architectures as well as the file generate-vgpu-types.yaml which you can configure to specify your desired Virtual GPU (vGPU) / VFIO-Mdev topologies as they are presented in the sysfsdev mdev_bus path and as seen by tools such as mdevctl. Once you have configured the available types your liking you can refresh the supported types registered with the Mediated Core by rebooting your machine or reloading the vendor driver kernel module then restarting mdev-post.service or by invoking mdev-cli. +


+The available yaml properties which may be specified in /etc/gvm/mdev-gpu/generate-vgpu-types.yaml are shown below. Note that fields with the [required] tag must be specified in the yaml file whereas fields with the [optional] tag may be omitted from configuration if you would prefer to rely upon default parameters instead. +

+
num
+

[required] +

num refers to the Mediated Device (Mdev) type number. This value specifies the profile's numerical identifier in the sysfsdev mdev_bus path. +

+
vDevId
+

[optional] +

The vGPU (Virtual GPU) PCI Device ID which should be presented to the guest. +

+
pDevId
+

[optional] +

The pGPU (Physical GPU) PCI Device ID which should be presented to the host. +

+
name
+

[optional] +

The GPU name presented to the guest. +

+
gpuClass
+

[optional] +

The class of GPU to use. +

available strings: +

"Compute" +

"Graphics" +

+
maxInstances
+

[required] +

maxInstances refers to the maximum number of instances available of any given Mediated Device (Mdev) profile. This number can be configured arbitrarily however it should ideally not be set to a value which allows for fbLen/fbRes values that allow a number of Mdev devices to be created which would exceed your device's available VRAM. +

+
virtDisplay
+

[optional] +

virtDisplay controls the topologies of virtual displays. virtDisplay exposes the following user configurable properties: +

+
numHeads
+

[optional] +

Number of heads [virtual monitors] available for each Mediated Device (Mdev). +

+
maxResX
+

[optional] +

Maximum width of the mediated display. +

+
maxResY
+

[optional] +

Maximum height of the mediated display. +

+
frlConfig
+

[optional] +

Frame rate limiter for the mediated display. +

+
frlEnable
+

[optional] +

Do we enable frame rate limiting or not? +

+
ecc
+

[optional] +

ecc refers to if error correcting memory should be used. +

+
fbLen
+

[required] +

fbLen is the framebuffer length (in megabytes). +

+
fbRes
+

[required] +

fbRes is the framebuffer reserved by the hypervisor (in megabytes). In most circumstances this value should scale to around 1/7th the size of your chosen fbLen value. +

+
mapVideoSize
+

[optional] +

Mappable video size in MBs, 24 by default. +

+
encCap
+

[optional] +

Percentage we use the NvEnc hardware. +

+
bar1Len
+

[optional] +

bar1Len refers to the size of the Base Address Registers for BAR1 (MSI) as presented by the VFIO File Descriptor. +

+ + + + +
+
+ +
+
+ +
+

Navigation menu

+
+ + +
+ + + + +
+
+ + + + + + +
+
+ + + +
+ + + + + \ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Mediated_Device_Internals.html b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html new file mode 100644 index 0000000..fb28c2e --- /dev/null +++ b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html @@ -0,0 +1,1014 @@ + + + + +Virtual I/O Internals - Open-IOV + + + + + + + + + + + + +
+
+
+ +
+
+
+

Virtual I/O Internals

+
+
From Open-IOV
+
(Redirected from Mediated Device Internals)
+
+ +
+ Jump to navigation + Jump to search +

The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
  • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
  2. +
  3. mdpy-fb.c
  4. +
  5. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
  2. +
  3. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
  4. +
  5. [2017] Scalable I/O Virtualization by Kevin Tian
  6. +
  7. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
  8. +
  9. Scalable I/O Virtualization Revision 1.0
  10. +
  11. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
  12. +
  13. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
  14. +
  15. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
  16. +
  17. IOCTL
  18. +
  19. eventfd - root/virt/kvm/eventfd.c
  20. +
  21. (kernel diff:: KVM: irqfd)
  22. +
  23. (kernel diff:: KVM: add ioeventfd support)
  24. +
  25. KVM irqfd & ioeventfd
  26. +
  27. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
  28. +
  29. VFIO Mediated Devices
  30. +
  31. IOMMU Aware Mediated Device
  32. +
  33. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
  34. +
  35. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
  36. +
  37. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
  38. +
  39. Auxiliary Bus
  40. +
  41. Shared Virtual Addressing
  42. +
  43. vfio.blogspot.com
  44. +
  45. XenGT by Kevin Tian
  46. +
  47. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
  48. +
  49. PCI SIG I/O Virtualization
  50. +
  51. VMGL by the University of Toronto Computer Science Department
  52. +
  53. Kepler VGX Hypervisor
  54. +
  55. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
  56. +
  57. DMA-Mapping.txt (Dynamic DMA Mapping)
  58. +
  59. KVM MMU Virtualization by Xiao Guangrong
  60. +
  61. OSDEV: PCI
  62. +
  63. Down to the TLP: How PCI express devices talk (Part I)
  64. +
  65. Down to the TLP: How PCI express devices talk (Part II)
  66. +
  67. Intel ACRN: Enabling SR-IOV Virtualization
  68. +
  69. Kernel.org sysfs-bus-pci
  70. +
  71. Linux Kernel Labs: Memory Mapping
  72. +
  73. Inside Windows Page Frame Number (PFN) - Part 1
  74. +
  75. Direct Rendering Infrastructure (DRI)
  76. +
  77. DRI User Guide
  78. +
  79. Linux Kernel Labs: IO Virtualization
  80. +
  81. Gallium3D: Main Page
  82. +
  83. Gallium3D Wiki
  84. +
  85. Gallium3D talk from XDS 2007
  86. +
  87. Memory Management High Level Design (ARCN)
  88. +
  89. Block Architecture Diagrams for Geforce series
  90. +
  91. Block diagrams for 40 series instruction format
  92. +
  93. PCI Configuration Space
  94. +
  95. GPU virtual memory in WDDM 2.0
  96. +
  97. Intel Graphics Programmer's Reference Manuals (PRM)
  98. +
  99. i915: Hardware Contexts (and some bits about batchbuffers)
  100. +
  101. i915: The Global GTT Part 1
  102. +
  103. i915: Aliasing PPGTT Part 2
  104. +
  105. i915: True PPGTT Part 3
  106. +
  107. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
  108. +
  109. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
  110. +
  111. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  112. +
  113. A deep dive into QEMU: PCI slave devices
  114. +
  115. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
  116. +
  117. IOMMU Introduction
  118. +
  119. Arch Wiki: Intel Graphics
  120. +
  121. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
  122. +
  123. Kernel.org: vfio iommu type1: Add support for mediated devices
  124. +
  125. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
  126. +
  127. More Shadow Walker: The Progression of TLB-Splitting on x86
  128. +
  129. MMU Virtualization Via Intel EPT: Technical Details
  130. +
  131. Alex Williamson Github: VFIO Development (tree next)
  132. +
  133. GPU PMU: performance monitoring with perf event
  134. +
  135. Remote Procedure Call (RPC)
  136. +
  137. Virtual Open Systems: API Remoting
  138. +
  139. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
  140. +
  141. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
  142. +
  143. docs.kernel.org: DRM Memory Management
  144. +
  145. docs.kernel.org: PCI Bus Subsystem
  146. +
  147. openglbook.com: What is OpenGL?
  148. +
  149. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
  150. +
  151. Dynamic Mediation for Live Migration VFIO-PCI
  152. +
  153. DRM Management Via CGroups
  154. +
  155. DRM: Add GEM ("graphics execution manager") to i915 driver.
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Merged Drivers

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The following page will provide specifications and details on the current state of host DRM + VFIO-Mdev drivers in support of various vendors. +

In the context of this page the term "Merged Driver" refers to drivers which allow simultaneous acceleration of the host using a device's PF (Physical Function) and acceleration of guests using one or more VFs (Virtual Functions) created using the same device. +

+Merged functionality is currently supported for drivers which both make use of VFIO-Mdev and SR-IOV functionality depending on the vendor and driver implementation.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Intel i915

+
Intel's slides mention the ability to accelerate up to '8 VMs plus DOM0'. Source: https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf
+

Intel currently supports host DRM and VFIO-Mdev/SR-IOV functionality in it's current i915 driver sources (VFIO-Mdev/GVT-g) and upstreaming i915 driver sources (VFIO-Mdev/SR-IOV). +

+

Known Issues

+
  1. SR-IOV functionality is undocumented in the i915 driver API documentation.
    Confirmed affected versions: *
    A diagram depicting i915's shared host + VFIO-Mdev driver model.
+

Resolved Issues

+
  1. Multiplexing functionality requires use modified KVM and Xen hypervisors (KVMGT/XenGT).
    Confirmed affected versions:
    current i915 driver sources (GVT-g)
    Fixed in:
    upstreaming i915 driver sources (SR-IOV)
+

Nvidia

+

Known Issues

+
  1. Power management on laptops running mediated graphics functionality may causes graphical errors when not plugged in to AC power.
    Confirmed affected versions: 460.32.01, 460.73.04
    Possible mitigation: lore.kernel.org: "vfio/pci: Change the PF power state to D0 before enabling VFs"
  2. +
  3. VFIO-vmalloc errors may occur as a result of page collisions between host & guest on GPUs with smaller VRAM frame buffer sizes.
    Confirmed affected versions: 460.32.01, 460.73.04
  4. +
  5. Mdev service daemons may crash or load incorrectly requiring a service restart or reboot during host runtime.
    Confirmed affected versions: 460.32.01, 460.73.04, 510.xx.xx
  6. +
  7. Guest drivers fail to initialize correctly when VFIO-Mdev devices are mixed with some VFIO passthrough'd USB hubs.
    Confirmed affected versions: 460.73.01
+

Resolved Issues

+
  1. Upon executing QEMU mdev device initialization for a second Mdev an IOMMU group binding error occurs in QEMU preventing the device from being brought up.
    Confirmed affected versions: 460.32.01, 460.73.04
    Fixed in: 510.xx.xx
+

Module Configuration

+

Depending on your use-case the use of some additional parameters when booting the system may be helpful. +

Here is a list of some parameters which may be used when loading the module via GRUB or Systemd-boot. +

+ + + + + + + + + + + + + +
Module Parameters +
Parameter +Description +Side-Effects +
cudahost=1 +Allows use of CUDA on the host system. +Windows guests may fail. +
nvidia.vgpukvm=0 +Disables GPU virtualization on the host. + +
+

AMDGPU

+

At this time AMDGPU does not currently support VFIO-Mdev functionality. It may be possible to incorporate Mdev Mode mediated device support similar to those functions in nvidia.ko and i915.ko in the Linux kernel's AMDGPU driver sources to produce a driver suitable for merged host+guest DRM for use with AMD GPU devices. +

+

Known Issues

+
  1. Host DRM does not work alongside guest VFIO-Mdev.
    Confirmed affected versions: *
  2. +
  3. The amdgpu kernel module doesn't contain hooks for guest signalling via irqfd & ioeventfd used for VFIO-mdev callbacks.
    Confirmed affected versions: *
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Open-IOV:About

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An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization.  +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

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OpenRM

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OpenRM refers to the open sourcing of the NVIDIA kernel module for Linux, specifically the RM Core or the internal resource manager. +

+Through the open sourced code (located here) we have been able to deduce 7 top level APIs that are being exposed to the Linux developers.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Interaction With OpenRM

+

All of OpenRM is a high scale object oriented abstraction layer for the GPU, all resources are internally classes which have control definitions (methods) on how you can use them. These classes can also represent physical resources or engines. +

+

Alloc (Client)

+

This is analogous to calling an object constructor in a higher level programming language, such as C#. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
  2. +
  3. hObjectParent - Parent of the resource we are allocating.
  4. +
  5. hObjectNew - New object to allocate.
  6. +
  7. hClass - Class of the object we are dealing with.
  8. +
  9. pAllocParams - Pointer to values passed into the constructor call.
  10. +
  11. status - Status of the constructor call (did it succeed or fail)
+

Alloc Memory 64

+

This creates a CPU's mapping to a resource. +

The data for this call requires the following components: +

+
  1. hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).
  2. +
  3. hObjectParent - Parent of the resource we create the CPU mapping to.
  4. +
  5. hObjectNew - Mapping object resource id.
  6. +
  7. hClass - Class of the mapped object.
  8. +
  9. flags - Flags to use on the mapped object.
  10. +
  11. pMemory - pointer for the memory to map.
  12. +
  13. pLimit - Edge of memory map.
  14. +
  15. status - Status of the constructor call.
+

NOTE: Seems to be deprecated. +

+

Control

+

This is a control command which is analogous to calling a method on a class. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
  2. +
  3. hObject - Object id.
  4. +
  5. cmd - Method to call.
  6. +
  7. params - Parameters into this method.
  8. +
  9. paramsSize - Size of the params.
  10. +
  11. status - Status of the control call.
+

NOTE: The control will overwrite the object we pass in over the params pointer. +

+

Dup Object

+

Duplicates the object, or clones the object, which is a deep copy. This procedure can be used across processes in order to produce shared memory. +

The data for this call requires the following components: +

+
  1. hClient - RM Client Id.
  2. +
  3. hParent - Parent of the object.
  4. +
  5. hObject - Object destination for duplicating.
  6. +
  7. hClientSrc - Client source id.
  8. +
  9. hObjectSrc - Object source.
  10. +
  11. flags - Flags to use.
  12. +
  13. status - Status of the duplication.
+

Free

+

Frees an object from the object tree. +

The data for this call requires the following components: +

+
  1. hRoot - Client Id.
  2. +
  3. hObjectParent - Parent of the object.
  4. +
  5. hObjectOld - Object to call the destructor on.
  6. +
  7. status - Status of the free.
+

Vid Heap Control

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Map Memory

+

This seems to be the same as alloc memory but seems to be used more often. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hDevice - Device id.
  4. +
  5. hMemory - Memory resource.
  6. +
  7. offset - Offset of the memory.
  8. +
  9. length - Length of the memory.
  10. +
  11. pLinearAddress - Pointer for returned address.
  12. +
  13. status - Status of the map memory.
  14. +
  15. flags - Flags to use.
+

Unmap Memory

+

This unmaps the CPU memory mapping from the resource. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hDevice - Device Id.
  4. +
  5. hMemory - Memory Id.
  6. +
  7. pLinearAddress - pointer to virtual address.
  8. +
  9. status - Status of the unmap command.
  10. +
  11. flags - Flags to use.
+

Alloc Context DMA 2

+

Allocates a context for DMA. +

The data for this call requires the following components: +

+
  1. hObjectParent - Object parent.
  2. +
  3. hSubDevice - Sub device to allocate on.
  4. +
  5. hObjectNew - Context id.
  6. +
  7. hClass - Type of class.
  8. +
  9. flags - Flags to use.
  10. +
  11. selector - UNKNOWN.
  12. +
  13. hMemory - Handle for Memory resource to DMA map.
  14. +
  15. offset - Offset for the DMA mapping.
  16. +
  17. limit - Limit of the DMA map.
  18. +
  19. status - Status of the allocation.
+

NOTE: Seems to be deprecated. +

+

Map Memory DMA

+

Map a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hDevice - Device Id.
  4. +
  5. hDma - DMA Id.
  6. +
  7. hMemory - Memory Id.
  8. +
  9. offset - Offset of the region.
  10. +
  11. limit - Limit of the region.
  12. +
  13. flags - flags to use.
  14. +
  15. dmaOffset - Offset of the mapping.
  16. +
  17. status - Status of the map Memory DMA.
+

Un-map Memory DMA

+

Unmaps a region of memory for DMA access. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hDevice - Device Id.
  4. +
  5. hDma - DMA handle.
  6. +
  7. hMemory - Memory handle.
  8. +
  9. flags - Flags to use.
  10. +
  11. dmaOffset - DMA Offset to unmap.
  12. +
  13. status - Status of the unmap Memory DMA.
+

Bind Context DMA

+

Binds a context for DMA interaction to a channel. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hChannel - Channel Id.
  4. +
  5. hCtxDma - Context for DMA Id.
  6. +
  7. status - Status of the bind context DMA.
+

NOTE: Seems to be deprecated. +

+

Share

+

Sharing of a resource between multiple clients. +

TODO: Understand this sharing more. +

The data for this call requires the following components: +

+
  1. hClient - Client Id.
  2. +
  3. hObject - Resource Id.
  4. +
  5. sharePolicy - Share policy.
  6. +
  7. status - Status of sharing.
+

Add VBlank Callback

+

TODO: Figure out what this does. +

NOTE: Seems to be deprecated. +

+

Engines

+

There are engines which internally act as classes inside the OpenRM driver. +

These classes have a few key components that make them unique. +

+

Table of Engines

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Engines +
Engine +Description +
Invalid +Does not exist. +
Software +Abstraction layer for software processes inside the OS Software. +
GPU +Interaction layer with the GPU. +
Falcon +Interaction with the Falcon on the GPU. +
Master Control +Unknown. +
Kernel Master Control +Interaction with the PMC.[1] +
Private Ring +Interaction with a private messaging ring. +
Software Interrupt +Interaction with software interrupts. +
Memory System +Interaction with the memory system. +
Kernel Memory System +Interaction with the kernel memory system. +
Memory Manager +Interaction with the memory management system. +
FBFlcn +Interaction with the FBFlcn subsystem. +
TMR +Interaction with the TMR on specific chips. +
DMA +Interaction with a GPU's DMA access. +
Kernel FIFO +First in First out queue in the GPU driver. +
FIFO +Interaction with a generic FIFO. +
OS +Interaction with the OS. +
BUS +PCI Bus interaction +
Kernel BUS +Internal module BUS. +
INFOROM +Interaction with the INFOROM Region on the GPU. +
PERF +Unknown. +
Kernel PERF +Unknown. +
BIF +Unknown. +
Kernel BIF +Unknown. +
SF +Unknown. +
GPIO +Interaction with GPIO. +
CLK +Clock manager system. +
Kernel Display +Kernel Display system. +
DISP +Display system. +
DPU +Data Processing Unit. +
+ +
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vGPU_Unlock is a project created by Jonathan Johansson, available on GitHub. +

The project is designed to allow Nvidia's enterprise GPU virtualization technology to run on consumer Nvidia graphics cards (ex: GeForce GTX series). +

Since its inception, there have been several forks of the project that are more up to date and more performant (ex: Rust version). +

Documentation for the original project is available here. +

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Virtual I/O Internals

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The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
  • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
  2. +
  3. mdpy-fb.c
  4. +
  5. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
  2. +
  3. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
  4. +
  5. [2017] Scalable I/O Virtualization by Kevin Tian
  6. +
  7. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
  8. +
  9. Scalable I/O Virtualization Revision 1.0
  10. +
  11. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
  12. +
  13. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
  14. +
  15. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
  16. +
  17. IOCTL
  18. +
  19. eventfd - root/virt/kvm/eventfd.c
  20. +
  21. (kernel diff:: KVM: irqfd)
  22. +
  23. (kernel diff:: KVM: add ioeventfd support)
  24. +
  25. KVM irqfd & ioeventfd
  26. +
  27. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
  28. +
  29. VFIO Mediated Devices
  30. +
  31. IOMMU Aware Mediated Device
  32. +
  33. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
  34. +
  35. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
  36. +
  37. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
  38. +
  39. Auxiliary Bus
  40. +
  41. Shared Virtual Addressing
  42. +
  43. vfio.blogspot.com
  44. +
  45. XenGT by Kevin Tian
  46. +
  47. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
  48. +
  49. PCI SIG I/O Virtualization
  50. +
  51. VMGL by the University of Toronto Computer Science Department
  52. +
  53. Kepler VGX Hypervisor
  54. +
  55. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
  56. +
  57. DMA-Mapping.txt (Dynamic DMA Mapping)
  58. +
  59. KVM MMU Virtualization by Xiao Guangrong
  60. +
  61. OSDEV: PCI
  62. +
  63. Down to the TLP: How PCI express devices talk (Part I)
  64. +
  65. Down to the TLP: How PCI express devices talk (Part II)
  66. +
  67. Intel ACRN: Enabling SR-IOV Virtualization
  68. +
  69. Kernel.org sysfs-bus-pci
  70. +
  71. Linux Kernel Labs: Memory Mapping
  72. +
  73. Inside Windows Page Frame Number (PFN) - Part 1
  74. +
  75. Direct Rendering Infrastructure (DRI)
  76. +
  77. DRI User Guide
  78. +
  79. Linux Kernel Labs: IO Virtualization
  80. +
  81. Gallium3D: Main Page
  82. +
  83. Gallium3D Wiki
  84. +
  85. Gallium3D talk from XDS 2007
  86. +
  87. Memory Management High Level Design (ARCN)
  88. +
  89. Block Architecture Diagrams for Geforce series
  90. +
  91. Block diagrams for 40 series instruction format
  92. +
  93. PCI Configuration Space
  94. +
  95. GPU virtual memory in WDDM 2.0
  96. +
  97. Intel Graphics Programmer's Reference Manuals (PRM)
  98. +
  99. i915: Hardware Contexts (and some bits about batchbuffers)
  100. +
  101. i915: The Global GTT Part 1
  102. +
  103. i915: Aliasing PPGTT Part 2
  104. +
  105. i915: True PPGTT Part 3
  106. +
  107. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
  108. +
  109. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
  110. +
  111. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  112. +
  113. A deep dive into QEMU: PCI slave devices
  114. +
  115. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
  116. +
  117. IOMMU Introduction
  118. +
  119. Arch Wiki: Intel Graphics
  120. +
  121. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
  122. +
  123. Kernel.org: vfio iommu type1: Add support for mediated devices
  124. +
  125. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
  126. +
  127. More Shadow Walker: The Progression of TLB-Splitting on x86
  128. +
  129. MMU Virtualization Via Intel EPT: Technical Details
  130. +
  131. Alex Williamson Github: VFIO Development (tree next)
  132. +
  133. GPU PMU: performance monitoring with perf event
  134. +
  135. Remote Procedure Call (RPC)
  136. +
  137. Virtual Open Systems: API Remoting
  138. +
  139. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
  140. +
  141. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
  142. +
  143. docs.kernel.org: DRM Memory Management
  144. +
  145. docs.kernel.org: PCI Bus Subsystem
  146. +
  147. openglbook.com: What is OpenGL?
  148. +
  149. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
  150. +
  151. Dynamic Mediation for Live Migration VFIO-PCI
  152. +
  153. DRM Management Via CGroups
  154. +
  155. DRM: Add GEM ("graphics execution manager") to i915 driver.
+ + + + +
+
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Virtual I/O Internals

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From Open-IOV
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The following document details the internals of a VFIO (Virtual Function I/O) driven Shared I/O Device.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+

This article places emphasis on the Virtual GPU (vGPU) use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Comparison of Assistance Modes +
Mdev Mode +SR-IOV Mode +SIOV Mode +
No hardware assistance needed. +Hardware assistance needed. +Hardware assistance needed. +
Host requires insight about guest workload. +Host ignorance of guest workload. +Host requires insight about guest workload. +
Error reporting. +No guest driver error reporting. +Error reporting. +
In depth dynamic monitoring. +Basic dynamic monitoring. +In depth dynamic monitoring. +
Software defined MMU guest separation. +Firmware defined MMU guest separation. +Firmware defined MMU guest separation. +
Requires deferred instructions to be supported by host software (support libraries). +Guest is ignorant of host supported software such as support libraries. + +
Routing interrupts. +Routing interrupts. +Routing interrupts. +
Device reset. +Device reset. +Device reset. +
Enable/Disable device. +Enable/Disable device. +Enable/Disable device. +
Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +Support for multiple scheduling techniques. +
Single PCI requester ID. +Multiple PCI requester IDs. +Multiple PCI requester IDs. +
+ + +

All Modes

+

This section will cover concepts which apply both to Mdev Mode, SR-IOV Mode & SIOV Mode. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Alex Williamson. +

See references 2, 14, & 22 in the References (Talks & Reading Material) section. +

+

Binding VFIO devices

+
Figure 1: VFIO group nodes are unit of ownership that VFIO uses. See slides from: [2]
+
Figure 2: IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: [2]
+
Figure 3: Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: [2]
+
Figure 4: Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: [2]
+

Figure 1: Binding devices to the vfio-pci driver results in VFIO group nodes. +

Opening the file "/dev/vfio/vfio" creates a VFIO Container. +

Figure 2: The interrupt routine IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO group inside the VFIO container. +

+

Programming the IOMMU

+

When this has been done IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU) can then be used to set an IOMMU type for the container which places it in a user interactable state. +

Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +

+

VFIO Memory Mapped IO

+

Figure 3: Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP) for map/pin and IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) for unmap/unpin. +

+

Getting the VFIO Group File Descriptor

+

Figure 4: Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +

+

VFIO device file descriptor

+

VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +

In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +

+ + + + + + + + + + + + + + + + + +
BAR regions in a VGA PCI device. +
00:00.0 VGA compatible controller +
Region 0 Bar0 (Config Space) starts at offset 0 +
Region 1 Bar1 (MSI - Message Signaled Interrupts) +
Region 2 Bar2 (MSIX) +
Region 3 Bar3 +
Region 4 Bar4 +
Region 5 Bar5 (IO port space) +
Expansion ROM +
+

Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +

+ + + + + + + + + + + + + + + +
VFIO representation of PCI BAR regions offsets. +
<- File Offset -> +
0 -> A +A -> (A+B) +(A+B) -> (A+B+C) +(A+B+C) -> (A+B+C+D) +... +
Region 0 (size A) +Region 1 (size B) +Region 2 (size C) +Region 3 (size D) +... +
+

VFIO Interrupts

+

Guests communicate with the host via VFIO Interrupt Requests (IRQs). These are sent via an irqfd (IRQ File Descriptor). Similarly, the host receives these interrupts via eventfd (Event File Descriptor). The resulting data can be returned via a callback. +

+

IRQs

+

Device properties discovered via interrupt (IOCTL). +

+
Get Device Info
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_INFO +
struct vfio_device_info +
+argz + +
flags + +
+VFIO_DEVICE_FLAGS_PCI +
VFIO_DEVICE_FLAGS_PLATFORM +
VFIO_DEVICE_FLAGS_RESET +
num_irqs + +
num_regions + +
+

The IRQ VFIO_DEVICE_GET_INFO can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get Region Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_REGION_INFO +
struct vfio_region_info +
+argz + +
cap_offset + +
flags + +
+VFIO_REGION_INFO_FLAG_CAPS +
VFIO_REGION_INFO_FLAG_MMAP +
VFIO_REGION_INFO_FLAG_READ +
VFIO_REGION_INFO_FLAG_WRITE +
index + +
offset + +
size + +
+

Once the interrupt user knows the number of regions within a VFIO device they can use IRQ VFIO_DEVICE_GET_REGION_INFO to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +

The upstream API can be read here (vfio.h). +

Sample mdev code to service this request can be found here, and here. +

+
Get IRQ Info
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_GET_IRQ_INFO +
struct vfio_irq_info +
+argz + +
count + +
flags + +
+VFIO_IRQ_INFO_AUTOMASKED +
VFIO_IRQ_INFO_EVENTFD +
VFIO_IRQ_INFO_MASKABLE +
VFIO_IRQ_INFO_NORESIZE +
index + +
+

VFIO_DEVICE_GET_IRQ_INFO is used to retrieve information about a device IRQ. +

VFIO_IRQ_INFO_AUTOMASKED is used to mask interrupts when they occur to protect the host. +

The upstream API can be read here (vfio.h) +

Sample mdev code to service this request can be found here, and here. +

+
Set IRQs
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
VFIO_DEVICE_SET_IRQS +
struct vfio_irq_set +
+argz + +
count + +
data[] + +
flags + +
+VFIO_IRQ_SET_ACTION_MASK +
VFIO_IRQ_SET_ACTION_TRIGGER +
VFIO_IRQ_SET_ACTION_UNMASK +
VFIO_IRQ_SET_DATA_BOOL +
VFIO_IRQ_SET_DATA_EVENTFD +
VFIO_IRQ_SET_DATA_NONE +
index + +
start + +
+

VFIO_DEVICE_SET_IRQS is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +

The upstream API can be read here (vfio.h). +

+

Device Decomposure/Recomposure

+
Figure 5: Device Decomposure and Recomposure via VFIO.
Figure 5: Device Decomposure and Recomposure via VFIO. See slides from: [2]
+

Figure 5: Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +

+

Memory Management Unit (MMU)

+
Error creating thumbnail: File missing
Figure 6: MMU - GMMU IOVA translation/isolation.
+

Figure 6: This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +

+

MMIO Isolation (Platform MMU)

+

The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in Random Access Memory (RAM). MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +

+

VRAM Isolation (GPU GMMU)

+

The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard Video Random Access Memory (VRAM). Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +

+

Platform MMIO <-> GPU Shadow Pages

+

In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +

+
Figure 7: A depiction of region overlays within a VFIO file descriptor.
Figure 7: A depiction of region overlays within a VFIO file descriptor. See slides from: [2]
+

VFIO Quirks (region traps)

+

Figure 7: Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +

+
Peer-to-Peer DMA Isolation under IOMMU
Figure 8: Peer-to-Peer DMA Isolation under IOMMU. See slides from: [2]
+

Known IOMMU Issues

+

DMA Aliasing +

+
  • Not all devices generate unique IDs.
  • +
  • Not all devices generate IDs they should.
+

DMA Isolation +

+
  • Figure 8: Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.
+
Figure 0: Approches to GPU Virtualization.
Figure 0: Approaches to GPU Virtualization. See slides from: [61]
+

Mdev Mode

+

Mdev Mode (VFIO Mediated Device) is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +

See references 1, 7, 8, 17, 18, 19, 70 in the References (Talks & Reading Material) section. +

+

Mediated Core

+

The mediated device framework made 3 major changes to the VFIO driver. +

+ +

The full list of these changes can be seen in the lists.gnu.org Qemu-devel mailing list archive. +

+

Device Initialization

+

This section will deal with how an Mdev driver is initialized. +

Sample mdev code for device initialization can be found here. +

+

Registering VFIO MDEV as a driver

+

VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +

+

Registering PCIE Device with the Mediated Core

+
Registering the mediated device.
Figure 9: Registering the mediated device. This step may be accomplished via the vendor driver or via GVM/Mdev-GPU for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.
+

Figure 9: The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Registering Mediated Callbacks (CBs)

+

Figure 9: The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the GVM Project's Mdev-GPU component to accomplish this step on behalf of the vendor driver. +

+

Creating a Mediated Device via mdev-sysfsdev API

+
Figure 10: Echoing a UUID into the mdev-sysfsdev API. This functionality is included in mdevctl and in . See slides from: [1]
+

Figure 10: The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +

+
Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor.
Figure 11: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: [1]
+

QEMU adds VFIO device to IOMMU container-group

+

Figure 11: When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +

+

QEMU passes mdev device file descriptor to VM

+
Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine.
Figure 12: QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: [1]
+

Figure 12: Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +

+

Instruction Execution

+
Figure 13: A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From blog.allenx
+

Figure 13: Mdev Mode moves instruction information across a virtual function (VF) device using Remote Procedure Calls generally by way of software interrupt (IOCTL). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the Interrupt Request File Descriptor (irqfd) and IO Event File Descriptor (ioeventfd). +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +

+

IRQ remapping

+

Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +

+

Interrupt Injection

+

-- +

--Researching-- +

-- +

+

Memory Management

+

Mdev memory management is handled by vendor driver software. +

+

Region Passthrough

+

Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +

+
Emulated Regions
+

Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as in this sample code. +

+
Passthrough Regions
+

Passthrough memory regions use direct communication requiring no VM-exit (fast). +

+
Region Access
+
Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs
Figure 14: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: [1]
+

Figure 14: QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +

+
Error creating thumbnail: File missing
Figure 15: Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: [1]
+

Figure 15: The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +

+
Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver.
Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: [1]
+

Figure 16: KVM services EPT violation and forwards to QEMU VFIO PCI driver. +

+
Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor.
Figure 17: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: [1]
+

Figure 17: QEMU convert request from KVM to R/W access to Mdev file descriptor. +

+

EPT Page Violations

+

Guest Memory Mapped IO (MMIO) trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the Mdev File Descriptor (FD). Reads and writes are then handled by the host GPU device driver via mediated callbacks (CBs) and VFIO-mdev. +

+

Mediated DMA Translations

+

-- +

--Researching-- +

-- +

Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +

Figure 18: Memory regions get added by QEMU. +

+
Memory Regions Added by QEMU
Figure 18: Memory Regions Added by QEMU. See slides from: [1]
+

Figure 19: QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +

+
QEMU calls VFIO DMA MAP via Memory listener
Figure 19: QEMU calls VFIO DMA MAP via Memory listener. See slides from: [1]
+
Type 1 IOMMU Tracks VA-GFN
Figure 20: Type 1 IOMMU Tracks <VA, GFN>. See slides from: [1]
+

Figure 20: Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +

+

Scheduling

+

Scheduling is handled by the host mdev driver. +

+

Kernel API

+

Kernel documentation used for implementing a VFIO Mediated Device may be found at kernel.org. +

+

Sample Code

+

Sample code for various mdev implementations may be found below: +

Mediated Virtual PCI Display Host Device: +

+
  1. mdpy.c
  2. +
  3. mdpy-fb.c
  4. +
  5. mbochs.c.
+

Serial PCI Port-based Mediated Device: +

+
  1. mtty.c.
+
Compilation
+

To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +

make +

When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +

+
Loading Kernel Modules
+

Now that you have compiled the kernel modules you may load them via the insmod command. +

For example to load the mtty.ko module run the following command from within the directory where you built the modules: +

insmod mtty.ko +

+
Unloading Kernel Modules
+

To unload any of the kernel modules you may make use of the rmmod command. +

For example to unload the mtty.ko module run the following command: +

rmmod mtty.ko +

+
Additional Documentation
+

An additional guide explaining how to make use of the mtty.c sample code may be found at line 308 of the kernel.org VFIO Mediated Device documentation. +

+

Mdev Mode Requirements

+

Driver Support. +

Software HPA<->GPA Boundary Enforcement. +

+

SR-IOV Mode

+

SR-IOV Mode (Single Root I/O Virtualization) involves hardware assisted virtualization on I/O peripherals. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +

See reference 6 in the References (Talks & Reading Material) section. +

+

Instruction Execution

+

SR-IOV communicates instructions from a virtual function (VF) directly to the PCI BAR. +

+

Memory Management

+

Guests are presenting with passthrough memory regions by the device firmware. +

+

Scheduling

+

Scheduling may be handled by the host mdev driver and/or the device firmware. +

+

SR-IOV Mode Requirements

+

Driver Support. +

Device SR-IOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

SIOV Mode

+

SIOV (Scalable I/O Virtualization) involves the combination of concepts form both SR-IOV Mode and Mdev Mode as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +

Revision 1.0 of the SIOV specification can be read on the Open Compute Project website. +

+

Knowledge Resources Used

+

This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +

See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the References (Talks & Reading Material) section. +

+

Memory Management

+

Enhancements to Intel VT-d introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (mdev memory management). This change is referred to as an IOMMU Aware Mediated Device. +

+

IOMMU Aware Mediated Device

+

SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +

The full list of these changes can be seen in the mailing list archive on lwn.net under (vfio/mdev: IOMMU aware mediated device). +

+

Shared Hardware Workqueues

+

SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +

According to kernel.org: "In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function." +

+

SIOV Mode Requirements

+

Driver Support. +

Device SIOV support. +

Firmware HPA<->GPA Boundary Enforcement. +

+

References (Talks & Reading Material)

+
  1. [2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede - slides
  2. +
  3. [2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson - slides
  4. +
  5. [2017] Scalable I/O Virtualization by Kevin Tian
  6. +
  7. [2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu - slides
  8. +
  9. Scalable I/O Virtualization Revision 1.0
  10. +
  11. [2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue - slides
  12. +
  13. [2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel
  14. +
  15. [2016] Qemu Graphics Update 2016 by Gerd Hoffmann
  16. +
  17. IOCTL
  18. +
  19. eventfd - root/virt/kvm/eventfd.c
  20. +
  21. (kernel diff:: KVM: irqfd)
  22. +
  23. (kernel diff:: KVM: add ioeventfd support)
  24. +
  25. KVM irqfd & ioeventfd
  26. +
  27. VFIO - Virtual Function I/O - root/virt/kvm/vfio.c
  28. +
  29. VFIO Mediated Devices
  30. +
  31. IOMMU Aware Mediated Device
  32. +
  33. Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian
  34. +
  35. [2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang
  36. +
  37. [2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian
  38. +
  39. Auxiliary Bus
  40. +
  41. Shared Virtual Addressing
  42. +
  43. vfio.blogspot.com
  44. +
  45. XenGT by Kevin Tian
  46. +
  47. VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman
  48. +
  49. PCI SIG I/O Virtualization
  50. +
  51. VMGL by the University of Toronto Computer Science Department
  52. +
  53. Kepler VGX Hypervisor
  54. +
  55. Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
  56. +
  57. DMA-Mapping.txt (Dynamic DMA Mapping)
  58. +
  59. KVM MMU Virtualization by Xiao Guangrong
  60. +
  61. OSDEV: PCI
  62. +
  63. Down to the TLP: How PCI express devices talk (Part I)
  64. +
  65. Down to the TLP: How PCI express devices talk (Part II)
  66. +
  67. Intel ACRN: Enabling SR-IOV Virtualization
  68. +
  69. Kernel.org sysfs-bus-pci
  70. +
  71. Linux Kernel Labs: Memory Mapping
  72. +
  73. Inside Windows Page Frame Number (PFN) - Part 1
  74. +
  75. Direct Rendering Infrastructure (DRI)
  76. +
  77. DRI User Guide
  78. +
  79. Linux Kernel Labs: IO Virtualization
  80. +
  81. Gallium3D: Main Page
  82. +
  83. Gallium3D Wiki
  84. +
  85. Gallium3D talk from XDS 2007
  86. +
  87. Memory Management High Level Design (ARCN)
  88. +
  89. Block Architecture Diagrams for Geforce series
  90. +
  91. Block diagrams for 40 series instruction format
  92. +
  93. PCI Configuration Space
  94. +
  95. GPU virtual memory in WDDM 2.0
  96. +
  97. Intel Graphics Programmer's Reference Manuals (PRM)
  98. +
  99. i915: Hardware Contexts (and some bits about batchbuffers)
  100. +
  101. i915: The Global GTT Part 1
  102. +
  103. i915: Aliasing PPGTT Part 2
  104. +
  105. i915: True PPGTT Part 3
  106. +
  107. i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)
  108. +
  109. i915: Security of the Intel Graphics Stack - Part 1 - Introduction
  110. +
  111. i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC
  112. +
  113. A deep dive into QEMU: PCI slave devices
  114. +
  115. Debugging QEMU Guests with GDB (start & stop, examine state like registers & memory, set breakpoints & watchpoints)
  116. +
  117. IOMMU Introduction
  118. +
  119. Arch Wiki: Intel Graphics
  120. +
  121. An Introduction to Intel Graphics Virtualization Technology (legacy GVT-g) by Zhi Wang
  122. +
  123. Kernel.org: vfio iommu type1: Add support for mediated devices
  124. +
  125. Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs
  126. +
  127. More Shadow Walker: The Progression of TLB-Splitting on x86
  128. +
  129. MMU Virtualization Via Intel EPT: Technical Details
  130. +
  131. Alex Williamson Github: VFIO Development (tree next)
  132. +
  133. GPU PMU: performance monitoring with perf event
  134. +
  135. Remote Procedure Call (RPC)
  136. +
  137. Virtual Open Systems: API Remoting
  138. +
  139. A Full GPU Virtualization Solution with Mediated Pass-Through by Yiying Zhang, David Cowperthwaite, Kun Tian, and Yaozu Dong - [Paper] - [Video] - [Slides 1] - [Slides 2]
  140. +
  141. [2014] KvmGT: A Full GPU Virtualization Solution by Jike Song
  142. +
  143. docs.kernel.org: DRM Memory Management
  144. +
  145. docs.kernel.org: PCI Bus Subsystem
  146. +
  147. openglbook.com: What is OpenGL?
  148. +
  149. [2020] Getting pixels on screen: introduction to Kernel Mode Setting (KMS) by Simon Ser - slides
  150. +
  151. Dynamic Mediation for Live Migration VFIO-PCI
  152. +
  153. DRM Management Via CGroups
  154. +
  155. DRM: Add GEM ("graphics execution manager") to i915 driver.
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Virtualization Fundamentals

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From Open-IOV
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This following page is intended to index and summarize information related to the fundamentals of virtualization of computer systems.

An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +

This CC-BY-4.0 licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +

+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.

+ + +

Popek and Goldberg Virtualization Requirements

+

The Popek and Goldberg virtualization requirements are a set of conditions sufficient for a computer architecture to support system virtualization efficiently. They were introduced by Gerald J. Popek and Robert P. Goldberg in their 1974 article "Formal Requirements for Virtualizable Third Generation Architectures". Even though the requirements are derived under simplifying assumptions, they still represent a convenient way of determining whether a computer architecture supports efficient virtualization and provide guidelines for the design of virtualized computer architectures. +

+

Goldberg Survey of Virtual Machine Research

+

The complete instruction-by-instruction simulation of one computer system on a different system is a well-known computing technique. It is often used for software development when a hardware base is being altered. For example, if a programmer is developing software for some new special purpose (e.g., aerospace) computer X which is under construction and as yet unavailable, he will likely begin by writing a simulator for that computer on some available general-purpose machine G. The simulator will provide a detailed simulation of the special-purpose environment X, including its processor, memory, and I/O devices. Except for possible timing dependencies, programs which run on the “simulated machine X” can later run on the “real machine X” (when it is finally built and checked out) with identical effect. The programs running on X can be arbitrary — including code to exercise simulated I/O devices, move data and instructions anywhere in simulated memory, or execute any instruction of the simulated machine. The simulator provides a layer of software filtering which protects the resources of the machine G from being misused by programs on X. +

+

Microkernels Meet Recursive Virtual Machines

+

This paper describes a novel approach to providing mod- ular and extensible operating system functionality and en- capsulated environments based on a synthesis of micro- kernel and virtual machine concepts. We have developed a software-based virtualizable architecture called Fluke that allows recursive virtual machines (virtual machines running on other virtual machines) to be implemented ef- ficiently by a microkernel running on generic hardware. A complete virtual machine interface is provided at each level; efficiency derives from needing to implement only new functionality at each level. This infrastructure allows common OS functionality, such as process management, demand paging, fault tolerance, and debugging support, to be provided by cleanly modularized, independent, stack- able virtual machine monitors, implemented as user pro- cesses. It can also provide uncommon or unique OS fea- tures, including the above features specialized for particu- lar applications’ needs, virtual machines transparently dis- tributed cross-node, or security monitors that allow arbi- trary untrusted binaries to be executed safely. Our proto- type implementation of this model indicates that it is prac- tical to modularize operating systems this way. Some types of virtual machine layers impose almost no overhead at all, while others impose some overhead (typically 0–35%), but only on certain classes of applications. +

+

A Comparison of Software and Hardware Techniques for x86 Virtualization

+

Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMwareR Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization. We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution. We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization. +

+

Virtualizing I/O Devices on VMware Workstation’s Hosted Virtual Machine Monitor

+

Virtual machines were developed by IBM in the 1960’s to provide concurrent, interactive access to a mainframe computer. Each virtual machine is a replica of the underlying physical machine and users are given the illusion of running directly on the physical machine. Virtual machines also provide benefits like isolation and resource sharing, and the ability to run multiple flavors and configurations of operating systems. VMware tmWorkstation brings such mainframe-class virtual machine technology to PC-based desktop and workstation computers. This paper focuses on VMware Workstation’s approach to virtualizing I/O devices. PCs have a staggering variety of hardware, and are usually pre-installed with an operating system. Instead of replacing the pre-installed OS, VMware Workstation uses it to host a user-level application (VMApp) component, as well as to schedule a privileged virtual machine monitor (VMM) component. The VMM directly provides high-performance CPU virtualization while the VMApp uses the host OS to virtualize I/O devices and shield the VMM from the variety of devices. A crucial question is whether virtualizing devices via such a hosted architecture can meet the performance required of high throughput, low latency devices. To this end, this paper studies the virtualization and performance of an Ethernet adapter on VMware Workstation. Results indicate that with optimizations, VMware Workstation’s hosted virtualization architecture can match native I/O throughput on standard PCs. Although a straightforward hosted implementation is CPU-limited due to virtualization overhead on a 733 MHz PentiumR III system on a 100 Mb/s Ethernet, a series of optimizations targeted at reducing CPU utilization allows the system to match native network throughput. Further optimizations are discussed both within and outside a hosted architecture. +

+

Dynamic binary translation and optimization

+

We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach o�ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime pro�le information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system, and their impact on �nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage. Keywords| dynamic compilation, binary translation, dynamic optimization, just-in-time compilation, adaptive code generation, pro�le-directed feedback, instruction-level parallelism, very long instruction word architectures, virtual machines, instruction set architectures, instruction set layering. +

+

Xen and the Art of Virtualization

+

Numerous systems have been designed which use virtualization to subdivide the ample resources of a modern computer. Some require specialized hardware, or cannot support commodity operating systems. Some target 100% binary compatibility at the expense of performance. Others sacrifice security or functionality for speed. Few offer resource isolation or performance guarantees; most provide only best-effort provisioning, risking denial of service. This paper presents Xen, an x86 virtual machine monitor which allows multiple commodity operating systemsto share conventional hardware in a safe and resource managed fashion, but without sacrificing either performance or functionality. This is achieved by providing an idealized virtual machine abstraction to which operating systems such as Linux, BSD and Windows XP, can be ported with minimal effort. Our design is targeted at hosting up to 100 virtual machine instances simultaneously on a modern server. The virtualization approach taken by Xen is extremely efficient: we allow operating systems such as Linux and Windows XP to be hosted simultaneously for a negligible performance overhead — at most a few percent compared with the unvirtualized case. We considerably outperform competing commercial and freely available solutions in a range of microbenchmarks and system-wide tests. +

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