diff options
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/gsp_phys_booter.c | 12 | ||||
| -rw-r--r-- | kernel/gsp_phys_gpu.h | 1 | ||||
| -rw-r--r-- | kernel/gsp_sema_service.c | 15 |
3 files changed, 26 insertions, 2 deletions
diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c index 43e4e11..733937c 100644 --- a/kernel/gsp_phys_booter.c +++ b/kernel/gsp_phys_booter.c @@ -19810,6 +19810,18 @@ bool gsp_phys_rmcall_gr_sph_bind_value(void) } /* + * SESSION 155 CONT 25: the synth slot mask must be readable by the sema + * service so it authors exactly the stage images the booter binds. With + * sema_gl_sph_bind=0 + sema_sph_bind_mask=0x35 the booter emits j0/j2/j5, + * but the service's PS/TCS authoring loop was gated on the all-slots bool, + * so the PS image could be left stale/zero at draw time (r1575). + */ +u32 gsp_phys_rmcall_gr_sph_bind_mask_value(void) +{ + return READ_ONCE(gsp_phys_rmcall_gr_sph_bind_mask); +} + +/* * SESSION 154c (viewport wall): the replayed 3D window carries no * viewport family state - the colour target, raster enable, shader * binds, attributes, index buffer and draws are present, but the diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h index 7de4fd5..d84b080 100644 --- a/kernel/gsp_phys_gpu.h +++ b/kernel/gsp_phys_gpu.h @@ -347,6 +347,7 @@ int gsp_phys_rmcall_gr_shadow_win0_value(void); * author the matching program images at those family VAs. */ bool gsp_phys_rmcall_gr_sph_bind_value(void); +u32 gsp_phys_rmcall_gr_sph_bind_mask_value(void); /* * SESSION 155 CONT 11: bind a synthesized header-only GEOMETRY SPH to diff --git a/kernel/gsp_sema_service.c b/kernel/gsp_sema_service.c index 6972172..e42e23d 100644 --- a/kernel/gsp_sema_service.c +++ b/kernel/gsp_sema_service.c @@ -10587,14 +10587,25 @@ static void svc_gl_flush(struct nv_vgpu_device *vgpu, ~(u64)(SEMA_PAGE_SIZE - 1); u32 k; - for (k = 0; gsp_phys_rmcall_gr_sph_bind_value() && - k < 2u && n_recs < SVC_GL_PROG_MAX; k++) { + /* + * CONT 25: author exactly the slots the booter emits. + * The booter emits j5 (PS) on mask 0x20 and j2 (TCS) + * on 0x04 when the all-slots bool is off; gate each + * image on the same condition instead of the bool + * alone (the r1575 zero-PS re-capture). + */ + for (k = 0; k < 2u && n_recs < SVC_GL_PROG_MAX; k++) { + u32 slot_bit = k ? 0x04u : 0x20u; u64 dst = fam + (k ? 0x200u : 0x0u); const u8 *b = k ? svc_gl_vs : svc_gl_ps; u32 bl = k ? svc_gl_vs_len : svc_gl_ps_len; bool dup = false; u32 pi3; + if (!(gsp_phys_rmcall_gr_sph_bind_value() || + (gsp_phys_rmcall_gr_sph_bind_mask_value() & + slot_bit))) + continue; if (!b || bl < 4u) continue; for (pi3 = 0; pi3 < svc_gl.n_progs; pi3++) |