diff options
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index 2f8a127..a394425 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -796,6 +796,27 @@ unsigned int gsp_phys_rmcall_gr_lmem_tpc_size_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lmem_tpc_size_value); /* + * m76 lane tail (gsp_phys_rmcall_gr_lane_tail; default 0). When set, the + * mode-35 lane enable also sends the R2 capture's tail after #1063: TSG + * PREEMPT (bWait=1, #1073), device-sched disable (#1075) and the + * PERF_BOOST_SET_2X control (#1077). The real client preempts its own TSG at + * context creation so the first dispatch performs a clean context load; our + * lane's context otherwise sits loaded from the ladder and task activation + * ends in a save/unload instead of execution. + */ +static int gsp_phys_rmcall_gr_lane_tail_param; +module_param_named(gsp_phys_rmcall_gr_lane_tail, + gsp_phys_rmcall_gr_lane_tail_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_lane_tail, + "Send the R2 #1073/#1075/#1077 lane tail after the mode-35 lane enable (default 0)"); + +int gsp_phys_rmcall_gr_lane_tail_value(void) +{ + return gsp_phys_rmcall_gr_lane_tail_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_lane_tail_value); + +/* * m74 R1/F2 ordering (gsp_phys_rmcall_gr_r1_first; default 0). 1 = send the * VA-only booking promote (R1) before F2's mapped-MAIN promote so the * one-shot context-image initializer (0x52a94f8, pEngCtx+0x135) sees the |