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-rw-r--r--kernel/gsp_phys_fwsec.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/gsp_phys_fwsec.h b/kernel/gsp_phys_fwsec.h
index 8e9d71d..cb8a499 100644
--- a/kernel/gsp_phys_fwsec.h
+++ b/kernel/gsp_phys_fwsec.h
@@ -20,11 +20,23 @@
*/
bool gsp_phys_fwsec_enabled(void);
+bool gsp_phys_fwsec_dryrun_enabled(void);
int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
void __iomem *bar0);
/*
+ * Read-only subset of stage 3c: VBIOS/PROM read, IFR/expansion-ROM/BIT
+ * parse, FWSEC ucode extraction, capacity-register reads and the complete
+ * staging/placement computation, logged under the
+ * "gsp-phys-fwsec-dryrun:" prefix. No BAR0 writes, no falcon resets, no DMA
+ * kicks; readl() of state registers is the only device interaction. Mutually
+ * exclusive with gsp_phys_fwsec=1 (both set is a hard refusal).
+ */
+int gsp_phys_fwsec_dryrun_run(struct gsp_phys_boot *boot, struct pci_dev *pdev,
+ void __iomem *bar0);
+
+/*
* Prepare the device for hand-back. If a FWSEC run programmed WPR2, run the
* teardown (FWSEC-SB + booter unload) while the module still owns BAR0.
* Returns nonzero when WPR2 could not be torn down: the caller must then