diff options
| -rw-r--r-- | kernel/Makefile | 2 | ||||
| -rw-r--r-- | kernel/gsp_phys_booter_unload_img.h | 3283 | ||||
| -rw-r--r-- | kernel/gsp_phys_fwsec.c | 1038 | ||||
| -rw-r--r-- | kernel/gsp_phys_fwsec.h | 36 | ||||
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 62 | ||||
| -rw-r--r-- | kernel/gsp_phys_sec2_bl.h | 83 | ||||
| -rw-r--r-- | kernel/gsp_phys_vbios.c | 771 | ||||
| -rw-r--r-- | kernel/gsp_phys_vbios.h | 71 |
8 files changed, 5340 insertions, 6 deletions
diff --git a/kernel/Makefile b/kernel/Makefile index b20dd87..d2950e9 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -18,6 +18,8 @@ open-iov-vfio-y := \ dynamic_rpc_dispatcher.o \ gsp_phys_gpu.o \ gsp_phys_boot.o \ + gsp_phys_vbios.o \ + gsp_phys_fwsec.o \ architecture/architecture.o \ version/version.o diff --git a/kernel/gsp_phys_booter_unload_img.h b/kernel/gsp_phys_booter_unload_img.h new file mode 100644 index 0000000..34c9a3d --- /dev/null +++ b/kernel/gsp_phys_booter_unload_img.h @@ -0,0 +1,3283 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Booter unload image (production, Turing) used to tear WPR2 down after + * a failed or completed FWSEC run. The 16-byte production signature is + * already patched at its bindata patch location (offset 0x4e00). + * + * Generated from the open kernel-modules bindata archives; do not edit + * by hand. The image is the production variant for Turing (TU10x). + */ + +#ifndef GSP_PHYS_BOOTER_UNLOAD_IMG_H +#define GSP_PHYS_BOOTER_UNLOAD_IMG_H + +#include <linux/types.h> + +static const u8 gsp_phys_booter_unload_image[39168] = { + 0x49, 0x00, 0x10, 0xce, 0x99, 0x00, 0x8f, 0x50, 0x16, 0x00, 0xbd, 0xe4, + 0xa0, 0xf9, 0xb5, 0xfe, 0x01, 0x49, 0x00, 0x11, 0xce, 0x99, 0x00, 0x8f, + 0x58, 0x16, 0x00, 0xa0, 0xf9, 0xb5, 0xfe, 0x01, 0x89, 0x00, 0x00, 0x01, + 0xfe, 0x94, 0x00, 0x7e, 0x2f, 0x00, 0x00, 0xf8, 0x02, 0xf8, 0x00, 0xf9, + 0x02, 0x8d, 0x00, 0x02, 0x00, 0xbf, 0xde, 0xdf, 0xff, 0xff, 0xff, 0x0f, + 0x89, 0x00, 0x01, 0x00, 0xff, 0x9f, 0x04, 0xb3, 0xe4, 0x00, 0x33, 0x98, + 0xd9, 0x01, 0xb3, 0x94, 0x00, 0x2c, 0x98, 0xd9, 0x02, 0xb3, 0x94, 0x00, + 0x25, 0x98, 0xd9, 0x03, 0xb3, 0x94, 0x00, 0x1e, 0x89, 0x00, 0x00, 0x00, + 0x98, 0x9f, 0x03, 0xb5, 0xdf, 0x03, 0xbf, 0x9f, 0xa0, 0xdf, 0x98, 0x9f, + 0x01, 0x98, 0x99, 0x02, 0xb5, 0xdf, 0x01, 0xb5, 0xd9, 0x02, 0x7e, 0xd6, + 0x00, 0x00, 0x0f, 0x31, 0x49, 0x00, 0x10, 0xf7, 0x9f, 0x00, 0x0f, 0x01, + 0x89, 0x00, 0x67, 0x04, 0xf7, 0x9f, 0x00, 0x0f, 0x0d, 0xb8, 0x99, 0x00, + 0x01, 0x02, 0xf7, 0x9f, 0x00, 0xf4, 0x3c, 0x02, 0x8f, 0x00, 0x00, 0x06, + 0x89, 0x00, 0x02, 0x00, 0xfd, 0x9f, 0x05, 0xbd, 0xf4, 0xfa, 0xf9, 0x06, + 0xf8, 0x03, 0x89, 0x00, 0x00, 0x02, 0x95, 0x0f, 0x08, 0xde, 0xff, 0xff, + 0xff, 0x0f, 0xfd, 0xf9, 0x05, 0x89, 0x00, 0x4c, 0x00, 0xfd, 0x9e, 0x04, + 0xbb, 0x90, 0x02, 0xb6, 0x94, 0x10, 0xfd, 0xf9, 0x05, 0xfe, 0xfa, 0x00, + 0x7e, 0x00, 0x01, 0x00, 0xf8, 0x02, 0xbd, 0xa4, 0xfb, 0x01, 0x8f, 0x33, + 0x35, 0x09, 0x89, 0x40, 0x4c, 0x00, 0xa0, 0x9f, 0xf8, 0x00, 0x8f, 0x40, + 0x4c, 0x00, 0xbf, 0xff, 0xf4, 0x30, 0xfc, 0xfe, 0x49, 0x01, 0xa0, 0x9f, + 0x3e, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc6, 0x83, 0x36, 0xd8, 0x93, 0x98, 0x7d, 0x67, + 0x36, 0x14, 0xd9, 0x15, 0x8d, 0x31, 0xd8, 0x2d, 0x97, 0xf9, 0x32, 0xb3, + 0x40, 0xf1, 0x43, 0xda, 0xed, 0x48, 0xc3, 0xc4, 0x72, 0x80, 0xa5, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +#endif /* GSP_PHYS_BOOTER_UNLOAD_IMG_H */ diff --git a/kernel/gsp_phys_fwsec.c b/kernel/gsp_phys_fwsec.c new file mode 100644 index 0000000..93a4208 --- /dev/null +++ b/kernel/gsp_phys_fwsec.c @@ -0,0 +1,1038 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Real-GSP boot stage 3c: FWSEC secure-verification run plus failure recovery. + * + * FWSEC is the VBIOS-provided security ucode that verifies the GSP image and + * carves the WPR2/FRTS region in video memory. It is not part of the GSP-RM + * firmware file; this module reads it from the GPU's own VBIOS (stage 3c's + * VBIOS/BIT parser) and runs it on the GSP falcon through the generic SEC2 + * boot-loader that ships as bindata. After a successful run WPR2 is up, so + * the distribution driver must not be rebound until the teardown (FWSEC-SB + + * booter unload) has put WPR2 back down; release refuses the hand-back + * otherwise. + * + * Disabled by default (gsp_phys_fwsec=N). The run happens only when the + * physical GPU is claimed (gsp_phys_gpu=1 + gsp_phys_hazard_ack=1) and the + * boot layout (gsp_phys_layout=1) succeeded. All device writes are BAR0 + * register/DMEM/IMEM programmings plus resets; the host never touches FB or + * BAR1. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/jiffies.h> +#include <asm/unaligned.h> + +#include "gsp_phys_fwsec.h" +#include "gsp_phys_vbios.h" +#include "gsp_phys_sec2_bl.h" +#include "gsp_phys_booter_unload_img.h" + +static bool gsp_phys_fwsec_param; +module_param_named(gsp_phys_fwsec, gsp_phys_fwsec_param, bool, 0644); +MODULE_PARM_DESC(gsp_phys_fwsec, + "Run the stage-3c FWSEC/FRTS verification on the claimed GPU after the boot layout succeeds (default 0; device writes)"); + +bool gsp_phys_fwsec_enabled(void) +{ + return gsp_phys_fwsec_param; +} + +/* Falcon engine bases (BAR0 absolute). */ +#define GSP_PHYS_GSP_BASE 0x00110000 +#define GSP_PHYS_GSP_FBIF_BASE 0x00110600 +#define GSP_PHYS_SEC2_BASE 0x00840000 +#define GSP_PHYS_SEC2_FBIF_BASE 0x00840600 + +/* Falcon register offsets, relative to the engine base. */ +#define GSP_PHYS_FALCON_MAILBOX0 0x40 +#define GSP_PHYS_FALCON_MAILBOX1 0x44 +#define GSP_PHYS_FALCON_RM 0x84 +#define GSP_PHYS_FALCON_HWCFG2 0xf4 +#define GSP_PHYS_FALCON_CPUCTL 0x100 +#define GSP_PHYS_FALCON_BOOTVEC 0x104 +#define GSP_PHYS_FALCON_HWCFG 0x108 +#define GSP_PHYS_FALCON_DMACTL 0x10c +#define GSP_PHYS_FALCON_CPUCTL_ALIAS 0x130 +#define GSP_PHYS_FALCON_IMEMC 0x180 +#define GSP_PHYS_FALCON_IMEMD 0x184 +#define GSP_PHYS_FALCON_IMEMT 0x188 +#define GSP_PHYS_FALCON_DMEMC 0x1c0 +#define GSP_PHYS_FALCON_DMEMD 0x1c4 +#define GSP_PHYS_FALCON_ENGINE 0x3c0 + +/* FBIF registers, relative to the falcon's FBIF base. */ +#define GSP_PHYS_FBIF_TRANSCFG(i) ((i) * 4) +#define GSP_PHYS_FBIF_CTL 0x24 + +/* Falcon CPUCTL / ENGINE / DMACTL field bits. */ +#define GSP_PHYS_CPUCTL_STARTCPU BIT(1) +#define GSP_PHYS_CPUCTL_HALTED BIT(4) +#define GSP_PHYS_CPUCTL_ALIAS_EN BIT(6) +#define GSP_PHYS_ENGINE_RESET BIT(0) +#define GSP_PHYS_DMACTL_DMEM_SCRUBBING BIT(1) +#define GSP_PHYS_DMACTL_IMEM_SCRUBBING BIT(2) +#define GSP_PHYS_HWCFG_IMEM_SIZE 0x1ff + +/* FBIF CTL / TRANSCFG fields. */ +#define GSP_PHYS_FBIF_CTL_ALLOW_PHYS_NO_CTX BIT(7) +#define GSP_PHYS_FBIF_TRANSCFG_TARGET_MASK 0x3 +#define GSP_PHYS_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x1 +#define GSP_PHYS_FBIF_TRANSCFG_MEM_TYPE BIT(2) + +/* IMEM/DMEM access port fields. */ +#define GSP_PHYS_FALCON_ADDR_MASK (0x0000fffc) +#define GSP_PHYS_FALCON_AINCW BIT(24) +#define GSP_PHYS_FALCON_IMEMC_SECURE BIT(28) + +/* GPU-side boot state registers. */ +#define GSP_PHYS_PMC_BOOT_0 0x00000000 +#define GSP_PHYS_VBIOS_SCRATCH_0E 0x001438 +#define GSP_PHYS_VBIOS_SCRATCH_15 0x001454 +#define GSP_PHYS_WPR2_ADDR_LO 0x1fa824 +#define GSP_PHYS_WPR2_ADDR_HI 0x1fa828 +/* WPR2 VAL field is bits 31:4 (DRF_VAL returns the unshifted field). */ +#define GSP_PHYS_WPR2_VAL_SHIFT 4 +#define GSP_PHYS_WPR2_VAL_MASK 0x0fffffffu +#define GSP_PHYS_GFW_BOOT 0x118234 +#define GSP_PHYS_GFW_BOOT_PROGRESS_MASK 0xff +#define GSP_PHYS_GFW_BOOT_COMPLETED 0xff +#define GSP_PHYS_GFW_PLM 0x118128 +#define GSP_PHYS_GFW_PLM_LEVEL0 BIT(0) +#define GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS 0x2174c +#define GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS_FIELD BIT(0) + +/* Timeouts (bounded; never an unbounded poll). */ +#define GSP_PHYS_GFW_BOOT_TIMEOUT_MS 2050 /* 50 ms + 2 s, as scaled by the driver */ +#define GSP_PHYS_FALCON_RESET_TIMEOUT_MS 1000 +#define GSP_PHYS_FWSEC_HALT_TIMEOUT_MS 5000 +#define GSP_PHYS_BOOTER_HALT_TIMEOUT_MS 5000 + +/* FWSEC interface command ids (DMEM mapper init_cmd). */ +#define GSP_PHYS_FWSEC_CMD_FRTS 0x15 +#define GSP_PHYS_FWSEC_CMD_SB 0x19 +/* FRTS region size in 4 KB units (1 MB). */ +#define GSP_PHYS_FRTS_REGION_SIZE_4K 0x100 +/* FRTS region media type: frame buffer. */ +#define GSP_PHYS_FRTS_REGION_MEDIA_FB 2 +/* readVbiosDesc flags used for the FWSEC FRTS/SB commands. */ +#define GSP_PHYS_FWSEC_READ_VBIOS_FLAGS 2 +/* DMEM mapper interface entry id. */ +#define GSP_PHYS_FWSEC_IFACE_ID_DMEMMAPPER 4 +/* Generic SEC2 boot-loader placement in IMEM (start tag). */ +#define GSP_PHYS_SEC2_BL_START_TAG 0xfd +/* + * Only the 0x200-byte code section of the 768-byte generic boot-loader image + * is loaded, as the distribution driver does (its data section and the DMEM + * descriptor are supplied separately). + */ +#define GSP_PHYS_SEC2_BL_CODE_SIZE 0x200 +/* Booter unload image layout (direct mode, from its bindata header). */ +#define GSP_PHYS_BOOTER_UNLOAD_NS_CODE_OFF 0x0000 +#define GSP_PHYS_BOOTER_UNLOAD_NS_CODE_SIZE 0x0100 +#define GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_OFF 0x0100 +#define GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_SIZE 0x4b00 +#define GSP_PHYS_BOOTER_UNLOAD_DATA_OFF 0x4c00 +#define GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE 0x4d00 +#define GSP_PHYS_BOOTER_UNLOAD_MBOX 0xff +#define GSP_PHYS_BOOTER_UNLOAD_IMAGE_SIZE 0x9900 + +/* Packed command structures consumed by the FWSEC ucode (little endian). */ +struct gsp_phys_fwsec_read_vbios_desc { + u32 version; + u32 size; + u64 gfw_image_offset; + u32 gfw_image_size; + u32 flags; +}; + +struct gsp_phys_fwsec_frts_region_desc { + u32 version; + u32 size; + u32 frts_region_offset4k; + u32 frts_region_size; + u32 frts_region_media_type; +}; + +struct gsp_phys_fwsec_frts_cmd { + struct gsp_phys_fwsec_read_vbios_desc read_vbios_desc; + struct gsp_phys_fwsec_frts_region_desc frts_region_desc; +}; + +/* + * DMEM descriptor handed to the generic boot-loader: reserved/signature + * (zero), the DMA context, the code/data DMA bases and the IMEM/DMEM + * offsets. 84 bytes exactly, 32-bit aligned fields only. + */ +struct gsp_phys_fwsec_bl_dmem_desc { + u32 reserved[4]; + u32 signature[4]; + u32 ctx_dma; + u32 code_dma_lo; + u32 code_dma_hi; + u32 non_secure_code_off; + u32 non_secure_code_size; + u32 secure_code_off; + u32 secure_code_size; + u32 code_entry_point; + u32 data_dma_lo; + u32 data_dma_hi; + u32 data_size; + u32 argc; + u32 argv; +}; + +/* FWSEC data-interface records (found inside the ucode DMEM image). */ +struct gsp_phys_fwsec_intf_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; +}; + +struct gsp_phys_fwsec_intf_entry { + u32 id; + u32 dmem_offset; +}; + +struct gsp_phys_fwsec_dmem_mapper { + u32 signature; + u16 version; + u16 size; + u32 cmd_in_buffer_offset; + u32 cmd_in_buffer_size; + u32 cmd_out_buffer_offset; + u32 cmd_out_buffer_size; + u32 nvf_img_data_buffer_offset; + u32 nvf_img_data_buffer_size; + u32 printf_buffer_hdr; + u32 ucode_build_time_stamp; + u32 ucode_signature; + u32 init_cmd; + u32 ucode_feature; + u32 ucode_cmd_mask0; + u32 ucode_cmd_mask1; + u32 multi_tgt_tbl; +}; + +struct gsp_phys_fwsec_ucode { + struct gsp_phys_fwsec_desc desc; + void *code_va; + dma_addr_t code_dma; + size_t code_size; + void *data_va; + dma_addr_t data_dma; + size_t data_size; +}; + +static struct gsp_phys_fwsec { + bool touched; /* FWSEC device state may be programmed */ + struct gsp_phys_fwsec_ucode ucode; +} fwsec; + +static u32 gsp_phys_fwsec_wpr2_hi_val(void __iomem *bar0) +{ + return (readl(bar0 + GSP_PHYS_WPR2_ADDR_HI) >> + GSP_PHYS_WPR2_VAL_SHIFT) & GSP_PHYS_WPR2_VAL_MASK; +} + +static u32 gsp_phys_fwsec_wpr2_lo_val(void __iomem *bar0) +{ + return (readl(bar0 + GSP_PHYS_WPR2_ADDR_LO) >> + GSP_PHYS_WPR2_VAL_SHIFT) & GSP_PHYS_WPR2_VAL_MASK; +} + +static bool gsp_phys_fwsec_wpr2_up(void __iomem *bar0) +{ + return gsp_phys_fwsec_wpr2_hi_val(bar0) != 0; +} + +static void gsp_phys_fwsec_dump_state(void __iomem *bar0, const char *what) +{ + pr_info("gsp-phys-fwsec: %s: GSP_CPUCTL=0x%08x SEC2_CPUCTL=0x%08x GSP_BOOTVEC=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x scratch0E=0x%08x scratch15=0x%08x GFW_BOOT=0x%08x SEC2_M0=0x%08x SEC2_M1=0x%08x\n", + what, + readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL), + readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_CPUCTL), + readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC), + readl(bar0 + GSP_PHYS_WPR2_ADDR_LO), + readl(bar0 + GSP_PHYS_WPR2_ADDR_HI), + readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_0E), + readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_15), + readl(bar0 + GSP_PHYS_GFW_BOOT), + readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX0), + readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1)); +} + +/* + * Falcon reset: pulse the engine reset bit with the reference's propagation + * read cycles, wait for the IMEM/DMEM scrubbers to report done (bounded), + * then load FALCON_RM with the raw PMC_BOOT_0 value. + */ +static int gsp_phys_falcon_reset(void __iomem *bar0, u32 base) +{ + unsigned long deadline; + u32 i, value; + int ret = 0; + + value = readl(bar0 + base + GSP_PHYS_FALCON_ENGINE); + writel(value | GSP_PHYS_ENGINE_RESET, + bar0 + base + GSP_PHYS_FALCON_ENGINE); + for (i = 0; i < 10; i++) + readl(bar0 + base + GSP_PHYS_FALCON_ENGINE); + + value = readl(bar0 + base + GSP_PHYS_FALCON_ENGINE); + writel(value & ~GSP_PHYS_ENGINE_RESET, + bar0 + base + GSP_PHYS_FALCON_ENGINE); + for (i = 0; i < 10; i++) + readl(bar0 + base + GSP_PHYS_FALCON_ENGINE); + + deadline = jiffies + msecs_to_jiffies(GSP_PHYS_FALCON_RESET_TIMEOUT_MS); + for (;;) { + value = readl(bar0 + base + GSP_PHYS_FALCON_DMACTL); + if (!(value & (GSP_PHYS_DMACTL_DMEM_SCRUBBING | + GSP_PHYS_DMACTL_IMEM_SCRUBBING))) + break; + if (time_after_eq(jiffies, deadline)) { + pr_err("gsp-phys-fwsec: falcon@0x%x reset scrub not done (DMACTL=0x%08x)\n", + base, value); + ret = -ETIMEDOUT; + break; + } + usleep_range(50, 100); + } + + if (ret) + return ret; + + writel(readl(bar0 + GSP_PHYS_PMC_BOOT_0), + bar0 + base + GSP_PHYS_FALCON_RM); + pr_info("gsp-phys-fwsec: falcon@0x%x reset: DMACTL=0x%08x FALCON_RM=0x%08x (PMC_BOOT_0) ENGINE=0x%08x\n", + base, readl(bar0 + base + GSP_PHYS_FALCON_DMACTL), + readl(bar0 + base + GSP_PHYS_FALCON_RM), + readl(bar0 + base + GSP_PHYS_FALCON_ENGINE)); + return ret; +} + +/* + * Allow physical DMA without a bound context: FBIF CTL bit7 and DMACTL=0, + * so the generic boot-loader can fetch its code/data descriptors. + */ +static void gsp_phys_falcon_disable_ctx_req(void __iomem *bar0, u32 base, + u32 fbif) +{ + u32 value; + + value = readl(bar0 + fbif + GSP_PHYS_FBIF_CTL); + writel(value | GSP_PHYS_FBIF_CTL_ALLOW_PHYS_NO_CTX, + bar0 + fbif + GSP_PHYS_FBIF_CTL); + writel(0, bar0 + base + GSP_PHYS_FALCON_DMACTL); + + pr_info("gsp-phys-fwsec: falcon@0x%x FBIF_CTL=0x%08x (ALLOW_PHYS_NO_CTX) DMACTL=0x%08x\n", + base, readl(bar0 + fbif + GSP_PHYS_FBIF_CTL), + readl(bar0 + base + GSP_PHYS_FALCON_DMACTL)); +} + +static void gsp_phys_falcon_dmem_copy(void __iomem *bar0, u32 base, u32 dest, + const u8 *src, u32 size) +{ + u32 words = size / 4; + u32 i; + + writel((dest & GSP_PHYS_FALCON_ADDR_MASK) | GSP_PHYS_FALCON_AINCW, + bar0 + base + GSP_PHYS_FALCON_DMEMC); + for (i = 0; i < words; i++) + writel(get_unaligned_le32(src + i * 4), + bar0 + base + GSP_PHYS_FALCON_DMEMD); +} + +/* + * IMEM block copy with per-256-byte tags starting at tag>>8, incrementing + * once per block. The tag names the virtual IMEM block the block belongs to. + */ +static void gsp_phys_falcon_imem_copy(void __iomem *bar0, u32 base, u32 dest, + const u8 *src, u32 size, bool secure, + u32 tag) +{ + u32 words = size / 4; + u32 i, value; + + value = (dest & GSP_PHYS_FALCON_ADDR_MASK) | GSP_PHYS_FALCON_AINCW; + if (secure) + value |= GSP_PHYS_FALCON_IMEMC_SECURE; + writel(value, bar0 + base + GSP_PHYS_FALCON_IMEMC); + + tag >>= 8; + for (i = 0; i < words; i++) { + if ((i & 63) == 0) { + writel(tag & 0xffff, + bar0 + base + GSP_PHYS_FALCON_IMEMT); + tag++; + } + writel(get_unaligned_le32(src + i * 4), + bar0 + base + GSP_PHYS_FALCON_IMEMD); + } +} + +static void gsp_phys_falcon_start_cpu(void __iomem *bar0, u32 base) +{ + u32 cpuctl = readl(bar0 + base + GSP_PHYS_FALCON_CPUCTL); + + if (cpuctl & GSP_PHYS_CPUCTL_ALIAS_EN) { + pr_info("gsp-phys-fwsec: falcon@0x%x ALIAS_EN set, starting via CPUCTL_ALIAS\n", + base); + writel(GSP_PHYS_CPUCTL_STARTCPU, + bar0 + base + GSP_PHYS_FALCON_CPUCTL_ALIAS); + } else { + writel(GSP_PHYS_CPUCTL_STARTCPU, + bar0 + base + GSP_PHYS_FALCON_CPUCTL); + } +} + +static int gsp_phys_falcon_wait_halt(void __iomem *bar0, u32 base, + u32 timeout_ms) +{ + unsigned long deadline = jiffies + msecs_to_jiffies(timeout_ms); + u32 cpuctl; + + for (;;) { + cpuctl = readl(bar0 + base + GSP_PHYS_FALCON_CPUCTL); + if (cpuctl & GSP_PHYS_CPUCTL_HALTED) + return 0; + if (time_after_eq(jiffies, deadline)) { + pr_err("gsp-phys-fwsec: falcon@0x%x did not halt (CPUCTL=0x%08x, timeout %ums)\n", + base, cpuctl, timeout_ms); + return -ETIMEDOUT; + } + usleep_range(500, 1000); + } +} + +/* Wait for GFW boot completion: falcon halted and progress 0xff. */ +static int gsp_phys_fwsec_wait_gfw_boot(void __iomem *bar0) +{ + unsigned long deadline = jiffies + + msecs_to_jiffies(GSP_PHYS_GFW_BOOT_TIMEOUT_MS); + u32 cpuctl = 0, progress = 0; + + for (;;) { + cpuctl = readl(bar0 + GSP_PHYS_GSP_BASE + + GSP_PHYS_FALCON_CPUCTL); + progress = readl(bar0 + GSP_PHYS_GFW_BOOT) & + GSP_PHYS_GFW_BOOT_PROGRESS_MASK; + if ((cpuctl & GSP_PHYS_CPUCTL_HALTED) && + progress == GSP_PHYS_GFW_BOOT_COMPLETED) { + pr_info("gsp-phys-fwsec: GFW boot complete: CPUCTL=0x%08x (halted) progress=0xff\n", + cpuctl); + return 0; + } + if (time_after_eq(jiffies, deadline)) + break; + msleep(1); + } + + pr_err("gsp-phys-fwsec: GFW boot not complete (CPUCTL=0x%08x progress=0x%x, timeout %ums); not resetting or kicking the falcon\n", + cpuctl, progress, GSP_PHYS_GFW_BOOT_TIMEOUT_MS); + return -ETIMEDOUT; +} + +static void gsp_phys_read_vbios_desc_init(struct gsp_phys_fwsec_read_vbios_desc *d) +{ + memset(d, 0, sizeof(*d)); + d->version = 1; + d->size = sizeof(*d); + d->flags = GSP_PHYS_FWSEC_READ_VBIOS_FLAGS; +} + +/* + * Patch the FWSEC interface in the staged DMEM copy for one command: walk + * the application-interface header to the DMEM mapper entry, program + * init_cmd and copy the command payload into the mapper's input buffer. + */ +static int gsp_phys_fwsec_patch_interface(struct gsp_phys_fwsec_ucode *u, + u32 cmd, const void *cmd_buf, + u32 cmd_size) +{ + struct gsp_phys_fwsec_intf_header *hdr; + struct gsp_phys_fwsec_dmem_mapper *mapper = NULL; + u8 *data = u->data_va; + u32 mapped_size = u->desc.dmem_load_size; + u32 interface_offset = u->desc.interface_offset; + u32 cur, i; + + if (interface_offset > mapped_size || + sizeof(*hdr) > mapped_size - interface_offset) { + pr_err("gsp-phys-fwsec: interface offset 0x%x outside DMEM image 0x%x\n", + interface_offset, mapped_size); + return -EINVAL; + } + + hdr = (struct gsp_phys_fwsec_intf_header *)(data + interface_offset); + if (hdr->entry_count < 2) { + pr_err("gsp-phys-fwsec: interface at 0x%x has only %u entries\n", + interface_offset, hdr->entry_count); + return -EINVAL; + } + + cur = interface_offset + sizeof(*hdr); + for (i = 0; i < hdr->entry_count; i++) { + struct gsp_phys_fwsec_intf_entry *entry; + + if (cur + sizeof(*entry) > mapped_size) + return -EINVAL; + entry = (struct gsp_phys_fwsec_intf_entry *)(data + cur); + cur += sizeof(*entry); + + if (entry->id == GSP_PHYS_FWSEC_IFACE_ID_DMEMMAPPER) { + if (entry->dmem_offset > mapped_size || + sizeof(*mapper) > mapped_size - entry->dmem_offset) + return -EINVAL; + mapper = (struct gsp_phys_fwsec_dmem_mapper *) + (data + entry->dmem_offset); + } + } + + if (!mapper) { + pr_err("gsp-phys-fwsec: no DMEM mapper entry for cmd 0x%x\n", + cmd); + return -EINVAL; + } + + mapper->init_cmd = cmd; + if (mapper->cmd_in_buffer_size < cmd_size) + pr_warn("gsp-phys-fwsec: interface input buffer 0x%x smaller than cmd 0x%x (0x%x bytes)\n", + mapper->cmd_in_buffer_size, cmd, cmd_size); + if (mapper->cmd_in_buffer_offset > mapped_size || + cmd_size > mapped_size - mapper->cmd_in_buffer_offset) { + pr_err("gsp-phys-fwsec: cmd buffer 0x%x+0x%x outside DMEM image 0x%x\n", + mapper->cmd_in_buffer_offset, cmd_size, mapped_size); + return -EINVAL; + } + + memcpy(data + mapper->cmd_in_buffer_offset, cmd_buf, cmd_size); + pr_info("gsp-phys-fwsec: interface patched: mapper@0x%x init_cmd=0x%x cmd@0x%x (0x%x bytes), out buffer 0x%x/0x%x\n", + (u32)((u8 *)mapper - data), cmd, + mapper->cmd_in_buffer_offset, cmd_size, + mapper->cmd_out_buffer_offset, mapper->cmd_out_buffer_size); + return 0; +} + +/* + * Prepare and run one FWSEC command on the GSP falcon through the generic + * SEC2 boot-loader: patch the interface, reset the falcon, then load the + * boot-loader at the top of IMEM with the FWSEC code/data descriptors. + */ +static int gsp_phys_fwsec_exec_with_loader(void __iomem *bar0, + struct gsp_phys_fwsec_ucode *u) +{ + struct gsp_phys_fwsec_bl_dmem_desc bl; + const struct gsp_phys_fwsec_desc *d = &u->desc; + s64 secure_off64; + u32 secure_off, secure_size, block_count, bl_dst; + u32 transcfg, cpuctl; + int ret; + + secure_off64 = (s64)d->imem_sec_base - d->imem_virt_base + + d->imem_phys_base; + if (secure_off64 < 0) { + pr_err("gsp-phys-fwsec: secure IMEM offset underflows (base=0x%x virt=0x%x phys=0x%x)\n", + d->imem_sec_base, d->imem_virt_base, + d->imem_phys_base); + return -EINVAL; + } + secure_off = (u32)secure_off64; + secure_size = ALIGN(d->imem_sec_size, 256); + + if (secure_off + secure_size > u->code_size || + d->imem_phys_base + d->imem_load_size > u->code_size) { + pr_err("gsp-phys-fwsec: code placement invalid (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%zx)\n", + d->imem_phys_base, d->imem_load_size, secure_off, + secure_size, u->code_size); + return -EINVAL; + } + + gsp_phys_falcon_disable_ctx_req(bar0, GSP_PHYS_GSP_BASE, + GSP_PHYS_GSP_FBIF_BASE); + + transcfg = readl(bar0 + GSP_PHYS_GSP_FBIF_BASE + + GSP_PHYS_FBIF_TRANSCFG(4)); + transcfg &= ~(GSP_PHYS_FBIF_TRANSCFG_TARGET_MASK | + GSP_PHYS_FBIF_TRANSCFG_MEM_TYPE); + transcfg |= GSP_PHYS_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM | + GSP_PHYS_FBIF_TRANSCFG_MEM_TYPE; + writel(transcfg, bar0 + GSP_PHYS_GSP_FBIF_BASE + + GSP_PHYS_FBIF_TRANSCFG(4)); + pr_info("gsp-phys-fwsec: TRANSCFG[4]@0x%x = 0x%08x (coherent sysmem, physical)\n", + GSP_PHYS_GSP_FBIF_BASE + GSP_PHYS_FBIF_TRANSCFG(4), + readl(bar0 + GSP_PHYS_GSP_FBIF_BASE + + GSP_PHYS_FBIF_TRANSCFG(4))); + + memset(&bl, 0, sizeof(bl)); + bl.ctx_dma = 4; /* physical system memory DMA context */ + bl.code_dma_lo = lower_32_bits(u->code_dma); + bl.code_dma_hi = upper_32_bits(u->code_dma); + bl.non_secure_code_off = d->imem_phys_base; + bl.non_secure_code_size = d->imem_load_size - d->imem_sec_size; + bl.secure_code_off = secure_off; + bl.secure_code_size = secure_size; + bl.code_entry_point = 0; + bl.data_dma_lo = lower_32_bits(u->data_dma); + bl.data_dma_hi = upper_32_bits(u->data_dma); + bl.data_size = d->dmem_load_size; + + gsp_phys_falcon_dmem_copy(bar0, GSP_PHYS_GSP_BASE, 0, (const u8 *)&bl, + sizeof(bl)); + pr_info("gsp-phys-fwsec: BL descriptor at DMEM0: ctxDma=%u codeDma=0x%llx nsOff/Size=0x%x/0x%x secOff/Size=0x%x/0x%x dataDma=0x%llx dataSize=0x%x\n", + bl.ctx_dma, (u64)u->code_dma, bl.non_secure_code_off, + bl.non_secure_code_size, bl.secure_code_off, + bl.secure_code_size, (u64)u->data_dma, bl.data_size); + + block_count = readl(bar0 + GSP_PHYS_GSP_BASE + + GSP_PHYS_FALCON_HWCFG) & GSP_PHYS_HWCFG_IMEM_SIZE; + if (block_count * 256 < GSP_PHYS_SEC2_BL_CODE_SIZE) { + pr_err("gsp-phys-fwsec: GSP IMEM too small for the boot-loader (%u blocks)\n", + block_count); + return -EINVAL; + } + bl_dst = (block_count - GSP_PHYS_SEC2_BL_CODE_SIZE / 256) << 8; + gsp_phys_falcon_imem_copy(bar0, GSP_PHYS_GSP_BASE, bl_dst, + gsp_phys_sec2_bl_image, + GSP_PHYS_SEC2_BL_CODE_SIZE, false, + GSP_PHYS_SEC2_BL_START_TAG << 8); + pr_info("gsp-phys-fwsec: generic SEC2 BL code 0x%x bytes at IMEM 0x%x (IMEM_SIZE=%u blocks, 256-byte blocks, tag 0x%x)\n", + GSP_PHYS_SEC2_BL_CODE_SIZE, bl_dst, block_count, + GSP_PHYS_SEC2_BL_START_TAG); + + writel(GSP_PHYS_SEC2_BL_START_TAG << 8, + bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC); + cpuctl = readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL); + pr_info("gsp-phys-fwsec: BOOTVEC=0x%08x CPUCTL before start=0x%08x\n", + readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_BOOTVEC), + cpuctl); + + gsp_phys_falcon_start_cpu(bar0, GSP_PHYS_GSP_BASE); + ret = gsp_phys_falcon_wait_halt(bar0, GSP_PHYS_GSP_BASE, + GSP_PHYS_FWSEC_HALT_TIMEOUT_MS); + pr_info("gsp-phys-fwsec: GSP CPUCTL after FWSEC kick=0x%08x\n", + readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_CPUCTL)); + return ret; +} + +static int gsp_phys_fwsec_exec_cmd(void __iomem *bar0, + struct gsp_phys_fwsec_ucode *u, u32 cmd, + const void *cmd_buf, u32 cmd_size) +{ + int ret; + + ret = gsp_phys_fwsec_patch_interface(u, cmd, cmd_buf, cmd_size); + if (ret) + return ret; + + ret = gsp_phys_falcon_reset(bar0, GSP_PHYS_GSP_BASE); + if (ret) + return ret; + + return gsp_phys_fwsec_exec_with_loader(bar0, u); +} + +static void gsp_phys_fwsec_ucode_free(struct pci_dev *pdev); + +/* + * Stage the FWSEC code/data images into device-visible coherent memory. The + * code image is copied at its IMEM physical base, the data at its DMEM + * physical base, both zero-padded to a 256-byte allocation granularity. + */ +static int gsp_phys_fwsec_ucode_stage(struct pci_dev *pdev, + const struct gsp_phys_vbios *vbios, + const struct gsp_phys_fwsec_desc *desc) +{ + struct gsp_phys_fwsec_ucode *u = &fwsec.ucode; + u32 image_start = desc->desc_offset + desc->desc_size; + u32 code_alloc, data_alloc, secure_off, secure_size; + s64 secure_off64; + + code_alloc = ALIGN(desc->imem_load_size, 256); + data_alloc = ALIGN(desc->dmem_load_size, 256); + secure_off64 = (s64)desc->imem_sec_base - desc->imem_virt_base + + desc->imem_phys_base; + if (secure_off64 < 0) + return -EINVAL; + secure_off = (u32)secure_off64; + secure_size = ALIGN(desc->imem_sec_size, 256); + + if (desc->imem_phys_base >= code_alloc || + desc->imem_load_size > code_alloc - desc->imem_phys_base || + secure_off >= code_alloc || + secure_size > code_alloc - secure_off) { + pr_err("gsp-phys-fwsec: FWSEC IMEM does not fit the code allocation (phys=0x%x load=0x%x secOff=0x%x secSize=0x%x alloc=0x%x)\n", + desc->imem_phys_base, desc->imem_load_size, secure_off, + secure_size, code_alloc); + return -EINVAL; + } + if (desc->dmem_phys_base >= data_alloc || + desc->dmem_load_size > data_alloc - desc->dmem_phys_base) { + pr_err("gsp-phys-fwsec: FWSEC DMEM does not fit the data allocation (phys=0x%x load=0x%x alloc=0x%x)\n", + desc->dmem_phys_base, desc->dmem_load_size, data_alloc); + return -EINVAL; + } + if (desc->dmem_phys_base != 0) + pr_warn("gsp-phys-fwsec: FWSEC DMEM physical base is 0x%x (not 0); interface patching uses the image-buffer offsets as the distribution driver does\n", + desc->dmem_phys_base); + + if (image_start + desc->imem_load_size > vbios->size || + image_start + desc->dmem_offset + desc->dmem_load_size > + vbios->size) { + pr_err("gsp-phys-fwsec: FWSEC images outside the VBIOS copy\n"); + return -EINVAL; + } + + u->desc = *desc; + u->code_size = code_alloc; + u->data_size = data_alloc; + u->code_va = dma_alloc_coherent(&pdev->dev, code_alloc, &u->code_dma, + GFP_KERNEL); + if (!u->code_va) { + pr_err("gsp-phys-fwsec: FWSEC code allocation (0x%x) failed\n", + code_alloc); + return -ENOMEM; + } + u->data_va = dma_alloc_coherent(&pdev->dev, data_alloc, &u->data_dma, + GFP_KERNEL); + if (!u->data_va) { + pr_err("gsp-phys-fwsec: FWSEC data allocation (0x%x) failed\n", + data_alloc); + gsp_phys_fwsec_ucode_free(pdev); + return -ENOMEM; + } + + memset(u->code_va, 0, code_alloc); + memcpy(u->code_va + desc->imem_phys_base, + vbios->data + image_start, desc->imem_load_size); + memset(u->data_va, 0, data_alloc); + memcpy(u->data_va + desc->dmem_phys_base, + vbios->data + image_start + desc->dmem_offset, + desc->dmem_load_size); + + pr_info("gsp-phys-fwsec: staged FWSEC: code alloc 0x%x dma=0x%llx (imemLoad=0x%x secOff/Size=0x%x/0x%x), data alloc 0x%x dma=0x%llx (dmemLoad=0x%x)\n", + code_alloc, (u64)u->code_dma, desc->imem_load_size, + secure_off, secure_size, data_alloc, (u64)u->data_dma, + desc->dmem_load_size); + return 0; +} + +static void gsp_phys_fwsec_ucode_free(struct pci_dev *pdev) +{ + struct gsp_phys_fwsec_ucode *u = &fwsec.ucode; + + if (u->code_va) + dma_free_coherent(&pdev->dev, u->code_size, u->code_va, + u->code_dma); + if (u->data_va) + dma_free_coherent(&pdev->dev, u->data_size, u->data_va, + u->data_dma); + memset(u, 0, sizeof(*u)); +} + +/* + * Booter unload on SEC2: reset, load the unload image in direct mode and run + * it with mailbox0/1 = 0xff. Success leaves WPR2 down. + */ +static int gsp_phys_booter_unload(void __iomem *bar0) +{ + const u8 *img = gsp_phys_booter_unload_image; + u32 m0, m1; + int ret; + + pr_info("gsp-phys-fwsec: booter unload: resetting SEC2 falcon\n"); + ret = gsp_phys_falcon_reset(bar0, GSP_PHYS_SEC2_BASE); + if (ret) + return ret; + + gsp_phys_falcon_disable_ctx_req(bar0, GSP_PHYS_SEC2_BASE, + GSP_PHYS_SEC2_FBIF_BASE); + gsp_phys_falcon_imem_copy(bar0, GSP_PHYS_SEC2_BASE, + GSP_PHYS_BOOTER_UNLOAD_NS_CODE_OFF, + img + GSP_PHYS_BOOTER_UNLOAD_NS_CODE_OFF, + GSP_PHYS_BOOTER_UNLOAD_NS_CODE_SIZE, false, + GSP_PHYS_BOOTER_UNLOAD_NS_CODE_OFF); + gsp_phys_falcon_imem_copy(bar0, GSP_PHYS_SEC2_BASE, + GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_OFF, + img + GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_OFF, + GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_SIZE, true, + GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_OFF); + gsp_phys_falcon_dmem_copy(bar0, GSP_PHYS_SEC2_BASE, 0, + img + GSP_PHYS_BOOTER_UNLOAD_DATA_OFF, + GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE); + writel(0, bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_BOOTVEC); + writel(GSP_PHYS_BOOTER_UNLOAD_MBOX, + bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX0); + writel(GSP_PHYS_BOOTER_UNLOAD_MBOX, + bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1); + + pr_info("gsp-phys-fwsec: booter unload: image 0x%zx bytes (ns 0x%x, sec 0x%x, data 0x%x), MAILBOX0/1=0xff, BOOTVEC=0\n", + sizeof(gsp_phys_booter_unload_image), + GSP_PHYS_BOOTER_UNLOAD_NS_CODE_SIZE, + GSP_PHYS_BOOTER_UNLOAD_SEC_CODE_SIZE, + GSP_PHYS_BOOTER_UNLOAD_DATA_SIZE); + + gsp_phys_falcon_start_cpu(bar0, GSP_PHYS_SEC2_BASE); + ret = gsp_phys_falcon_wait_halt(bar0, GSP_PHYS_SEC2_BASE, + GSP_PHYS_BOOTER_HALT_TIMEOUT_MS); + if (ret) + return ret; + + m0 = readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX0); + m1 = readl(bar0 + GSP_PHYS_SEC2_BASE + GSP_PHYS_FALCON_MAILBOX1); + pr_info("gsp-phys-fwsec: booter unload done: SEC2 M0=0x%08x M1=0x%08x WPR2_LO=0x%08x WPR2_HI=0x%08x\n", + m0, m1, readl(bar0 + GSP_PHYS_WPR2_ADDR_LO), + readl(bar0 + GSP_PHYS_WPR2_ADDR_HI)); + + if (m0 != 0) { + pr_err("gsp-phys-fwsec: booter unload reported error 0x%x\n", + m0); + return -EIO; + } + return 0; +} + +/* + * Teardown: FWSEC-SB (puts the pre-OS applications back) followed by the + * booter unload (removes WPR2). The final criterion is WPR2 down, not the + * individual ucode statuses. + */ +static int gsp_phys_fwsec_teardown(void __iomem *bar0) +{ + struct gsp_phys_fwsec_read_vbios_desc sb_cmd; + u32 scratch, sb_err, plm, progress; + int ret; + + if (!gsp_phys_fwsec_wpr2_up(bar0)) { + pr_info("gsp-phys-fwsec: teardown: WPR2 already down; resetting the GSP falcon only\n"); + gsp_phys_falcon_reset(bar0, GSP_PHYS_GSP_BASE); + return 0; + } + + if (fwsec.ucode.code_va) { + gsp_phys_read_vbios_desc_init(&sb_cmd); + pr_info("gsp-phys-fwsec: FWSEC-SB cmd 0x%x (readVbiosDesc version=%u size=%u flags=%u)\n", + GSP_PHYS_FWSEC_CMD_SB, sb_cmd.version, sb_cmd.size, + sb_cmd.flags); + ret = gsp_phys_fwsec_exec_cmd(bar0, &fwsec.ucode, + GSP_PHYS_FWSEC_CMD_SB, &sb_cmd, + sizeof(sb_cmd)); + if (ret) { + pr_err("gsp-phys-fwsec: FWSEC-SB execution failed: %d; continuing to booter unload\n", + ret); + } else { + plm = readl(bar0 + GSP_PHYS_GFW_PLM); + progress = readl(bar0 + GSP_PHYS_GFW_BOOT) & + GSP_PHYS_GFW_BOOT_PROGRESS_MASK; + scratch = readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_15); + sb_err = scratch & 0xffff; + pr_info("gsp-phys-fwsec: FWSEC-SB done: SB_ERR=0x%x PLM_LEVEL0=%u GFW_progress=0x%x\n", + sb_err, !!(plm & GSP_PHYS_GFW_PLM_LEVEL0), + progress); + if (sb_err != 0) + pr_warn("gsp-phys-fwsec: FWSEC-SB reported error 0x%x\n", + sb_err); + } + } else { + pr_warn("gsp-phys-fwsec: no staged FWSEC ucode for FWSEC-SB; running booter unload only\n"); + } + + ret = gsp_phys_booter_unload(bar0); + if (ret) + pr_err("gsp-phys-fwsec: booter unload failed: %d\n", ret); + + if (gsp_phys_fwsec_wpr2_up(bar0)) { + pr_err("gsp-phys-fwsec: teardown did not clear WPR2 (HI=0x%08x)\n", + readl(bar0 + GSP_PHYS_WPR2_ADDR_HI)); + return -EIO; + } + + pr_info("gsp-phys-fwsec: teardown complete: WPR2 down\n"); + return 0; +} + +int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev, + void __iomem *bar0) +{ + struct gsp_phys_vbios vbios = { }; + struct gsp_phys_fwsec_desc desc; + struct gsp_phys_fwsec_frts_cmd frts; + u32 wpr2_hi, wpr2_lo, scratch, frts_err, hwcfg2, fuse; + bool use_debug_app; + int ret, recover_ret; + + if (!boot || !pdev || !bar0) + return -EINVAL; + if (!boot->initialized) { + pr_err("gsp-phys-fwsec: boot layout not initialised; refusing stage 3c\n"); + return -EINVAL; + } + + pr_info("gsp-phys-fwsec: stage 3c FWSEC/FRTS on %s: frtsOffset=0x%llx frtsSize=0x%llx\n", + pci_name(pdev), boot->frts_offset, boot->frts_size); + + /* Precondition 1: WPR2 must be down. */ + wpr2_hi = gsp_phys_fwsec_wpr2_hi_val(bar0); + wpr2_lo = gsp_phys_fwsec_wpr2_lo_val(bar0); + pr_info("gsp-phys-fwsec: precondition WPR2: LO=0x%08x (VAL=0x%x) HI=0x%08x (VAL=0x%x), must be down\n", + readl(bar0 + GSP_PHYS_WPR2_ADDR_LO), wpr2_lo, + readl(bar0 + GSP_PHYS_WPR2_ADDR_HI), wpr2_hi); + if (wpr2_hi != 0) { + pr_err("gsp-phys-fwsec: unexpected WPR2 already up; the GPU is in a bad state, refusing FWSEC\n"); + return -EBUSY; + } + + /* Precondition 2: GFW boot complete and GSP falcon halted. */ + ret = gsp_phys_fwsec_wait_gfw_boot(bar0); + if (ret) + return ret; + + /* Precondition 3: the RISC-V core exists (HWCFG2.RISCV). */ + hwcfg2 = readl(bar0 + GSP_PHYS_GSP_BASE + GSP_PHYS_FALCON_HWCFG2); + if (!(hwcfg2 & BIT(10))) { + pr_err("gsp-phys-fwsec: RISC-V core not enabled (HWCFG2=0x%08x); refusing FWSEC\n", + hwcfg2); + return -ENODEV; + } + pr_info("gsp-phys-fwsec: precondition RISC-V enabled (HWCFG2=0x%08x)\n", + hwcfg2); + + /* Read and parse the VBIOS for the FWSEC image. */ + ret = gsp_phys_vbios_read(&vbios, pdev, bar0); + if (ret) + return ret; + + fuse = readl(bar0 + GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS); + use_debug_app = !(fuse & GSP_PHYS_FUSE_SECURE_GSP_DEBUG_DIS_FIELD); + pr_info("gsp-phys-fwsec: fuse SECURE_GSP_DEBUG_DIS=0x%08x -> %s FWSEC image (appId 0x%x)\n", + fuse, use_debug_app ? "debug" : "production", + use_debug_app ? GSP_PHYS_FWSEC_APPID_DEBUG : + GSP_PHYS_FWSEC_APPID_PROD); + + ret = gsp_phys_vbios_parse_fwsec(&vbios, use_debug_app, &desc); + if (ret) { + pr_err("gsp-phys-fwsec: FWSEC parse from VBIOS failed: %d\n", ret); + gsp_phys_vbios_free(&vbios); + return ret; + } + + ret = gsp_phys_fwsec_ucode_stage(pdev, &vbios, &desc); + gsp_phys_vbios_free(&vbios); + if (ret) + return ret; + + /* From here on the device may carry FWSEC state. */ + fwsec.touched = true; + + gsp_phys_read_vbios_desc_init(&frts.read_vbios_desc); + frts.frts_region_desc.version = 1; + frts.frts_region_desc.size = sizeof(frts.frts_region_desc); + frts.frts_region_desc.frts_region_offset4k = + (u32)(boot->frts_offset >> 12); + frts.frts_region_desc.frts_region_size = GSP_PHYS_FRTS_REGION_SIZE_4K; + frts.frts_region_desc.frts_region_media_type = + GSP_PHYS_FRTS_REGION_MEDIA_FB; + pr_info("gsp-phys-fwsec: FRTS cmd: readVbiosDesc{version=%u size=%u flags=%u}, region{offset4K=0x%x size=0x%x(4K) media=FB}\n", + frts.read_vbios_desc.version, frts.read_vbios_desc.size, + frts.read_vbios_desc.flags, + frts.frts_region_desc.frts_region_offset4k, + frts.frts_region_desc.frts_region_size); + + ret = gsp_phys_fwsec_exec_cmd(bar0, &fwsec.ucode, + GSP_PHYS_FWSEC_CMD_FRTS, &frts, + sizeof(frts)); + if (ret) { + pr_err("gsp-phys-fwsec: FWSEC/FRTS execution failed: %d\n", ret); + goto recover; + } + + /* Success checks: FRTS error clear, WPR2 up, WPR2 at frtsOffset. */ + scratch = readl(bar0 + GSP_PHYS_VBIOS_SCRATCH_0E); + frts_err = scratch >> 16; + wpr2_hi = gsp_phys_fwsec_wpr2_hi_val(bar0); + wpr2_lo = gsp_phys_fwsec_wpr2_lo_val(bar0); + gsp_phys_fwsec_dump_state(bar0, "after FWSEC/FRTS"); + pr_info("gsp-phys-fwsec: checks: FRTS_ERR_CODE=0x%x (want 0), WPR2_HI VAL=0x%x (want nonzero), WPR2_LO VAL=0x%x (want 0x%x)\n", + frts_err, wpr2_hi, wpr2_lo, (u32)(boot->frts_offset >> 12)); + + if (frts_err != 0 || wpr2_hi == 0 || + wpr2_lo != (u32)(boot->frts_offset >> 12)) { + pr_err("gsp-phys-fwsec: stage 3c FWSEC/FRTS checks FAILED\n"); + ret = -EIO; + goto recover; + } + + pr_info("gsp-phys-fwsec: stage 3c complete: WPR2 up at frtsOffset=0x%llx; device stays WPR2-owned until release tears it down\n", + boot->frts_offset); + return 0; + +recover: + pr_err("gsp-phys-fwsec: running WPR2 teardown (FWSEC-SB + booter unload)\n"); + recover_ret = gsp_phys_fwsec_teardown(bar0); + if (recover_ret) { + pr_err("gsp-phys-fwsec: teardown FAILED: WPR2 is still up; release will refuse the hand-back (reboot may be required; do not retry in this boot)\n"); + } else { + pr_info("gsp-phys-fwsec: teardown complete after failure: WPR2 down; the GPU can be handed back at release\n"); + } + gsp_phys_fwsec_dump_state(bar0, "after teardown"); + return ret; +} + +int gsp_phys_fwsec_release(struct gsp_phys_boot *boot, struct pci_dev *pdev, + void __iomem *bar0) +{ + int ret; + + if (!fwsec.touched) + return 0; + if (!pdev || !bar0) + return -EIO; + + if (!gsp_phys_fwsec_wpr2_up(bar0)) { + pr_info("gsp-phys-fwsec: release: WPR2 already down; freeing FWSEC staging and handing back\n"); + gsp_phys_fwsec_ucode_free(pdev); + fwsec.touched = false; + return 0; + } + + pr_info("gsp-phys-fwsec: release: WPR2 is up; tearing down before hand-back\n"); + ret = gsp_phys_fwsec_teardown(bar0); + gsp_phys_fwsec_ucode_free(pdev); + + if (ret || gsp_phys_fwsec_wpr2_up(bar0)) { + pr_err("gsp-phys-fwsec: release: WPR2 still up after teardown (HI=0x%08x); refusing the hand-back to the distribution driver\n", + readl(bar0 + GSP_PHYS_WPR2_ADDR_HI)); + return -EIO; + } + + pr_info("gsp-phys-fwsec: release: WPR2 down after teardown; hand-back is safe\n"); + fwsec.touched = false; + return 0; +} + +/* + * ABI shape checks for the FWSEC structures and the embedded bindata. These + * must match the generations the boot path was derived for; a mismatch means + * the structures or the extracted images changed, which must not be ignored. + */ +static void __maybe_unused gsp_phys_fwsec_abi_check(void) +{ + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_read_vbios_desc) != 24); + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_frts_region_desc) != 20); + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_frts_cmd) != 44); + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_bl_dmem_desc) != 84); + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_intf_header) != 4); + BUILD_BUG_ON(sizeof(struct gsp_phys_fwsec_intf_entry) != 8); + BUILD_BUG_ON(sizeof(gsp_phys_sec2_bl_image) != 0x300); + BUILD_BUG_ON(GSP_PHYS_SEC2_BL_CODE_SIZE != 0x200); + BUILD_BUG_ON(sizeof(gsp_phys_booter_unload_image) != + GSP_PHYS_BOOTER_UNLOAD_IMAGE_SIZE); +} diff --git a/kernel/gsp_phys_fwsec.h b/kernel/gsp_phys_fwsec.h new file mode 100644 index 0000000..8e9d71d --- /dev/null +++ b/kernel/gsp_phys_fwsec.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef GSP_PHYS_FWSEC_H +#define GSP_PHYS_FWSEC_H + +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/io.h> + +#include "gsp_phys_boot.h" + +/* + * Real-GSP boot stage 3c: the FWSEC secure-verification run that carves + * WPR2/FRTS on the claimed physical GPU, plus the teardown path that removes + * WPR2 again before the device is handed back to the distribution driver. + * + * The stage is disabled by default (gsp_phys_fwsec=N); claim must be enabled + * too (gsp_phys_gpu=1 + gsp_phys_hazard_ack=1) and the boot layout (stage 3b) + * must have succeeded. Every step logs its register reads; failures abort and + * the recovery path is attempted immediately. + */ + +bool gsp_phys_fwsec_enabled(void); + +int gsp_phys_fwsec_run(struct gsp_phys_boot *boot, struct pci_dev *pdev, + void __iomem *bar0); + +/* + * Prepare the device for hand-back. If a FWSEC run programmed WPR2, run the + * teardown (FWSEC-SB + booter unload) while the module still owns BAR0. + * Returns nonzero when WPR2 could not be torn down: the caller must then + * refuse to rebind the distribution driver and keep the power-domain locks. + */ +int gsp_phys_fwsec_release(struct gsp_phys_boot *boot, struct pci_dev *pdev, + void __iomem *bar0); + +#endif /* GSP_PHYS_FWSEC_H */ diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index a0f564f..a7c8e57 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -61,6 +61,7 @@ #include "gsp_phys_gpu.h" #include "gsp_phys_boot.h" +#include "gsp_phys_fwsec.h" #define GSP_PHYS_VENDOR 0x10de #define GSP_PHYS_DEVICE 0x1ed3 @@ -695,11 +696,24 @@ int gsp_phys_gpu_claim(void) } else { pr_info("gsp-phys: real GSP firmware staged (backend rung 2)\n"); - if (gsp_phys_layout_enabled() && - gsp_phys_boot_layout_init(&phys.boot, phys.pdev, phys.bar0, - phys.fw_image_size, phys.bar1_len)) - pr_warn("gsp-phys: boot layout/allocation failed; " - "backend stays at rung 2\n"); + if (gsp_phys_layout_enabled()) { + if (gsp_phys_boot_layout_init(&phys.boot, phys.pdev, + phys.bar0, + phys.fw_image_size, + phys.bar1_len)) { + pr_warn("gsp-phys: boot layout/allocation failed; " + "backend stays at rung 2\n"); + } else if (gsp_phys_fwsec_enabled()) { + if (gsp_phys_fwsec_run(&phys.boot, phys.pdev, + phys.bar0)) + pr_warn("gsp-phys: stage 3c FWSEC failed " + "(see recovery log above)\n"); + else + pr_info("gsp-phys: stage 3c FWSEC complete " + "(WPR2 up; release will tear it " + "down)\n"); + } + } } return 0; @@ -731,11 +745,30 @@ void gsp_phys_gpu_release(void) { struct pci_dev *pdev; struct device_driver *drv; - int ret; + int ret, wpr2_ret = 0; if (!phys.drv_registered && !phys.claimed && !phys.nr_locks) return; + /* + * WPR2 teardown must run while this module still owns BAR0. A + * successful stage 3c leaves WPR2 carved in FB; the distribution + * driver refuses to boot against an unexpected WPR2, so it has to be + * removed (FWSEC-SB + booter unload) before the hand-back. If the + * board stopped answering, skip the teardown (writes to a dead + * device are pointless) and let the fail-safe below refuse the + * hand-back. + */ + if (phys.pdev) { + if (gsp_phys_board_check(phys.pdev, "before WPR2 teardown")) { + wpr2_ret = -EIO; + } else { + wpr2_ret = gsp_phys_fwsec_release(&phys.boot, + phys.pdev, + phys.bar0); + } + } + if (phys.pdev) gsp_phys_boot_layout_fini(&phys.boot, phys.pdev); @@ -751,6 +784,23 @@ void gsp_phys_gpu_release(void) if (pdev) { /* + * Fail-safe: a WPR2 that survived the teardown makes the + * distribution driver's boot path fail (or worse), so never + * hand the device back in that state. Keep the D0 locks and + * the runtime-PM reference, as with the unresponsive-board + * abort. + */ + if (wpr2_ret) { + pr_err("gsp-phys: NOT rebinding %s: WPR2 teardown did not complete (WPR2 still up or board unresponsive); do not boot the distribution driver against it; power domain stays LOCKED (reboot with approval; do not retry in this boot)\n", + pci_name(pdev)); + if (phys.runtime_ref_held) + pr_debug("gsp-phys: keeping the runtime-PM reference on %s held (WPR2 still up)\n", + pci_name(pdev)); + pci_dev_put(pdev); + return; + } + + /* * Abort signal before handing the GPU back: if the board no * longer answers config reads, do not run the distribution * driver's power-up path. Keep the D0 locks so that a diff --git a/kernel/gsp_phys_sec2_bl.h b/kernel/gsp_phys_sec2_bl.h new file mode 100644 index 0000000..10b308e --- /dev/null +++ b/kernel/gsp_phys_sec2_bl.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generic SEC2 boot-loader image used to run the FWSEC image on the + * GSP falcon (code 0x200 at offset 0, data 0x100 at offset 0x200, + * start tag 0xfd, DMEM descriptor load offset 0). + * + * Generated from the open kernel-modules bindata archives; do not edit + * by hand. The image is the production variant for Turing (TU10x). + */ + +#ifndef GSP_PHYS_SEC2_BL_H +#define GSP_PHYS_SEC2_BL_H + +#include <linux/types.h> + +static const u8 gsp_phys_sec2_bl_image[768] = { + 0xd0, 0x00, 0x40, 0x00, 0x00, 0xfe, 0x04, 0x00, 0xbd, 0xa4, 0x7e, 0x10, + 0xfd, 0x00, 0xf8, 0x02, 0x89, 0x00, 0x00, 0x00, 0x98, 0x9e, 0x09, 0x98, + 0x9d, 0x0a, 0xf9, 0x12, 0x98, 0x9b, 0x12, 0xb6, 0xe5, 0x08, 0x94, 0xdf, + 0x18, 0x98, 0x9c, 0x0f, 0xfd, 0xfe, 0x05, 0x98, 0x9a, 0x13, 0x98, 0x91, + 0x14, 0x98, 0x90, 0x0e, 0xfe, 0xf6, 0x00, 0xb6, 0xd5, 0x08, 0xfe, 0xde, + 0x00, 0x89, 0x00, 0x00, 0x00, 0x98, 0x9f, 0x08, 0x94, 0xf9, 0x08, 0x94, + 0xfe, 0x0c, 0xfd, 0x9e, 0x05, 0xfd, 0x9f, 0x05, 0xfe, 0x9b, 0x00, 0x89, + 0x00, 0x00, 0x00, 0x98, 0x9f, 0x0c, 0x98, 0x99, 0x0b, 0xbd, 0xd4, 0xbc, + 0x9f, 0xf0, 0x3e, 0x73, 0xfd, 0x00, 0xfa, 0x9d, 0x04, 0xb8, 0x99, 0x00, + 0x01, 0x00, 0xb8, 0xdd, 0x00, 0x01, 0x00, 0xa6, 0x9f, 0xf4, 0x08, 0xf1, + 0xf8, 0x07, 0xb3, 0x00, 0x00, 0x60, 0xf4, 0x3c, 0x02, 0x8f, 0x00, 0x00, + 0x06, 0x89, 0x10, 0x00, 0x00, 0xfd, 0x9f, 0x05, 0xbd, 0xf4, 0xfa, 0xf9, + 0x06, 0xf8, 0x03, 0x89, 0x00, 0x00, 0x01, 0xfe, 0x9a, 0x00, 0x89, 0x00, + 0x00, 0x00, 0x98, 0x9e, 0x0d, 0xb2, 0xe9, 0xbc, 0xe0, 0xf0, 0x3e, 0xb7, + 0xfd, 0x00, 0xfa, 0x9d, 0x04, 0xb8, 0x99, 0x00, 0x01, 0x00, 0xb8, 0xdd, + 0x00, 0x01, 0x00, 0xa6, 0x9f, 0xf4, 0x08, 0xf1, 0xf8, 0x07, 0x89, 0x00, + 0x00, 0x00, 0x98, 0x9f, 0x0e, 0x98, 0x99, 0x09, 0xb6, 0xf4, 0x10, 0xb6, + 0x95, 0x08, 0xbc, 0x9e, 0x90, 0xb6, 0x95, 0x08, 0xfd, 0x9f, 0x05, 0xfe, + 0x9a, 0x00, 0x89, 0x00, 0x00, 0x00, 0x98, 0x9f, 0x08, 0x94, 0xf9, 0x08, + 0x94, 0xfe, 0x0c, 0xfd, 0x9e, 0x05, 0xfd, 0x9f, 0x05, 0xfe, 0x9b, 0x00, + 0x89, 0x00, 0x00, 0x00, 0x98, 0x9f, 0x10, 0x98, 0x9e, 0x11, 0xb6, 0xf5, + 0x08, 0x94, 0xe9, 0x18, 0xfd, 0x9f, 0x05, 0xfe, 0x97, 0x00, 0xb6, 0xe5, + 0x08, 0xfe, 0xef, 0x00, 0xbd, 0xf4, 0x3e, 0x21, 0xfe, 0x00, 0x8e, 0x00, + 0x00, 0x06, 0xbc, 0xfe, 0x90, 0xfa, 0xf9, 0x05, 0xb8, 0xff, 0x00, 0x01, + 0x00, 0xa6, 0xfb, 0xf4, 0x08, 0xef, 0xf8, 0x03, 0x09, 0x08, 0xcf, 0x99, + 0x00, 0xf0, 0x94, 0x08, 0xf4, 0x0b, 0x1b, 0x8f, 0x00, 0x00, 0x01, 0x49, + 0x90, 0x00, 0xfa, 0x9f, 0x00, 0x0f, 0x02, 0x09, 0x58, 0xfa, 0x9f, 0x00, + 0x0f, 0x08, 0x09, 0x04, 0xfa, 0x9f, 0x00, 0xb3, 0xa0, 0x00, 0x0c, 0xb2, + 0x1b, 0xf9, 0xc5, 0x3e, 0x59, 0xfe, 0x00, 0xf9, 0xc5, 0xb3, 0x00, 0x00, + 0x12, 0xf4, 0x31, 0x10, 0xf4, 0x31, 0x11, 0xf4, 0x31, 0x12, 0xbd, 0x94, + 0xfe, 0x9a, 0x00, 0xbd, 0xa4, 0xfb, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +#endif /* GSP_PHYS_SEC2_BL_H */ diff --git a/kernel/gsp_phys_vbios.c b/kernel/gsp_phys_vbios.c new file mode 100644 index 0000000..4c35636 --- /dev/null +++ b/kernel/gsp_phys_vbios.c @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Real-GSP boot stage 3c support: VBIOS access and FWSEC image parsing. + * + * Port of the distribution driver's Turing ROM extraction path, reduced to + * what the FWSEC/FRTS run needs: raw 32-bit reads through the PROM window, + * the legacy PCI ROM header / expansion-ROM walk, the BIT header scan and + * the falcon-ucode table lookup for the FWSEC application. No device writes. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/io.h> +#include <linux/string.h> +#include <linux/slab.h> +#include <asm/unaligned.h> + +#include "gsp_phys_vbios.h" + +/* Legacy PCI ROM / PCI data structure constants. */ +#define GSP_PHYS_ROM_SIG_STD 0xaa55 +#define GSP_PHYS_ROM_SIG_NV 0x4e56 +#define GSP_PHYS_ROM_SIG_NV2 0xbb77 +#define GSP_PHYS_PCIR_SIG 0x52494350 +#define GSP_PHYS_PCIR_SIG_NV 0x5344504e +#define GSP_PHYS_PCIR_SIG_NV2 0x53494752 +#define GSP_PHYS_PCIR_LAST_IMAGE BIT(7) +#define GSP_PHYS_ROM_BLOCK_SIZE 512 +#define GSP_PHYS_PCIR_STRUCT_LEN 0x0a +#define GSP_PHYS_PCIR_IMAGE_LEN 0x10 +#define GSP_PHYS_PCIR_CODE_TYPE 0x14 +#define GSP_PHYS_PCIR_LAST_IMAGE_OFF 0x15 +#define GSP_PHYS_PCIR_PTR 0x18 +#define GSP_PHYS_NPDE_SIG 0x4544504e +#define GSP_PHYS_NPDE_REV_10 0x0100 +#define GSP_PHYS_NPDE_REV_11 0x0101 +#define GSP_PHYS_NPDE_LEN 0x06 +#define GSP_PHYS_NPDE_REV 0x04 +#define GSP_PHYS_NPDE_SUBIMAGE_LEN 0x08 +#define GSP_PHYS_NPDE_LAST_IMAGE 0x0a +#define GSP_PHYS_NPDE_CODE_TYPE_VBIOS_BASE 0x00 +#define GSP_PHYS_NPDE_CODE_TYPE_VBIOS_EXT 0xe0 + +/* IFR (image format record) fixed fields at the start of the PROM image. */ +#define GSP_PHYS_IFR_FIXED1_VERSIONSW 0x0000ff00 +#define GSP_PHYS_IFR_FIXED1_VERSIONSW_SHIFT 8 +#define GSP_PHYS_IFR_FIXED1_FIXED_DATA_SIZE 0x7fff0000 +#define GSP_PHYS_IFR_FIXED1_FIXED_DATA_SIZE_SHIFT 16 +#define GSP_PHYS_IFR_FIXED2_TOTAL_DATA_SIZE 0x000fffff +#define GSP_PHYS_IFR_SIGNATURE 0x4947564e +#define GSP_PHYS_ROM_DIRECTORY_IDENTIFIER 0x44524652 +#define GSP_PHYS_ROM_DIRECTORY_SKIP 4096 + +/* BIOS Information Table (BIT) header and tokens. */ +#define GSP_PHYS_BIT_ID 0xb8ff +#define GSP_PHYS_BIT_SIGNATURE 0x00544942 +#define GSP_PHYS_BIT_HEADER_SIZE_OFF 8 +#define GSP_PHYS_BIT_TOKEN_SIZE_OFF 9 +#define GSP_PHYS_BIT_TOKEN_ENTRIES_OFF 10 +#define GSP_PHYS_BIT_TOKEN_BIOSDATA 0x42 +#define GSP_PHYS_BIT_TOKEN_FALCON_DATA 0x70 +#define GSP_PHYS_BIT_TOKEN_SIZE_6 6 +#define GSP_PHYS_BIT_TOKEN_SIZE_8 8 +#define GSP_PHYS_BIT_BIOSDATA_SIZE_MIN 5 +#define GSP_PHYS_BIT_FALCON_DATA_V2_SIZE_MIN 4 +#define GSP_PHYS_FALCON_UCODE_TABLE_VERSION 1 +#define GSP_PHYS_FALCON_UCODE_TABLE_HDR_SIZE 6 +#define GSP_PHYS_FALCON_UCODE_ENTRY_SIZE 6 +#define GSP_PHYS_FALCON_UCODE_DESC_V2_SIZE 60 +#define GSP_PHYS_FALCON_UCODE_DESC_V3_SIZE 44 + +/* + * Read one aligned 32-bit word from the PROM window. The window exposes only + * whole 32-bit registers; smaller/unaligned reads are assembled from them by + * gsp_phys_prom_read(), exactly like the distribution driver does. + */ +static bool gsp_phys_prom_read32(void __iomem *bar0, u32 offset, u32 *value) +{ + if (offset > GSP_PHYS_VBIOS_MAX_SIZE - sizeof(u32)) + return false; + *value = readl(bar0 + GSP_PHYS_VBIOS_PROM_WINDOW + offset); + return true; +} + +/* + * Read 1-4 bytes at an arbitrary PROM offset via 32-bit window reads. An + * unaligned access is assembled from one or two aligned words; the returned + * value is little endian (first byte at the lowest offset is the LSB). + */ +static bool gsp_phys_prom_read(void __iomem *bar0, u32 offset, u32 size, + u32 *value) +{ + union { + u32 word[2]; + u8 byte[8]; + } buf; + u32 byte_index; + bool second; + + if (size == 0 || size > sizeof(u32)) + return false; + if (offset > GSP_PHYS_VBIOS_MAX_SIZE - size) + return false; + + byte_index = offset & (sizeof(u32) - 1); + offset -= byte_index; + byte_index += size; + second = byte_index > sizeof(u32); + + if (!gsp_phys_prom_read32(bar0, offset, &buf.word[0])) + return false; + if (second && !gsp_phys_prom_read32(bar0, offset + sizeof(u32), + &buf.word[1])) + return false; + + *value = 0; + while (size--) + *value = (*value << 8) + buf.byte[--byte_index]; + return true; +} + +static bool gsp_phys_prom_read8(void __iomem *bar0, u32 offset, u32 *value) +{ + return gsp_phys_prom_read(bar0, offset, 1, value); +} + +static bool gsp_phys_prom_read16(void __iomem *bar0, u32 offset, u32 *value) +{ + return gsp_phys_prom_read(bar0, offset, 2, value); +} + +/* Read 1-4 bytes out of the already-copied image, little endian. */ +static bool gsp_phys_img_read(const struct gsp_phys_vbios *img, u32 offset, + u32 size, u32 *value) +{ + u32 v = 0, i; + + if (size == 0 || size > sizeof(u32)) + return false; + if (offset > img->size || size > img->size - offset) + return false; + + for (i = 0; i < size; i++) + v |= (u32)img->data[offset + i] << (8 * i); + *value = v; + return true; +} + +/* + * Locate the legacy PCI ROM image: either the image starts at PROM offset 0 + * (standard/nv signature) or the IFR record points at the image start. IFR + * versions 1/2 use the extended data-size field for the image offset; version + * 3 stores the flash-status offset at the total-data-size offset and the ROM + * directory 4096 bytes after that. + */ +static int gsp_phys_vbios_find_pci_header(void __iomem *bar0, u32 *pci_offset) +{ + u32 fixed0, fixed1, fixed2; + u32 image_offset = 0; + u32 data_size, flash_status, directory_sig, version; + + if (!gsp_phys_prom_read32(bar0, 0, &fixed0) || + !gsp_phys_prom_read32(bar0, 4, &fixed1) || + !gsp_phys_prom_read32(bar0, 8, &fixed2)) + return -EIO; + + if (fixed0 != GSP_PHYS_IFR_SIGNATURE) { + /* No IFR record: the image starts at offset 0. */ + *pci_offset = 0; + return 0; + } + + version = (fixed1 & GSP_PHYS_IFR_FIXED1_VERSIONSW) >> + GSP_PHYS_IFR_FIXED1_VERSIONSW_SHIFT; + + switch (version) { + case 1: + case 2: + data_size = (fixed1 & GSP_PHYS_IFR_FIXED1_FIXED_DATA_SIZE) >> + GSP_PHYS_IFR_FIXED1_FIXED_DATA_SIZE_SHIFT; + if (!gsp_phys_prom_read32(bar0, data_size + 4, &image_offset)) + return -EIO; + break; + case 3: + data_size = fixed2 & GSP_PHYS_IFR_FIXED2_TOTAL_DATA_SIZE; + if (!gsp_phys_prom_read32(bar0, data_size, &flash_status)) + return -EIO; + if (flash_status > + GSP_PHYS_VBIOS_MAX_SIZE - GSP_PHYS_ROM_DIRECTORY_SKIP - 8) + return -EINVAL; + if (!gsp_phys_prom_read32(bar0, + flash_status + + GSP_PHYS_ROM_DIRECTORY_SKIP, + &directory_sig)) + return -EIO; + if (directory_sig != GSP_PHYS_ROM_DIRECTORY_IDENTIFIER) { + pr_err("gsp-phys-vbios: ROM directory not found (0x%08x)\n", + directory_sig); + return -EINVAL; + } + if (!gsp_phys_prom_read32(bar0, + flash_status + + GSP_PHYS_ROM_DIRECTORY_SKIP + 8, + &image_offset)) + return -EIO; + break; + default: + pr_err("gsp-phys-vbios: unsupported IFR version %u\n", version); + return -EINVAL; + } + + if (image_offset > GSP_PHYS_VBIOS_MAX_SIZE - sizeof(u32)) { + pr_err("gsp-phys-vbios: IFR image offset 0x%x out of range\n", + image_offset); + return -EINVAL; + } + + *pci_offset = image_offset; + return 0; +} + +static bool gsp_phys_pci_data_sig_valid(u32 sig) +{ + return sig == GSP_PHYS_PCIR_SIG || sig == GSP_PHYS_PCIR_SIG_NV || + sig == GSP_PHYS_PCIR_SIG_NV2; +} + +/* + * Walk the PCI expansion ROM chain: every block starts with a ROM header + * whose 0x18 pointer gives the PCI data structure; the optional NVIDIA PCI + * data extension can override the sub-image length and the last-image flag. + * Returns the total image size relative to pci_offset and the expansion ROM + * base (the region that carries the BIT and the falcon ucode table). + */ +static int gsp_phys_vbios_locate_expansion_roms(void __iomem *bar0, + u32 pci_offset, + u32 *bios_size, + u32 *expansion_rom_offset) +{ + u32 curr_block = pci_offset; + u32 ext_rom_offset = 0, base_rom_size = 0; + u32 block_offset = 0, block_size = 0; + u32 iterations = GSP_PHYS_VBIOS_MAX_SIZE / GSP_PHYS_ROM_BLOCK_SIZE + 8; + u32 iter; + + for (iter = 0; iter < iterations; iter++) { + u32 pcir_ptr, base, sig, img_len, sub_img_len, code_type; + u32 struct_len, ext_at, ext_sig, ext_rev, ext_len; + bool last_image; + + if (!gsp_phys_prom_read16(bar0, curr_block + GSP_PHYS_PCIR_PTR, + &pcir_ptr)) + return -EIO; + if ((u64)curr_block + pcir_ptr > + GSP_PHYS_VBIOS_MAX_SIZE - 2) + return -EINVAL; + base = curr_block + pcir_ptr; + + if (!gsp_phys_prom_read32(bar0, base, &sig)) + return -EIO; + if (!gsp_phys_pci_data_sig_valid(sig)) { + pr_err("gsp-phys-vbios: invalid PCI data signature 0x%08x at 0x%x\n", + sig, base); + return -EINVAL; + } + + { + u32 v; + + if (!gsp_phys_prom_read8(bar0, + base + + GSP_PHYS_PCIR_LAST_IMAGE_OFF, + &v)) + return -EIO; + last_image = (v & GSP_PHYS_PCIR_LAST_IMAGE) != 0; + } + if (!gsp_phys_prom_read16(bar0, base + GSP_PHYS_PCIR_IMAGE_LEN, + &img_len)) + return -EIO; + sub_img_len = img_len; + + if (!gsp_phys_prom_read16(bar0, base + GSP_PHYS_PCIR_STRUCT_LEN, + &struct_len)) + return -EIO; + ext_at = (base + struct_len + 0xf) & ~0xfu; + + if (gsp_phys_prom_read32(bar0, ext_at, &ext_sig) && + ext_sig == GSP_PHYS_NPDE_SIG && + gsp_phys_prom_read16(bar0, ext_at + GSP_PHYS_NPDE_REV, + &ext_rev) && + (ext_rev == GSP_PHYS_NPDE_REV_10 || + ext_rev == GSP_PHYS_NPDE_REV_11)) { + if (!gsp_phys_prom_read16(bar0, + ext_at + GSP_PHYS_NPDE_LEN, + &ext_len)) + return -EIO; + if (!gsp_phys_prom_read16(bar0, + ext_at + + GSP_PHYS_NPDE_SUBIMAGE_LEN, + &sub_img_len)) + return -EIO; + if (GSP_PHYS_NPDE_LAST_IMAGE + 1 <= ext_len) { + u32 v; + + if (!gsp_phys_prom_read8(bar0, + ext_at + + GSP_PHYS_NPDE_LAST_IMAGE, + &v)) + return -EIO; + last_image = (v & GSP_PHYS_PCIR_LAST_IMAGE) != 0; + } else if (sub_img_len < img_len) { + last_image = false; + } + } + + if (!gsp_phys_prom_read8(bar0, base + GSP_PHYS_PCIR_CODE_TYPE, + &code_type)) + return -EIO; + + block_offset = curr_block - pci_offset; + block_size = sub_img_len * GSP_PHYS_ROM_BLOCK_SIZE; + + if (ext_rom_offset == 0 && + code_type == GSP_PHYS_NPDE_CODE_TYPE_VBIOS_EXT) + ext_rom_offset = block_offset; + else if (base_rom_size == 0 && + code_type == GSP_PHYS_NPDE_CODE_TYPE_VBIOS_BASE) + base_rom_size = block_size; + + if (last_image) + break; + + if (sub_img_len == 0) { + pr_err("gsp-phys-vbios: zero-sized ROM block at 0x%x\n", + curr_block); + return -EINVAL; + } + curr_block += sub_img_len * GSP_PHYS_ROM_BLOCK_SIZE; + if (curr_block > GSP_PHYS_VBIOS_MAX_SIZE) + return -EINVAL; + } + + if (iter == iterations) + return -EINVAL; + + if (bios_size) + *bios_size = block_offset + block_size; + if (expansion_rom_offset) { + if (ext_rom_offset > 0 && base_rom_size > 0) + *expansion_rom_offset = ext_rom_offset - base_rom_size; + else + *expansion_rom_offset = 0; + } + + return 0; +} + +static int gsp_phys_vbios_copy_image(struct gsp_phys_vbios *img, + void __iomem *bar0, u32 pci_offset, + u32 bios_size) +{ + u32 aligned, i; + u8 *buf; + + if (bios_size == 0 || bios_size > GSP_PHYS_VBIOS_MAX_SIZE) + return -EINVAL; + + buf = kvzalloc(bios_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + aligned = bios_size & ~0x3u; + for (i = 0; i < aligned; i += 4) { + u32 word; + + if (!gsp_phys_prom_read32(bar0, pci_offset + i, &word)) { + kvfree(buf); + return -EIO; + } + put_unaligned_le32(word, buf + i); + } + for (; i < bios_size; i++) { + u32 byte; + + if (!gsp_phys_prom_read8(bar0, pci_offset + i, &byte)) { + kvfree(buf); + return -EIO; + } + buf[i] = (u8)byte; + } + + img->data = buf; + img->size = bios_size; + img->pci_offset = pci_offset; + return 0; +} + +int gsp_phys_vbios_read(struct gsp_phys_vbios *img, struct pci_dev *pdev, + void __iomem *bar0) +{ + u32 pci_offset = 0, bios_size = 0, expansion_rom_offset = 0; + u32 rom_sig; + int ret; + + if (!img || !bar0) + return -EINVAL; + + memset(img, 0, sizeof(*img)); + + if (!gsp_phys_prom_read16(bar0, 0, &rom_sig)) + return -EIO; + + if (rom_sig != GSP_PHYS_ROM_SIG_STD && + rom_sig != GSP_PHYS_ROM_SIG_NV && + rom_sig != GSP_PHYS_ROM_SIG_NV2) { + ret = gsp_phys_vbios_find_pci_header(bar0, &pci_offset); + if (ret) + return ret; + + /* Re-read the ROM signature at the IFR image start. */ + if (!gsp_phys_prom_read16(bar0, pci_offset, &rom_sig)) + return -EIO; + } + + if (rom_sig != GSP_PHYS_ROM_SIG_STD && + rom_sig != GSP_PHYS_ROM_SIG_NV && + rom_sig != GSP_PHYS_ROM_SIG_NV2) { + pr_err("gsp-phys-vbios: no valid ROM signature at offset 0x%x (0x%04x)\n", + pci_offset, rom_sig); + return -EINVAL; + } + + ret = gsp_phys_vbios_locate_expansion_roms(bar0, pci_offset, + &bios_size, + &expansion_rom_offset); + if (ret) { + pr_err("gsp-phys-vbios: expansion ROM walk failed: %d\n", ret); + return ret; + } + if (bios_size > GSP_PHYS_VBIOS_MAX_SIZE) { + pr_err("gsp-phys-vbios: expansion ROM size 0x%x exceeds the window\n", + bios_size); + return -EINVAL; + } + + ret = gsp_phys_vbios_copy_image(img, bar0, pci_offset, bios_size); + if (ret) + return ret; + + img->expansion_rom_offset = expansion_rom_offset; + + pr_info("gsp-phys-vbios: ROM on %s: pciOffset=0x%x size=0x%x expansionRomOffset=0x%x\n", + pci_name(pdev), pci_offset, bios_size, expansion_rom_offset); + return 0; +} + +void gsp_phys_vbios_free(struct gsp_phys_vbios *img) +{ + if (!img) + return; + kvfree(img->data); + memset(img, 0, sizeof(*img)); +} + +/* Find the BIT header: id 0xB8FF + "BIT\0" signature, header checksum 0. */ +static int gsp_phys_vbios_find_bit(const struct gsp_phys_vbios *img, + u32 *bit_addr) +{ + u32 addr; + + for (addr = 0; addr + 4 <= img->size; addr++) { + u32 id, sig, header_size, checksum = 0, j; + + if (!gsp_phys_img_read(img, addr, 2, &id) || + id != GSP_PHYS_BIT_ID) + continue; + if (!gsp_phys_img_read(img, addr + 2, 4, &sig) || + sig != GSP_PHYS_BIT_SIGNATURE) + continue; + if (!gsp_phys_img_read(img, addr + GSP_PHYS_BIT_HEADER_SIZE_OFF, + 1, &header_size)) + continue; + if (header_size == 0 || header_size > img->size - addr) + continue; + for (j = 0; j < header_size; j++) { + u32 b; + + if (!gsp_phys_img_read(img, addr + j, 1, &b)) + break; + checksum += b; + } + if (j != header_size) + continue; + if ((checksum & 0xff) == 0) { + *bit_addr = addr; + return 0; + } + } + + return -ENOENT; +} + +static bool gsp_phys_fwsec_appid_wanted(u32 app_id, bool use_debug_app) +{ + if (app_id == GSP_PHYS_FWSEC_APPID_FIRMWARE_SEC_LIC) + return true; + if (use_debug_app) + return app_id == GSP_PHYS_FWSEC_APPID_DEBUG; + return app_id == GSP_PHYS_FWSEC_APPID_PROD; +} + +static int gsp_phys_vbios_parse_desc(const struct gsp_phys_vbios *img, + u32 desc_offset, u32 app_id, u32 target_id, + struct gsp_phys_fwsec_desc *desc) +{ + u32 vdesc, version, size, fields[14]; + u32 i, image_start, image_end; + + if (!gsp_phys_img_read(img, desc_offset, 4, &vdesc)) + return -EIO; + + /* The flags bit0 must announce a version; 0 means unavailable. */ + if ((vdesc & 0x1) == 0) + return 0; + + version = (vdesc >> 8) & 0xff; + size = (vdesc >> 16) & 0xffff; + + if (version == 3 && size >= GSP_PHYS_FALCON_UCODE_DESC_V3_SIZE) { + pr_err("gsp-phys-vbios: FWSEC appId=0x%x is a V3 (boot-from-HS) descriptor; this GPU generation boots FWSEC with the generic SEC2 boot-loader (V2) only - cannot proceed\n", + app_id); + return -EOPNOTSUPP; + } + if (version != 2 || size < GSP_PHYS_FALCON_UCODE_DESC_V2_SIZE) + return 1; /* not a usable descriptor; keep looking */ + + if (desc_offset > img->size || size > img->size - desc_offset) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(fields); i++) { + if (!gsp_phys_img_read(img, desc_offset + 4 + i * 4, 4, + &fields[i])) + return -EIO; + } + + /* V2 fields: Stored, Uncompressed, VirtualEntry, Interface, IMEMPhys, + * IMEMLoad, IMEMVirt, IMEMSecBase, IMEMSecSize, DMEMOffset, DMEMPhys, + * DMEMLoad, altIMEM, altDMEM. + */ + memset(desc, 0, sizeof(*desc)); + desc->app_id = app_id; + desc->target_id = target_id; + desc->desc_version = version; + desc->desc_size = size; + desc->desc_offset = desc_offset; + desc->virtual_entry = fields[2]; + desc->interface_offset = fields[3]; + desc->imem_phys_base = fields[4]; + desc->imem_load_size = fields[5]; + desc->imem_virt_base = fields[6]; + desc->imem_sec_base = fields[7]; + desc->imem_sec_size = fields[8]; + desc->dmem_offset = fields[9]; + desc->dmem_phys_base = fields[10]; + desc->dmem_load_size = fields[11]; + + if (desc->imem_load_size == 0 || desc->dmem_load_size == 0) { + pr_err("gsp-phys-vbios: FWSEC descriptor has a zero-sized IMEM/DMEM image (imem=0x%x dmem=0x%x)\n", + desc->imem_load_size, desc->dmem_load_size); + return -EINVAL; + } + if (desc->imem_sec_size > desc->imem_load_size) { + pr_err("gsp-phys-vbios: FWSEC secure IMEM size 0x%x exceeds load size 0x%x\n", + desc->imem_sec_size, desc->imem_load_size); + return -EINVAL; + } + + /* Code is stored immediately after the descriptor, data after code. */ + image_start = desc_offset + size; + if (image_start > img->size || + desc->imem_load_size > img->size - image_start) { + pr_err("gsp-phys-vbios: FWSEC IMEM image runs past the ROM copy\n"); + return -EINVAL; + } + if (desc->dmem_offset > img->size - image_start) { + pr_err("gsp-phys-vbios: FWSEC DMEM offset runs past the ROM copy\n"); + return -EINVAL; + } + image_end = image_start + desc->dmem_offset; + if (desc->dmem_load_size > img->size - image_end) { + pr_err("gsp-phys-vbios: FWSEC DMEM image runs past the ROM copy\n"); + return -EINVAL; + } + if (desc->interface_offset >= desc->dmem_load_size) { + pr_err("gsp-phys-vbios: FWSEC interface offset 0x%x outside DMEM image (0x%x)\n", + desc->interface_offset, desc->dmem_load_size); + return -EINVAL; + } + + pr_info("gsp-phys-vbios: FWSEC entry appId=0x%x targetId=%u desc=V%u size=%u at 0x%x\n", + app_id, target_id, version, size, desc_offset); + pr_info("gsp-phys-vbios: FWSEC image: code at 0x%x (0x%x bytes) data at 0x%x (0x%x bytes)\n", + image_start, desc->imem_load_size, + image_start + desc->dmem_offset, desc->dmem_load_size); + pr_info("gsp-phys-vbios: FWSEC IMEM base/load/virt/secBase/secSize=0x%x/0x%x/0x%x/0x%x/0x%x DMEM off/phys/load=0x%x/0x%x/0x%x interfaceOff=0x%x entry=0x%x\n", + desc->imem_phys_base, desc->imem_load_size, + desc->imem_virt_base, desc->imem_sec_base, + desc->imem_sec_size, desc->dmem_offset, + desc->dmem_phys_base, desc->dmem_load_size, + desc->interface_offset, desc->virtual_entry); + return 0; +} + +/* + * Parse the copied VBIOS for the FWSEC falcon-ucode descriptor: find the BIT + * header, walk its tokens to the falcon-ucode table, then walk the table + * entries for the requested FWSEC application. Also reports the combined + * VBIOS version from the BIOSDATA token when present. + */ +int gsp_phys_vbios_parse_fwsec(const struct gsp_phys_vbios *img, + bool use_debug_app, + struct gsp_phys_fwsec_desc *desc) +{ + u32 bit_addr, header_size, token_size, token_entries; + u64 version = 0; + int ret; + + if (!img || !img->data || !desc) + return -EINVAL; + + ret = gsp_phys_vbios_find_bit(img, &bit_addr); + if (ret) { + pr_err("gsp-phys-vbios: BIT header not found in %zu-byte ROM image\n", + img->size); + return ret; + } + + if (!gsp_phys_img_read(img, bit_addr + GSP_PHYS_BIT_HEADER_SIZE_OFF, 1, + &header_size) || + !gsp_phys_img_read(img, bit_addr + GSP_PHYS_BIT_TOKEN_SIZE_OFF, 1, + &token_size) || + !gsp_phys_img_read(img, bit_addr + GSP_PHYS_BIT_TOKEN_ENTRIES_OFF, + 1, &token_entries)) { + pr_err("gsp-phys-vbios: truncated BIT header at 0x%x\n", + bit_addr); + return -EINVAL; + } + pr_info("gsp-phys-vbios: BIT header at 0x%x headerSize=%u tokenSize=%u tokens=%u\n", + bit_addr, header_size, token_size, token_entries); + + if (token_size < GSP_PHYS_BIT_TOKEN_SIZE_6) { + pr_err("gsp-phys-vbios: invalid BIT token size %u\n", + token_size); + return -EINVAL; + } + + { + u32 i; + + for (i = 0; i < token_entries; i++) { + u32 token_offset = bit_addr + header_size + + i * token_size; + u32 token_id, data_version, data_size, data_ptr; + u32 table_ptr; + + if (!gsp_phys_img_read(img, token_offset, 1, + &token_id) || + !gsp_phys_img_read(img, token_offset + 1, 1, + &data_version) || + !gsp_phys_img_read(img, token_offset + 2, 2, + &data_size)) + continue; + + if (token_size >= GSP_PHYS_BIT_TOKEN_SIZE_8) { + if (!gsp_phys_img_read(img, token_offset + 4, 4, + &data_ptr)) + continue; + } else { + if (!gsp_phys_img_read(img, token_offset + 4, 2, + &data_ptr)) + continue; + } + + if (token_id == GSP_PHYS_BIT_TOKEN_BIOSDATA && + (data_version == 1 || data_version == 2) && + data_size > GSP_PHYS_BIT_BIOSDATA_SIZE_MIN) { + u32 binver, oem; + + if (gsp_phys_img_read(img, data_ptr, 4, + &binver) && + gsp_phys_img_read(img, data_ptr + 4, 1, + &oem)) + version = ((u64)binver << 8) | oem; + } + + if (token_id != GSP_PHYS_BIT_TOKEN_FALCON_DATA || + data_version != 2 || + data_size < GSP_PHYS_BIT_FALCON_DATA_V2_SIZE_MIN) + continue; + + if (!gsp_phys_img_read(img, data_ptr, 4, &table_ptr)) + continue; + + { + u32 table_offset = img->expansion_rom_offset + + table_ptr; + u32 table_version, table_hdr_size, entry_size; + u32 entry_count, j; + + if (!gsp_phys_img_read(img, table_offset, 1, + &table_version) || + !gsp_phys_img_read(img, table_offset + 1, 1, + &table_hdr_size) || + !gsp_phys_img_read(img, table_offset + 2, 1, + &entry_size) || + !gsp_phys_img_read(img, table_offset + 3, 1, + &entry_count)) + continue; + + if (table_version != + GSP_PHYS_FALCON_UCODE_TABLE_VERSION || + table_hdr_size < + GSP_PHYS_FALCON_UCODE_TABLE_HDR_SIZE || + entry_size < GSP_PHYS_FALCON_UCODE_ENTRY_SIZE) + continue; + + for (j = 0; j < entry_count; j++) { + u32 entry_offset = table_offset + + table_hdr_size + + j * entry_size; + u32 app_id, target_id, desc_ptr; + + if (!gsp_phys_img_read(img, entry_offset, + 1, &app_id) || + !gsp_phys_img_read(img, + entry_offset + 1, 1, + &target_id) || + !gsp_phys_img_read(img, + entry_offset + 2, 4, + &desc_ptr)) + continue; + + if (!gsp_phys_fwsec_appid_wanted( + app_id, use_debug_app)) + continue; + + pr_info("gsp-phys-vbios: BIT falcon entry %u: appId=0x%x targetId=%u descPtr=0x%x\n", + j, app_id, target_id, desc_ptr); + + ret = gsp_phys_vbios_parse_desc( + img, + img->expansion_rom_offset + + desc_ptr, + app_id, target_id, desc); + if (ret < 0) + return ret; + if (ret == 0) { + pr_info("gsp-phys-vbios: VBIOS version (binver<<8|oem) = 0x%llx\n", + version); + return 0; + } + } + } + } + } + + pr_err("gsp-phys-vbios: no usable FWSEC V2 descriptor in the BIT (debug app %s)\n", + use_debug_app ? "wanted" : "not wanted"); + return -ENOENT; +} diff --git a/kernel/gsp_phys_vbios.h b/kernel/gsp_phys_vbios.h new file mode 100644 index 0000000..5fc6e85 --- /dev/null +++ b/kernel/gsp_phys_vbios.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef GSP_PHYS_VBIOS_H +#define GSP_PHYS_VBIOS_H + +#include <linux/types.h> +#include <linux/pci.h> + +/* + * Real-GSP boot stage 3c support: video-BIOS access and parsing. + * + * The FWSEC image that verifies and carves WPR2 is not part of the GSP-RM + * firmware file - it ships in the GPU's own VBIOS. This module reads the + * VBIOS through the PROM window while the physical GPU is claimed, walks the + * legacy PCI ROM header / ROM directory, then finds the BIOS Information + * Table (BIT) and the FWSEC falcon-ucode entry in the expansion ROM. + * + * All accesses are read-only. Disabled unless stage 3c is enabled + * (gsp_phys_fwsec=1); claim must be enabled too. + */ + +/* Upper bound used by the distribution driver's ROM extraction (1 MB). */ +#define GSP_PHYS_VBIOS_MAX_SIZE 0x00100000 + +/* PROM data window in BAR0: NV_PROM_DATA(i), 32-bit reads only. */ +#define GSP_PHYS_VBIOS_PROM_WINDOW 0x00300000 + +/* FWSEC ucode application ids in the BIT falcon-ucode table. */ +#define GSP_PHYS_FWSEC_APPID_FIRMWARE_SEC_LIC 0x05 +#define GSP_PHYS_FWSEC_APPID_DEBUG 0x45 +#define GSP_PHYS_FWSEC_APPID_PROD 0x85 + +struct gsp_phys_vbios { + u8 *data; /* copied VBIOS image (host memory) */ + size_t size; /* usable image size in bytes */ + u32 pci_offset; /* image start offset of the base ROM */ + u32 expansion_rom_offset; /* expansion ROM base, from image start */ + u64 version; /* (binary version << 8) | OEM, 0 if absent */ +}; + +/* + * FWSEC falcon-ucode descriptor as found in the BIT. Only the V2 variant is + * accepted: on this GPU generation the security falcon cannot boot the V3 + * (boot-from-HS) form, so a V3 descriptor is a hard stop. + */ +struct gsp_phys_fwsec_desc { + u32 app_id; + u32 target_id; + u32 desc_version; + u32 desc_size; + u32 desc_offset; /* offset of the descriptor in the image */ + u32 imem_phys_base; + u32 imem_load_size; + u32 imem_virt_base; + u32 imem_sec_base; + u32 imem_sec_size; + u32 dmem_offset; + u32 dmem_phys_base; + u32 dmem_load_size; + u32 interface_offset; + u32 virtual_entry; +}; + +int gsp_phys_vbios_read(struct gsp_phys_vbios *img, struct pci_dev *pdev, + void __iomem *bar0); +void gsp_phys_vbios_free(struct gsp_phys_vbios *img); + +int gsp_phys_vbios_parse_fwsec(const struct gsp_phys_vbios *img, + bool use_debug_app, + struct gsp_phys_fwsec_desc *desc); + +#endif /* GSP_PHYS_VBIOS_H */ |