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| author | Open-IOV <dev@open-iov.org> | 2026-09-23 05:44:08 -0400 |
|---|---|---|
| committer | Open-IOV <dev@open-iov.org> | 2026-09-23 05:46:43 -0400 |
| commit | 2302fc09080bad51c73f293294e19fd4db464eb0 (patch) | |
| tree | c722d186347fdef5a34131e9e143b1549b1daf8e /wiki/open-iov.org/index.php | |
| download | open-iov-2302fc09080bad51c73f293294e19fd4db464eb0.tar.gz open-iov-2302fc09080bad51c73f293294e19fd4db464eb0.zip | |
Open-IOV: initial public release
Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with
real GPU functionality - CUDA first, 3D and video to follow - on unmodified
hosts, without a proprietary vGPU license and without patching any driver,
firmware or hypervisor.
Core principle: emulate the interface, pass through the work.
kernel/ open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device
(PCI config space, BAR shadows, MSI-X), GSP boot emulation,
GSP-RM message-queue/RPC emulation, memory model (GPU-VA to
guest-PA discovery) and the semaphore-completion service that
advances guest UVM progress.
userspace/ libiov.so management API and examples.
tools/ guest diagnostics, firmware analysis wrappers, RM probes.
scripts/ stack manager, VM harness, build/load/test automation.
config/ hardware/version profiles (the portability surface).
docs/ documentation tree - start at docs/README.md.
wiki/ long-form firmware and protocol deep dives.
Status: initialization works end to end for a stock 570.144 Linux guest on
Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery,
object creation and the early CUDA/UVM start-up path. GPU work forwarding -
the step that makes CUDA kernels execute on real hardware - is the active
work item; see docs/04-implementation/01-known-knowns-and-unknowns.md.
License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link
GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md.
Diffstat (limited to 'wiki/open-iov.org/index.php')
122 files changed, 32441 insertions, 0 deletions
diff --git a/wiki/open-iov.org/index.php/AMDGPU.html b/wiki/open-iov.org/index.php/AMDGPU.html new file mode 100644 index 0000000..47c05f6 --- /dev/null +++ b/wiki/open-iov.org/index.php/AMDGPU.html @@ -0,0 +1,220 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>AMDGPU - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"d80ade6fa88063f5c2f9a158","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"AMDGPU","wgTitle":"AMDGPU","wgCurRevisionId":23746,"wgRevisionId":23746,"wgArticleId":88,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"AMDGPU","wgRelevantArticleId":88,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"}, +"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/CPU_Support.html b/wiki/open-iov.org/index.php/CPU_Support.html new file mode 100644 index 0000000..9ba71c7 --- /dev/null +++ b/wiki/open-iov.org/index.php/CPU_Support.html @@ -0,0 +1,233 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>CPU Support - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"d053896bb328dfb6375e7f5b","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"CPU_Support","wgTitle":"CPU Support","wgCurRevisionId":23744,"wgRevisionId":23744,"wgArticleId":22,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"CPU_Support","wgRelevantArticleId":22,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks": +"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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If your motherboard manufacturer has not made an update available you may need to apply an <a rel="nofollow" class="external text" href="https://vfio.blogspot.com/2014/08/iommu-groups-inside-and-out.html">ACS override patch</a>. Successive AMD CPU platforms are unaffected.</i> +</p> +<!-- +NewPP limit report +Cached time: 20260911162046 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.003 seconds +Real time usage: 0.003 seconds +Preprocessor visited node count: 9/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:22-0!canonical and timestamp 20260911162046 and revision id 23744. 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Serialized with JSON. + --> +</div></div><h2 id="filehistory">File history</h2> +<div id="mw-imagepage-section-filehistory"> +<p>Click on a date/time to view the file as it appeared at that time. +</p> +<table class="wikitable filehistory"> +<tr><th></th><th>Date/Time</th><th>Thumbnail</th><th>Dimensions</th><th>User</th><th>Comment</th></tr> +<tr><td>current</td><td class='filehistory-selected' style='white-space: nowrap;'><a href="../images/3/33/IOCTL_set_VFIO_container.png">18:37, 26 April 2022</a></td><td><a href="../images/3/33/IOCTL_set_VFIO_container.png"><img alt="Thumbnail for version as of 18:37, 26 April 2022" src="../images/thumb/3/33/IOCTL_set_VFIO_container.png/120px-IOCTL_set_VFIO_container.png" decoding="async" width="120" height="97" /></a></td><td>1,722 × 1,390 <span style="white-space: nowrap;">(113 KB)</span></td><td><a href="../index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html" class="new mw-userlink" title="User:Arthur (page does not exist)"><bdi>Arthur</bdi></a><span style="white-space: nowrap;"> <span class="mw-usertoollinks">(<a href="../index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html" class="new mw-usertoollinks-talk" title="User talk:Arthur (page does not exist)">talk</a> | <a href="./Special:Contributions/Arthur.html" class="mw-usertoollinks-contribs" title="Special:Contributions/Arthur">contribs</a>)</span></span></td><td dir="ltr"></td></tr> +</table> + +</div> +<div class="mw-imagepage-upload-links"><p id="mw-imagepage-upload-disallowed">You cannot overwrite this file.</p></div><h2 id="filelinks">File usage</h2> +<div id='mw-imagepage-section-linkstoimage'> +<p>The following page uses this file: +</p><ul class="mw-imagepage-linkstoimage"> +<li class="mw-imagepage-linkstoimage-ns0"><a href="Virtual_I/O_Internals.html" title="Virtual I/O Internals">Virtual I/O Internals</a></li> +</ul> +</div> + +<div class="printfooter">Retrieved from "<a dir="ltr" href="../index.php%3Ftitle=File:IOCTL_set_VFIO_container.png&oldid=343.html">https://open-iov.org/index.php?title=File:IOCTL_set_VFIO_container.png&oldid=343</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" class="mw-list-item"><a href="../index.php%3Ftitle=Special:UserLogin&returnto=File:IOCTL+set+VFIO+container.png.html" title="You are encouraged to log in; however, it is not mandatory [o]" accesskey="o">Log in</a></li></ul> + + </div> +</nav> + + <div id="left-navigation"> + <nav id="p-namespaces" class="mw-portlet mw-portlet-namespaces vector-menu vector-menu-tabs" aria-labelledby="p-namespaces-label" role="navigation" + > + <h3 id="p-namespaces-label" class="vector-menu-heading"> <span>Namespaces</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-nstab-image" class="selected mw-list-item"><a href="./File:IOCTL_set_VFIO_container.png.html" title="View the file page [c]" accesskey="c">File</a></li><li id="ca-talk" class="new mw-list-item"><a href="https://open-iov.org/index.php?title=File_talk:IOCTL_set_VFIO_container.png&action=edit&redlink=1" rel="discussion" title="Discussion about the content page (page does not exist) [t]" accesskey="t">Discussion</a></li></ul> + + </div> +</nav> + + <nav id="p-variants" class="mw-portlet mw-portlet-variants emptyPortlet vector-menu-dropdown-noicon vector-menu vector-menu-dropdown" aria-labelledby="p-variants-label" role="navigation" + > + <input type="checkbox" + id="p-variants-checkbox" + role="button" + aria-haspopup="true" + data-event-name="ui.dropdown-p-variants" + class=" vector-menu-checkbox" aria-labelledby="p-variants-label" /> + <h3 id="p-variants-label" class="vector-menu-heading"> <span>Variants</span> + <span class="vector-menu-checkbox-expanded">expanded</span> + <span class="vector-menu-checkbox-collapsed">collapsed</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"></ul> + + </div> +</nav> + + </div> + <div id="right-navigation"> + <nav id="p-views" class="mw-portlet mw-portlet-views vector-menu vector-menu-tabs" aria-labelledby="p-views-label" role="navigation" + > + <h3 id="p-views-label" class="vector-menu-heading"> <span>Views</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-view" class="selected mw-list-item"><a href="./File:IOCTL_set_VFIO_container.png.html">Read</a></li><li id="ca-viewsource" class="mw-list-item"><a href="../index.php%3Ftitle=File:IOCTL_set_VFIO_container.png&action=edit.html" title="This page is protected. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:IVSHMEM.png.html b/wiki/open-iov.org/index.php/File:IVSHMEM.png.html new file mode 100644 index 0000000..664339d --- /dev/null +++ b/wiki/open-iov.org/index.php/File:IVSHMEM.png.html @@ -0,0 +1,233 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>File:IVSHMEM.png - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"c642e2fc91bf0d719fd9cf0d","wgCSPNonce":!1,"wgCanonicalNamespace":"File","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":6,"wgPageName":"File:IVSHMEM.png","wgTitle":"IVSHMEM.png","wgCurRevisionId":45,"wgRevisionId":45,"wgArticleId":14,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"File:IVSHMEM.png","wgRelevantArticleId":14,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRestrictionUpload":[],"wgVisualEditor":{"pageLanguageCode":"en", +"pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","filepage":"ready","mediawiki.action.view.filepage":"ready","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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Serialized with JSON. + --> +</div></div><h2 id="filehistory">File history</h2> +<div id="mw-imagepage-section-filehistory"> +<p>Click on a date/time to view the file as it appeared at that time. +</p> +<table class="wikitable filehistory"> +<tr><th></th><th>Date/Time</th><th>Thumbnail</th><th>Dimensions</th><th>User</th><th>Comment</th></tr> +<tr><td>current</td><td class='filehistory-selected' style='white-space: nowrap;'><a href="../images/d/d3/IVSHMEM.png">00:45, 18 December 2021</a></td><td><a href="../images/d/d3/IVSHMEM.png"><img alt="Thumbnail for version as of 00:45, 18 December 2021" src="../images/thumb/d/d3/IVSHMEM.png/120px-IVSHMEM.png" decoding="async" width="120" height="81" /></a></td><td>834 × 564 <span style="white-space: nowrap;">(29 KB)</span></td><td><a href="../index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html" class="new mw-userlink" title="User:Arthur (page does not exist)"><bdi>Arthur</bdi></a><span style="white-space: nowrap;"> <span class="mw-usertoollinks">(<a href="../index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html" class="new mw-usertoollinks-talk" title="User talk:Arthur (page does not exist)">talk</a> | <a href="./Special:Contributions/Arthur.html" class="mw-usertoollinks-contribs" title="Special:Contributions/Arthur">contribs</a>)</span></span></td><td dir="ltr"></td></tr> +</table> + +</div> +<div class="mw-imagepage-upload-links"><p id="mw-imagepage-upload-disallowed">You cannot overwrite this file.</p></div><h2 id="filelinks">File usage</h2> +<div id='mw-imagepage-section-linkstoimage'> +<p>The following page uses this file: +</p><ul class="mw-imagepage-linkstoimage"> +<li class="mw-imagepage-linkstoimage-ns0"><a href="Glossary.html" title="Glossary">Glossary</a></li> +</ul> +</div> + +<div class="printfooter">Retrieved from "<a dir="ltr" href="../index.php%3Ftitle=File:IVSHMEM.png&oldid=45.html">https://open-iov.org/index.php?title=File:IVSHMEM.png&oldid=45</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" class="mw-list-item"><a href="../index.php%3Ftitle=Special:UserLogin&returnto=File:IVSHMEM.png.html" title="You are encouraged to log in; however, it is not mandatory [o]" accesskey="o">Log in</a></li></ul> + + </div> +</nav> + + <div id="left-navigation"> + <nav id="p-namespaces" class="mw-portlet mw-portlet-namespaces vector-menu vector-menu-tabs" aria-labelledby="p-namespaces-label" role="navigation" + > + <h3 id="p-namespaces-label" class="vector-menu-heading"> <span>Namespaces</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-nstab-image" class="selected mw-list-item"><a href="./File:IVSHMEM.png.html" title="View the file page [c]" accesskey="c">File</a></li><li id="ca-talk" class="new mw-list-item"><a href="https://open-iov.org/index.php?title=File_talk:IVSHMEM.png&action=edit&redlink=1" rel="discussion" title="Discussion about the content page (page does not exist) [t]" accesskey="t">Discussion</a></li></ul> + + </div> +</nav> + + <nav id="p-variants" class="mw-portlet mw-portlet-variants emptyPortlet vector-menu-dropdown-noicon vector-menu vector-menu-dropdown" aria-labelledby="p-variants-label" role="navigation" + > + <input type="checkbox" + id="p-variants-checkbox" + role="button" + aria-haspopup="true" + data-event-name="ui.dropdown-p-variants" + class=" vector-menu-checkbox" aria-labelledby="p-variants-label" /> + <h3 id="p-variants-label" class="vector-menu-heading"> <span>Variants</span> + <span class="vector-menu-checkbox-expanded">expanded</span> + <span class="vector-menu-checkbox-collapsed">collapsed</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"></ul> + + </div> +</nav> + + </div> + <div id="right-navigation"> + <nav id="p-views" class="mw-portlet mw-portlet-views vector-menu vector-menu-tabs" aria-labelledby="p-views-label" role="navigation" + > + <h3 id="p-views-label" class="vector-menu-heading"> <span>Views</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-view" class="selected mw-list-item"><a href="./File:IVSHMEM.png.html">Read</a></li><li id="ca-viewsource" class="mw-list-item"><a href="../index.php%3Ftitle=File:IVSHMEM.png&action=edit.html" title="This page is protected. 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class="mw-content-ltr"><div class="mw-parser-output"><p>QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs +</p> +<!-- +NewPP limit report +Cached time: 20260911202711 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.000 seconds +Real time usage: 0.000 seconds +Preprocessor visited node count: 1/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 1/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:66-0!canonical and timestamp 20260911202711 and revision id 487. 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Serialized with JSON. + --> +</div></div><h2 id="filehistory">File history</h2> +<div id="mw-imagepage-section-filehistory"> +<p>Click on a date/time to view the file as it appeared at that time. +</p> +<table class="wikitable filehistory"> +<tr><th></th><th>Date/Time</th><th>Thumbnail</th><th>Dimensions</th><th>User</th><th>Comment</th></tr> +<tr><td>current</td><td class='filehistory-selected' style='white-space: nowrap;'><a href="../images/2/2b/Telescope_LG-Proxy.png">17:37, 20 April 2022</a></td><td><a href="../images/2/2b/Telescope_LG-Proxy.png"><img alt="Thumbnail for version as of 17:37, 20 April 2022" src="../images/thumb/2/2b/Telescope_LG-Proxy.png/120px-Telescope_LG-Proxy.png" decoding="async" width="120" height="67" /></a></td><td>2,524 × 1,408 <span style="white-space: nowrap;">(213 KB)</span></td><td><a href="../index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html" class="new mw-userlink" title="User:Arthur (page does not exist)"><bdi>Arthur</bdi></a><span style="white-space: nowrap;"> <span class="mw-usertoollinks">(<a href="../index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html" class="new mw-usertoollinks-talk" title="User talk:Arthur (page does not exist)">talk</a> | <a href="./Special:Contributions/Arthur.html" class="mw-usertoollinks-contribs" title="Special:Contributions/Arthur">contribs</a>)</span></span></td><td dir="ltr"></td></tr> +</table> + +</div> +<div class="mw-imagepage-upload-links"><p id="mw-imagepage-upload-disallowed">You cannot overwrite this file.</p></div><h2 id="filelinks">File usage</h2> +<div id='mw-imagepage-section-linkstoimage'> +<p>The following page uses this file: +</p><ul class="mw-imagepage-linkstoimage"> +<li class="mw-imagepage-linkstoimage-ns0"><a href="Looking_Glass_KVMFR.html" title="Looking Glass KVMFR">Looking Glass KVMFR</a></li> +</ul> +</div> + +<div class="printfooter">Retrieved from "<a dir="ltr" href="../index.php%3Ftitle=File:Telescope_LG-Proxy.png&oldid=296.html">https://open-iov.org/index.php?title=File:Telescope_LG-Proxy.png&oldid=296</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" class="mw-list-item"><a href="../index.php%3Ftitle=Special:UserLogin&returnto=File:Telescope+LG-Proxy.png.html" title="You are encouraged to log in; however, it is not mandatory [o]" accesskey="o">Log in</a></li></ul> + + </div> +</nav> + + <div id="left-navigation"> + <nav id="p-namespaces" class="mw-portlet mw-portlet-namespaces vector-menu vector-menu-tabs" aria-labelledby="p-namespaces-label" role="navigation" + > + <h3 id="p-namespaces-label" class="vector-menu-heading"> <span>Namespaces</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-nstab-image" class="selected mw-list-item"><a href="./File:Telescope_LG-Proxy.png.html" title="View the file page [c]" accesskey="c">File</a></li><li id="ca-talk" class="new mw-list-item"><a href="https://open-iov.org/index.php?title=File_talk:Telescope_LG-Proxy.png&action=edit&redlink=1" rel="discussion" title="Discussion about the content page (page does not exist) [t]" accesskey="t">Discussion</a></li></ul> + + </div> +</nav> + + <nav id="p-variants" class="mw-portlet mw-portlet-variants emptyPortlet vector-menu-dropdown-noicon vector-menu vector-menu-dropdown" aria-labelledby="p-variants-label" role="navigation" + > + <input type="checkbox" + id="p-variants-checkbox" + role="button" + aria-haspopup="true" + data-event-name="ui.dropdown-p-variants" + class=" vector-menu-checkbox" aria-labelledby="p-variants-label" /> + <h3 id="p-variants-label" class="vector-menu-heading"> <span>Variants</span> + <span class="vector-menu-checkbox-expanded">expanded</span> + <span class="vector-menu-checkbox-collapsed">collapsed</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"></ul> + + </div> +</nav> + + </div> + <div id="right-navigation"> + <nav id="p-views" class="mw-portlet mw-portlet-views vector-menu vector-menu-tabs" aria-labelledby="p-views-label" role="navigation" + > + <h3 id="p-views-label" class="vector-menu-heading"> <span>Views</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-view" class="selected mw-list-item"><a href="./File:Telescope_LG-Proxy.png.html">Read</a></li><li id="ca-viewsource" class="mw-list-item"><a href="../index.php%3Ftitle=File:Telescope_LG-Proxy.png&action=edit.html" title="This page is protected. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Vfio-pci_driver_bindings.png.html b/wiki/open-iov.org/index.php/File:Vfio-pci_driver_bindings.png.html new file mode 100644 index 0000000..2a730b6 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Vfio-pci_driver_bindings.png.html @@ -0,0 +1,233 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>File:Vfio-pci driver bindings.png - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"fe7a7c2888095855d8fec189","wgCSPNonce":!1,"wgCanonicalNamespace":"File","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":6,"wgPageName":"File:Vfio-pci_driver_bindings.png","wgTitle":"Vfio-pci driver bindings.png","wgCurRevisionId":341,"wgRevisionId":341,"wgArticleId":47,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"File:Vfio-pci_driver_bindings.png","wgRelevantArticleId":47,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRestrictionUpload":[], +"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","filepage":"ready","mediawiki.action.view.filepage":"ready","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/File:Virgl.png.html b/wiki/open-iov.org/index.php/File:Virgl.png.html new file mode 100644 index 0000000..0c18802 --- /dev/null +++ b/wiki/open-iov.org/index.php/File:Virgl.png.html @@ -0,0 +1,233 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>File:Virgl.png - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"6dc27acabf1e4c5a6054ac18","wgCSPNonce":!1,"wgCanonicalNamespace":"File","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":6,"wgPageName":"File:Virgl.png","wgTitle":"Virgl.png","wgCurRevisionId":52,"wgRevisionId":52,"wgArticleId":20,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"File:Virgl.png","wgRelevantArticleId":20,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRestrictionUpload":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir": +"ltr","pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","filepage":"ready","mediawiki.action.view.filepage":"ready","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/GPU_Driver_Internals.html b/wiki/open-iov.org/index.php/GPU_Driver_Internals.html new file mode 100644 index 0000000..30a0652 --- /dev/null +++ b/wiki/open-iov.org/index.php/GPU_Driver_Internals.html @@ -0,0 +1,661 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>GPU Driver Internals - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"47297d43fa3b1a02456ceadd","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"GPU_Driver_Internals","wgTitle":"GPU Driver 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+</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-GPU_Driver_Internals rootpage-GPU_Driver_Internals skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >GPU Driver Internals</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="GPU_Driver_Internals.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="GPU_Driver_Internals.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>This page will detail the internals of various GPU drivers for use with I/O Virtualization.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="GPU_Driver_Internals.html#Article_Structure"><span class="tocnumber">1</span> <span class="toctext">Article Structure</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="GPU_Driver_Internals.html#High_Level_Architecture"><span class="tocnumber">1.1</span> <span class="toctext">High Level Architecture</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="GPU_Driver_Internals.html#Initialization"><span class="tocnumber">1.2</span> <span class="toctext">Initialization</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="GPU_Driver_Internals.html#Scheduling"><span class="tocnumber">1.3</span> <span class="toctext">Scheduling</span></a> +<ul> +<li class="toclevel-3 tocsection-5"><a href="GPU_Driver_Internals.html#In-VM_Scheduling"><span class="tocnumber">1.3.1</span> <span class="toctext">In-VM Scheduling</span></a></li> +<li class="toclevel-3 tocsection-6"><a href="GPU_Driver_Internals.html#Between-VM_Scheduling"><span class="tocnumber">1.3.2</span> <span class="toctext">Between-VM Scheduling</span></a></li> +<li class="toclevel-3 tocsection-7"><a href="GPU_Driver_Internals.html#Firmware_Scheduling_(if_applicable)"><span class="tocnumber">1.3.3</span> <span class="toctext">Firmware Scheduling (if applicable)</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-8"><a href="GPU_Driver_Internals.html#Memory_Management"><span class="tocnumber">1.4</span> <span class="toctext">Memory Management</span></a></li> +<li class="toclevel-2 tocsection-9"><a href="GPU_Driver_Internals.html#Display_Surface_Virtualization"><span class="tocnumber">1.5</span> <span class="toctext">Display Surface Virtualization</span></a> +<ul> +<li class="toclevel-3 tocsection-10"><a href="GPU_Driver_Internals.html#Graphics_Buffer_Sharing"><span class="tocnumber">1.5.1</span> <span class="toctext">Graphics Buffer Sharing</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-1 tocsection-11"><a href="GPU_Driver_Internals.html#Vendor_Neutral"><span class="tocnumber">2</span> <span class="toctext">Vendor Neutral</span></a> +<ul> +<li class="toclevel-2 tocsection-12"><a href="GPU_Driver_Internals.html#Knowledge_Resources_Used"><span class="tocnumber">2.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-13"><a href="GPU_Driver_Internals.html#Display_Surface_Virtualization_2"><span class="tocnumber">2.2</span> <span class="toctext">Display Surface Virtualization</span></a> +<ul> +<li class="toclevel-3 tocsection-14"><a href="GPU_Driver_Internals.html#Graphics_Buffer_Sharing_2"><span class="tocnumber">2.2.1</span> <span class="toctext">Graphics Buffer Sharing</span></a> +<ul> +<li class="toclevel-4 tocsection-15"><a href="GPU_Driver_Internals.html#Display_Flow_in_Linux"><span class="tocnumber">2.2.1.1</span> <span class="toctext">Display Flow in Linux</span></a></li> +<li class="toclevel-4 tocsection-16"><a href="GPU_Driver_Internals.html#SR-IOV_and_Mdev"><span class="tocnumber">2.2.1.2</span> <span class="toctext">SR-IOV and Mdev</span></a></li> +<li class="toclevel-4 tocsection-17"><a href="GPU_Driver_Internals.html#VFs_in_QEMU_Hypervisor_(VirtIO-GPU)"><span class="tocnumber">2.2.1.3</span> <span class="toctext">VFs in QEMU Hypervisor (VirtIO-GPU)</span></a></li> +<li class="toclevel-4 tocsection-18"><a href="GPU_Driver_Internals.html#Transport"><span class="tocnumber">2.2.1.4</span> <span class="toctext">Transport</span></a> +<ul> +<li class="toclevel-5 tocsection-19"><a href="GPU_Driver_Internals.html#QEMU_Host-Side_u-dma-buf"><span class="tocnumber">2.2.1.4.1</span> <span class="toctext">QEMU Host-Side u-dma-buf</span></a></li> +<li class="toclevel-5 tocsection-20"><a href="GPU_Driver_Internals.html#QEMU_Host-Side_Modules"><span class="tocnumber">2.2.1.4.2</span> <span class="toctext">QEMU Host-Side Modules</span></a></li> +</ul> +</li> +<li class="toclevel-4 tocsection-21"><a href="GPU_Driver_Internals.html#Windows_VFs"><span class="tocnumber">2.2.1.5</span> <span class="toctext">Windows VFs</span></a></li> +<li class="toclevel-4 tocsection-22"><a href="GPU_Driver_Internals.html#Windows_Driver_Stack"><span class="tocnumber">2.2.1.6</span> <span class="toctext">Windows Driver Stack</span></a></li> +<li class="toclevel-4 tocsection-23"><a href="GPU_Driver_Internals.html#DVServer_KMD"><span class="tocnumber">2.2.1.7</span> <span class="toctext">DVServer KMD</span></a></li> +<li class="toclevel-4 tocsection-24"><a href="GPU_Driver_Internals.html#Android_VFs"><span class="tocnumber">2.2.1.8</span> <span class="toctext">Android VFs</span></a></li> +</ul> +</li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-1 tocsection-25"><a href="GPU_Driver_Internals.html#i915"><span class="tocnumber">3</span> <span class="toctext">i915</span></a> +<ul> +<li class="toclevel-2 tocsection-26"><a href="GPU_Driver_Internals.html#Knowledge_Resources_Used_2"><span class="tocnumber">3.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-27"><a href="GPU_Driver_Internals.html#High_Level_Architecture_2"><span class="tocnumber">3.2</span> <span class="toctext">High Level Architecture</span></a> +<ul> +<li class="toclevel-3 tocsection-28"><a href="GPU_Driver_Internals.html#i915_Clients"><span class="tocnumber">3.2.1</span> <span class="toctext">i915 Clients</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-29"><a href="GPU_Driver_Internals.html#Initialization_2"><span class="tocnumber">3.3</span> <span class="toctext">Initialization</span></a></li> +<li class="toclevel-2 tocsection-30"><a href="GPU_Driver_Internals.html#Scheduling_2"><span class="tocnumber">3.4</span> <span class="toctext">Scheduling</span></a> +<ul> +<li class="toclevel-3 tocsection-31"><a href="GPU_Driver_Internals.html#In-VM_Scheduling_2"><span class="tocnumber">3.4.1</span> <span class="toctext">In-VM Scheduling</span></a></li> +<li class="toclevel-3 tocsection-32"><a href="GPU_Driver_Internals.html#Guest_kernel_(i915.ko)"><span class="tocnumber">3.4.2</span> <span class="toctext">Guest kernel (i915.ko)</span></a> +<ul> +<li class="toclevel-4 tocsection-33"><a href="GPU_Driver_Internals.html#vExeclist"><span class="tocnumber">3.4.2.1</span> <span class="toctext">vExeclist</span></a></li> +<li class="toclevel-4 tocsection-34"><a href="GPU_Driver_Internals.html#vGuC"><span class="tocnumber">3.4.2.2</span> <span class="toctext">vGuC</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-35"><a href="GPU_Driver_Internals.html#Between-VM_Scheduling_2"><span class="tocnumber">3.4.3</span> <span class="toctext">Between-VM Scheduling</span></a> +<ul> +<li class="toclevel-4 tocsection-36"><a href="GPU_Driver_Internals.html#Host_kernel_(i915.ko)"><span class="tocnumber">3.4.3.1</span> <span class="toctext">Host kernel (i915.ko)</span></a> +<ul> +<li class="toclevel-5 tocsection-37"><a href="GPU_Driver_Internals.html#Execlist"><span class="tocnumber">3.4.3.1.1</span> <span class="toctext">Execlist</span></a></li> +<li class="toclevel-5 tocsection-38"><a href="GPU_Driver_Internals.html#GuC"><span class="tocnumber">3.4.3.1.2</span> <span class="toctext">GuC</span></a></li> +</ul> +</li> +<li class="toclevel-4 tocsection-39"><a href="GPU_Driver_Internals.html#Device_Firmware_(GuC)"><span class="tocnumber">3.4.3.2</span> <span class="toctext">Device Firmware (GuC)</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-40"><a href="GPU_Driver_Internals.html#Memory_Management_2"><span class="tocnumber">3.5</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-41"><a href="GPU_Driver_Internals.html#Translation_Tables"><span class="tocnumber">3.5.1</span> <span class="toctext">Translation Tables</span></a> +<ul> +<li class="toclevel-4 tocsection-42"><a href="GPU_Driver_Internals.html#GTT_(Graphics_Translation_Table)"><span class="tocnumber">3.5.1.1</span> <span class="toctext">GTT (Graphics Translation Table)</span></a></li> +<li class="toclevel-4 tocsection-43"><a href="GPU_Driver_Internals.html#GGTT_(Global_Graphics_Translation_Table)"><span class="tocnumber">3.5.1.2</span> <span class="toctext">GGTT (Global Graphics Translation Table)</span></a></li> +<li class="toclevel-4 tocsection-44"><a href="GPU_Driver_Internals.html#PPGTT_(Per_Process_Graphics_Translation_Table)"><span class="tocnumber">3.5.1.3</span> <span class="toctext">PPGTT (Per Process Graphics Translation Table)</span></a></li> +<li class="toclevel-4 tocsection-45"><a href="GPU_Driver_Internals.html#Aliasing_PPGTT"><span class="tocnumber">3.5.1.4</span> <span class="toctext">Aliasing PPGTT</span></a></li> +<li class="toclevel-4 tocsection-46"><a href="GPU_Driver_Internals.html#Real_PPGTT"><span class="tocnumber">3.5.1.5</span> <span class="toctext">Real PPGTT</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-47"><a href="GPU_Driver_Internals.html#Display_Surface_Virtualization_3"><span class="tocnumber">3.6</span> <span class="toctext">Display Surface Virtualization</span></a> +<ul> +<li class="toclevel-3 tocsection-48"><a href="GPU_Driver_Internals.html#VirtIO-GPU"><span class="tocnumber">3.6.1</span> <span class="toctext">VirtIO-GPU</span></a></li> +<li class="toclevel-3 tocsection-49"><a href="GPU_Driver_Internals.html#IDD_(Indirect_Display_Driver)"><span class="tocnumber">3.6.2</span> <span class="toctext">IDD (Indirect Display Driver)</span></a></li> +<li class="toclevel-3 tocsection-50"><a href="GPU_Driver_Internals.html#Graphics_Buffer_Sharing_3"><span class="tocnumber">3.6.3</span> <span class="toctext">Graphics Buffer Sharing</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-1 tocsection-51"><a href="GPU_Driver_Internals.html#OpenRM"><span class="tocnumber">4</span> <span class="toctext">OpenRM</span></a> +<ul> +<li class="toclevel-2 tocsection-52"><a href="GPU_Driver_Internals.html#Knowledge_Resources_Used_3"><span class="tocnumber">4.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-53"><a href="GPU_Driver_Internals.html#High_Level_Architecture_3"><span class="tocnumber">4.2</span> <span class="toctext">High Level Architecture</span></a> +<ul> +<li class="toclevel-3 tocsection-54"><a href="GPU_Driver_Internals.html#RM_Clients"><span class="tocnumber">4.2.1</span> <span class="toctext">RM Clients</span></a></li> +<li class="toclevel-3 tocsection-55"><a href="GPU_Driver_Internals.html#RM_Server"><span class="tocnumber">4.2.2</span> <span class="toctext">RM Server</span></a></li> +<li class="toclevel-3 tocsection-56"><a href="GPU_Driver_Internals.html#RM_API"><span class="tocnumber">4.2.3</span> <span class="toctext">RM API</span></a></li> +<li class="toclevel-3 tocsection-57"><a href="GPU_Driver_Internals.html#RM_Core"><span class="tocnumber">4.2.4</span> <span class="toctext">RM Core</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-58"><a href="GPU_Driver_Internals.html#Initialization_3"><span class="tocnumber">4.3</span> <span class="toctext">Initialization</span></a></li> +<li class="toclevel-2 tocsection-59"><a href="GPU_Driver_Internals.html#Scheduling_3"><span class="tocnumber">4.4</span> <span class="toctext">Scheduling</span></a> +<ul> +<li class="toclevel-3 tocsection-60"><a href="GPU_Driver_Internals.html#Command_Submission"><span class="tocnumber">4.4.1</span> <span class="toctext">Command Submission</span></a> +<ul> +<li class="toclevel-4 tocsection-61"><a href="GPU_Driver_Internals.html#Runlist"><span class="tocnumber">4.4.1.1</span> <span class="toctext">Runlist</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-62"><a href="GPU_Driver_Internals.html#In-VM_Scheduling_3"><span class="tocnumber">4.4.2</span> <span class="toctext">In-VM Scheduling</span></a> +<ul> +<li class="toclevel-4 tocsection-63"><a href="GPU_Driver_Internals.html#Guest_kernel_(nvidia.ko)"><span class="tocnumber">4.4.2.1</span> <span class="toctext">Guest kernel (nvidia.ko)</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-64"><a href="GPU_Driver_Internals.html#Between-VM_Scheduling_3"><span class="tocnumber">4.4.3</span> <span class="toctext">Between-VM Scheduling</span></a> +<ul> +<li class="toclevel-4 tocsection-65"><a href="GPU_Driver_Internals.html#Host_kernel_(nvidia.ko)"><span class="tocnumber">4.4.3.1</span> <span class="toctext">Host kernel (nvidia.ko)</span></a></li> +<li class="toclevel-4 tocsection-66"><a href="GPU_Driver_Internals.html#Host_usermode_(nvidia-vgpu-mgr_/_libnvidia-vgpu.so)"><span class="tocnumber">4.4.3.2</span> <span class="toctext">Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)</span></a></li> +<li class="toclevel-4 tocsection-67"><a href="GPU_Driver_Internals.html#nvidia-vgpu-mgr"><span class="tocnumber">4.4.3.3</span> <span class="toctext">nvidia-vgpu-mgr</span></a> +<ul> +<li class="toclevel-5 tocsection-68"><a href="GPU_Driver_Internals.html#vmiop"><span class="tocnumber">4.4.3.3.1</span> <span class="toctext">vmiop</span></a></li> +</ul> +</li> +<li class="toclevel-4 tocsection-69"><a href="GPU_Driver_Internals.html#Device_Firmware_(GSP)"><span class="tocnumber">4.4.3.4</span> <span class="toctext">Device Firmware (GSP)</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-70"><a href="GPU_Driver_Internals.html#Memory_Management_3"><span class="tocnumber">4.5</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-71"><a href="GPU_Driver_Internals.html#Programming_the_MMU"><span class="tocnumber">4.5.1</span> <span class="toctext">Programming the MMU</span></a> +<ul> +<li class="toclevel-4 tocsection-72"><a href="GPU_Driver_Internals.html#AMAPLibrary"><span class="tocnumber">4.5.1.1</span> <span class="toctext">AMAPLibrary</span></a></li> +<li class="toclevel-4 tocsection-73"><a href="GPU_Driver_Internals.html#Architecture_HALs"><span class="tocnumber">4.5.1.2</span> <span class="toctext">Architecture HALs</span></a></li> +<li class="toclevel-4 tocsection-74"><a href="GPU_Driver_Internals.html#DMA_from_Falcon_/_NvRISC-V_to_Frame_Buffer_Interface_(FBIF)"><span class="tocnumber">4.5.1.3</span> <span class="toctext">DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-75"><a href="GPU_Driver_Internals.html#Translation_Tables_2"><span class="tocnumber">4.5.2</span> <span class="toctext">Translation Tables</span></a> +<ul> +<li class="toclevel-4 tocsection-76"><a href="GPU_Driver_Internals.html#vmiop_gva"><span class="tocnumber">4.5.2.1</span> <span class="toctext">vmiop_gva</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-77"><a href="GPU_Driver_Internals.html#Display_Surface_Virtualization_4"><span class="tocnumber">4.6</span> <span class="toctext">Display Surface Virtualization</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-78"><a href="GPU_Driver_Internals.html#amdgpu"><span class="tocnumber">5</span> <span class="toctext">amdgpu</span></a></li> +<li class="toclevel-1 tocsection-79"><a href="GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)"><span class="tocnumber">6</span> <span class="toctext">References (Talks & Reading Material)</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="Article_Structure">Article Structure</span></h2> +<p>This article will aim to provide information about the following details of GPU drivers: +</p> +<h3><span class="mw-headline" id="High_Level_Architecture">High Level Architecture</span></h3> +<p>This section will detail high level architectures of each driver. +</p> +<h3><span class="mw-headline" id="Initialization">Initialization</span></h3> +<p>This section will cover how the GPU's embedded components, the GPU driver, and virtualization functions are initialized. +</p> +<h3><span class="mw-headline" id="Scheduling">Scheduling</span></h3> +<p>This section will detail how the device schedules instructions for execution. +</p><p>This will attempt to provide a comprehensive view of scheduling from virtualized processes down to execution within the device. +</p> +<h4><span class="mw-headline" id="In-VM_Scheduling">In-VM Scheduling</span></h4> +<p>The In-VM Scheduling section will detail how instructions scheduled within the virtual machine's GPU device driver. +</p> +<h4><span class="mw-headline" id="Between-VM_Scheduling">Between-VM Scheduling</span></h4> +<p>The Between-VM Scheduling section will detail how the host kernel module and/or virtual GPU helper functions handle scheduling / context swaps between virtual machines on a computer system. +</p> +<h4><span id="Firmware_Scheduling_.28if_applicable.29"></span><span class="mw-headline" id="Firmware_Scheduling_(if_applicable)">Firmware Scheduling (if applicable)</span></h4> +<p>The Firmware Scheduling section will cover the GPU's internal scheduling model if a deferred execution pathway is used (like i915's GuC or OpenRM's GSP). +</p><p>In the case an intermediate scheduling microcontroller is not used this section may be less applicable (ie: vExeclist scheduling under Intel vGPUs). +</p> +<h3><span class="mw-headline" id="Memory_Management">Memory Management</span></h3> +<p>The Memory Management section will cover how the GPU driver manages memory for virtual GPUs and host processes. +</p><p>This will aim detail paging abstractions used for global memory translation, and per-process memory translation. +</p> +<h3><span class="mw-headline" id="Display_Surface_Virtualization">Display Surface Virtualization</span></h3> +<p>The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +</p> +<h4><span class="mw-headline" id="Graphics_Buffer_Sharing">Graphics Buffer Sharing</span></h4> +<p>This section will cover methods provided by the GPU driver suitable for high performance graphics sharing. +</p> +<h2><span class="mw-headline" id="Vendor_Neutral">Vendor Neutral</span></h2> +<p>This section will detail functions in common between GPU drivers. +</p><p>Also see <a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS">Display Virtualization for Windows OS</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions to documentation and open source by <b>Satyeshwar Singh</b>. +</p> +<h3><span class="mw-headline" id="Display_Surface_Virtualization_2">Display Surface Virtualization</span></h3> +<p>The Display Surface Virtualization section will detail how virtual displays are provided to guests and/or graphics rendering buffers (pixel surfaces) are shared from guest to host if such functions are provided via the driver. +</p> +<h4><span class="mw-headline" id="Graphics_Buffer_Sharing_2">Graphics Buffer Sharing</span></h4> +<p>This section will deal with graphics buffer sharing for vendor neutral GPUs. +</p> +<h5><span class="mw-headline" id="Display_Flow_in_Linux">Display Flow in Linux</span></h5> +<p>Userspace applications provide their buffers to compositor. +</p><p>Compositor asks Mesa to create a framebuffer. +</p><p>Framebuffer is allocated through vendor driver. +</p><p>Vendor driver flips the framebuffer on the screen. +</p> +<h5><span class="mw-headline" id="SR-IOV_and_Mdev">SR-IOV and Mdev</span></h5> +<p>SR-IOV VFs don't have access to the display controller (only PF does). +</p><p>Known issue is displaying a VF's framebuffer on the screen. +</p> +<h5><span id="VFs_in_QEMU_Hypervisor_.28VirtIO-GPU.29"></span><span class="mw-headline" id="VFs_in_QEMU_Hypervisor_(VirtIO-GPU)">VFs in QEMU Hypervisor (VirtIO-GPU)</span></h5> +<p>SR-IOV and Mdev VFs run in QEMU Hypervisor. +</p><p>QEMU has full access to all pages in VF's address space. +</p><p>VirtIO-GPU allows for allocating buffers (not API remoting in this case). +</p><p>Mesa's KMSRO allocates framebuffer via virtio-gpu. +</p><p>Mesa's KMSRO asks vendor driver to import framebuffer (no specific compositor dependancy). +</p> +<h5><span class="mw-headline" id="Transport">Transport</span></h5> +<p>A Scatter Gather List (SGL) of physical pages is constructed by VirtIO-GPU of VF. +</p> +<h6><span class="mw-headline" id="QEMU_Host-Side_u-dma-buf">QEMU Host-Side u-dma-buf</span></h6> +<p>Host QEMU uses u-dma-buf driver to reconstruct a virtual memory pointer from the SGL shared by VF. +</p><p>u-dma-buf driver allocates contiguous memory blocks in kernel as DMA buffers. +</p> +<h6><span class="mw-headline" id="QEMU_Host-Side_Modules">QEMU Host-Side Modules</span></h6> +<p>Once virtio-qemu has a DMA buffer, it shares it with the QEMU UI. +</p><p>QEMU UI has several toolkits to support like GTK, SDL, etc. with GTK. being the default. +</p><p>GTK uses EGL and passes it the DMABUF as a texture. +</p> +<h5><span class="mw-headline" id="Windows_VFs">Windows VFs</span></h5> +<p>Windows OS doesn't support DMABUF capability so we can't allocate buffers from VirtIO-GPU and share them with the Windows Kernel Mode Driver (KMD). +</p><p>Windows OS is different in the way that the FB is allocated via the OS rather than the miniport driver. +</p><p>Modified version of RedHat virtio-gpu-do (short for Display Only) driver used. +</p> +<h5><span class="mw-headline" id="Windows_Driver_Stack">Windows Driver Stack</span></h5> +<p>OS (DWM) allocates frame buffers and asks GPU to write to them through Miniport. +</p><p>DVServer UMD (IDD) asks the OS for the FB copy. +</p><p>DVServer UMD (IDD) passes the virtual memory address to DVServer KMD. +</p> +<h5><span class="mw-headline" id="DVServer_KMD">DVServer KMD</span></h5> +<p>DVServer KMD finds the SGL (Scatter Gather List) of physical pages for this virtual memory address. +</p><p>This SGL is passed via virt-queue from the VF to the host QEMU. +</p> +<h5><span class="mw-headline" id="Android_VFs">Android VFs</span></h5> +<p>Android uses Linux kernel underneath. VirtIO-GPU is present in Android's kernel. +</p><p>KMSRO patch to allocate framebuffer via VirtIO-GPU also ported over to Android. +</p><p>Need modifications in the minigbm lib of Android to connect with KMSRO part. +</p><p>Rest of stack looks identical to Linux VF/PF. +</p> +<h2><span class="mw-headline" id="i915">i915</span></h2> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_2">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions to documentation and open source by <b>Zhi Wang</b>, <b>Ben Widawsky</b>, and <b>Igor Bogdanov</b>. +</p><p>See references 2, 3, 4, 5, 6, 7, 8, and 9 in the <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="High_Level_Architecture_2">High Level Architecture</span></h3> +<h4><span class="mw-headline" id="i915_Clients">i915 Clients</span></h4> +<p>Processes which make use of the Intel i915 driver receive an i915 Client ID. +</p> +<h3><span class="mw-headline" id="Initialization_2">Initialization</span></h3> +<p>During initialization of the i915 driver the GuC binary blob is offloaded into the Graphics Translation Table (GTT). This allows the GuC to read GTT-loaded binary blob from shared framebuffer memory so that it may boot. +</p> +<h3><span class="mw-headline" id="Scheduling_2">Scheduling</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_0-_i915_vGPU_Scheduling.png.html" class="image"><img alt="Figure 0: i915 vGPU Scheduling" src="../images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/300px-Figure_0-_i915_vGPU_Scheduling.png" decoding="async" width="300" height="227" class="thumbimage" srcset="../images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/450px-Figure_0-_i915_vGPU_Scheduling.png 1.5x, ../images/thumb/c/c2/Figure_0-_i915_vGPU_Scheduling.png/600px-Figure_0-_i915_vGPU_Scheduling.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_0-_i915_vGPU_Scheduling.png.html" class="internal" title="Enlarge"></a></div><b>Figure 0:</b> i915 vGPU high-level Scheduling. See slides from: <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)">[9]</a></div></div></div> +<p>There are several abstractions for GPU virtual machine scheduling. Those are as follows: +</p> +<ul><li>Guest kernel (i915.ko)</li> +<li>Host kernel (i915.ko)</li> +<li>Device Firmware (GuC)</li></ul> +<h5><span class="mw-headline" id="In-VM_Scheduling_2">In-VM Scheduling</span></h5> +<h5><span id="Guest_kernel_.28i915.ko.29"></span><span class="mw-headline" id="Guest_kernel_(i915.ko)">Guest kernel (i915.ko)</span></h5> +<h6><span class="mw-headline" id="vExeclist">vExeclist</span></h6> +<p>The vExeclist is a method to submit commands directly to the GPU without the use of an intermediate microcontroller. +</p> +<h6><span class="mw-headline" id="vGuC">vGuC</span></h6> +<p>vGuC is a command submission interface used to process commands to the Intel <a rel="nofollow" class="external text" href="GPU_Firmware.html#GuC">Graphics Microcontroller (GuC)</a>. +</p> +<h4><span class="mw-headline" id="Between-VM_Scheduling_2">Between-VM Scheduling</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:I915_Scheduling_Events_and_Requests.png.html" class="image"><img alt="Figure 1: i915 vGPU Scheduling Requests & Events" src="../images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/300px-I915_Scheduling_Events_and_Requests.png" decoding="async" width="300" height="232" class="thumbimage" srcset="../images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/450px-I915_Scheduling_Events_and_Requests.png 1.5x, ../images/thumb/c/c3/I915_Scheduling_Events_and_Requests.png/600px-I915_Scheduling_Events_and_Requests.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:I915_Scheduling_Events_and_Requests.png.html" class="internal" title="Enlarge"></a></div><b>Figure 1:</b> i915 vGPU Scheduling Requests & Events. See slides from: <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)">[9]</a></div></div></div> +<h5><span id="Host_kernel_.28i915.ko.29"></span><span class="mw-headline" id="Host_kernel_(i915.ko)">Host kernel (i915.ko)</span></h5> +<p>Submitting commands to the GPU under i915 can take several paths. One pathway makes use of direct command submission without an intermediate micro-controller whereas the other uses an intermediate micro-controller. The intermediate micro-controller approach increases the amount of binary-blob code used and abstracts the kernel module from the device's internal scheduling model. +</p> +<h6><span class="mw-headline" id="Execlist">Execlist</span></h6> +<p>Execlist executes commands synchronously on the device without an intermediate microcontroller. This is the preferred method of executing commands by some driver developers because of it's stability and transparency under current i915 development. +</p> +<h6><span class="mw-headline" id="GuC">GuC</span></h6> +<p>GuC provides an execution pathway with an intermediate microcontroller providing a scheduling abstraction for Intel's preferred internal scheduling model. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_2-_Intel_vGPU_Scheduler.png.html" class="image"><img alt="Figure 2: Intel vGPU Scheduler request flow." src="../images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/300px-Figure_2-_Intel_vGPU_Scheduler.png" decoding="async" width="300" height="233" class="thumbimage" srcset="../images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/450px-Figure_2-_Intel_vGPU_Scheduler.png 1.5x, ../images/thumb/e/e0/Figure_2-_Intel_vGPU_Scheduler.png/600px-Figure_2-_Intel_vGPU_Scheduler.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_2-_Intel_vGPU_Scheduler.png.html" class="internal" title="Enlarge"></a></div><b>Figure 2:</b> i915 vGPU Scheduler request flow. See slides from: <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)">[9]</a></div></div></div> +<h5><span id="Device_Firmware_.28GuC.29"></span><span class="mw-headline" id="Device_Firmware_(GuC)">Device Firmware (GuC)</span></h5> +<h3><span class="mw-headline" id="Memory_Management_2">Memory Management</span></h3> +<h5><span class="mw-headline" id="Translation_Tables">Translation Tables</span></h5> +<h6><span id="GTT_.28Graphics_Translation_Table.29"></span><span class="mw-headline" id="GTT_(Graphics_Translation_Table)">GTT (Graphics Translation Table)</span></h6> +<p>GPU Memory on-device is a part of a GTT or Graphics Translation Table. This table stores information globally for all graphics processes within the system. Some processes access the Global Graphics Translation Table (GGTT) such as <a href="https://en.wikipedia.org/wiki/Direct_Rendering_Infrastructure" class="extiw" title="wikipedia:Direct Rendering Infrastructure">DRI</a> while other's receive a Per Process Graphics Translation Table (PPGTT) buffer based on their i915 Client ID. +</p> +<h6><span id="GGTT_.28Global_Graphics_Translation_Table.29"></span><span class="mw-headline" id="GGTT_(Global_Graphics_Translation_Table)">GGTT (Global Graphics Translation Table)</span></h6> +<h6><span id="PPGTT_.28Per_Process_Graphics_Translation_Table.29"></span><span class="mw-headline" id="PPGTT_(Per_Process_Graphics_Translation_Table)">PPGTT (Per Process Graphics Translation Table)</span></h6> +<p>Process-specific memory buffers are stored inside a Per Process Graphics Translation Table or PPGTT. This is a <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#VRAM_Isolation_(GPU_GMMU)">GPU MMU</a> translated subregion or IOVA of global GPU memory specific to a GPU process's client ID. +</p> +<h6><span class="mw-headline" id="Aliasing_PPGTT">Aliasing PPGTT</span></h6> +<p>Aliasing PPGTT (Per Process Graphics Translation Table) refers to partially separated GPU resources (process context). +</p> +<h6><span class="mw-headline" id="Real_PPGTT">Real PPGTT</span></h6> +<p>Real PPGTT (Per Process Graphics Translation Table) refers to fully separated GPU resources (process context). +</p> +<h3><span class="mw-headline" id="Display_Surface_Virtualization_3">Display Surface Virtualization</span></h3> +<p>The Intel vGPU makes use of two modes for Display Surface Virtualization. +</p> +<ul><li>VirtIO-GPU (Linux)</li> +<li>Indirect Display Driver (Windows)</li></ul> +<h4><span class="mw-headline" id="VirtIO-GPU">VirtIO-GPU</span></h4> +<h4><span id="IDD_.28Indirect_Display_Driver.29"></span><span class="mw-headline" id="IDD_(Indirect_Display_Driver)">IDD (Indirect Display Driver)</span></h4> +<p>The IDD (<a rel="nofollow" class="external text" href="https://learn.microsoft.com/en-us/windows-hardware/drivers/display/indirect-display-driver-model-overview">Indirect Display Driver</a>) provides virtual display functions with arbitrary resolutions to any rendering device virtual or physical. +</p><p>Intel's IDD can be found in their <a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS/">Display Virtualization for Windows OS</a> repository. +</p> +<h4><span class="mw-headline" id="Graphics_Buffer_Sharing_3">Graphics Buffer Sharing</span></h4> +<p>Intel's i915 driver provides functionality to directly map display memory from a <a rel="nofollow" class="external text" href="Merged_Drivers.html">guest vGPU Virtual Function (either SR-IOV or VFIO-Mdev) into the host GPU's Physical Function</a> without slow memory copies or graphics compression. For users running GPU virtualization on their local device this results in a significant performance uplift compared to traditional graphics sharing functionality built for remote access use-cases such as VDI. +</p><p>Intel's <a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS">0copy display virtualization tools</a> are simple to implement as sharing does not rely upon an added <a rel="nofollow" class="external text" href="https://www.qemu.org/docs/master/system/devices/ivshmem.html">IVSHMEM (Inter-VM Shared Memory device)</a> - rather the host directly maps the guest's display memory via <a rel="nofollow" class="external text" href="https://lwn.net/Articles/758903/">udmabuf</a> as the buffer sharing functions are provided within the i915 open source driver. +</p> +<h2><span class="mw-headline" id="OpenRM">OpenRM</span></h2> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png.html" class="image"><img alt="Figure 3: GPU BAR to Timeshared Syhededuling via Channel IO" src="../images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/300px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png" decoding="async" width="300" height="226" class="thumbimage" srcset="../images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/450px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png 1.5x, ../images/thumb/f/fd/Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png/600px-Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_3-_GPU_BAR_to_Timeshared_Syhededuling_via_Channel_IO.png.html" class="internal" title="Enlarge"></a></div><b>Figure 3:</b> GPU BAR to Timeshared Scheduling via Channel IO.</div></div></div> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_3">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions to documentation and open source by <b>Andy Currid</b>, <b>Neo Jia</b>, <b>John Fanelli</b>, and <b>Neha Joshi</b>. +</p> +<h3><span class="mw-headline" id="High_Level_Architecture_3">High Level Architecture</span></h3> +<p>The Open Resource Manager (RM driver) makes use of a highly object oriented paradigm comprised of multiple "engines" which act as micro-services for servicing driver requests. +</p><p>The Open Resource Manager driver (also known as <a rel="nofollow" class="external text" href="OpenRM.html">OpenRM</a>) refers to Nvidia's <a rel="nofollow" class="external text" href="https://github.com/NVIDIA/open-gpu-kernel-modules">open-kernel-modules</a>. +</p><p>Broadly speaking the OpenRM driver consists of two parts. +</p> +<ul><li>The Platform RM (OpenRM)</li> +<li>The Firmware RM (GSP RM / RM Core)</li></ul> +<p>The Platform RM is loaded into the Linux Kernel as nvidia.ko. This module communicates with the GSP RM for via <a href="https://en.wikipedia.org/wiki/Remote_procedure_call" class="extiw" title="wikipedia:Remote procedure call">Remote Procedure Calls (RPCs)</a> to communicate with engines from the RM Core. +</p> +<h5><span class="mw-headline" id="RM_Clients">RM Clients</span></h5> +<p>Processes (local, remote, or virtualized) which make use of the RM driver receive an RM Client ID. +</p> +<h4><span class="mw-headline" id="RM_Server">RM Server</span></h4> +<p>The RM Server (or Resource Server) tracks RM Clients as well as the hardware and software resources they control, allocate, and free. +</p> +<h4><span class="mw-headline" id="RM_API">RM API</span></h4> +<p>API to control the Resource Manager Server. +</p> +<h4><span class="mw-headline" id="RM_Core">RM Core</span></h4> +<p>Core functions of the RM driver controlling resource locking, mapping, unmapping, control calls, constructors, and deconstructors. Under OpenRM the RM Core runs within the GPU System Processor (GSP micro-controller) while in pre-open source versions of the Resource Manager the RM Core ran within the nvidia.ko kernel module +</p> +<h3><span class="mw-headline" id="Initialization_3">Initialization</span></h3> +<p>During bring up of the hardware several binary blobs are loaded from embedded <a href="https://en.wikipedia.org/wiki/Boot_ROM" class="extiw" title="wikipedia:Boot ROM">Boot ROM</a> memory to bootstrap embedded controller bring up from which point additional software is loaded from onboard <a href="https://en.wikipedia.org/wiki/Serial_Peripheral_Interface" class="extiw" title="wikipedia:Serial Peripheral Interface">SPI</a> flash memory. +</p><p>Software loaded from SPI flash is necessary for the full initialization of the Falcon/NvRISC processor as well as a cached version of the software necessary to run the GPU System Processor (GSP). +</p><p>Once the platform is posted it is ready to communicate with the host platform's RM driver. The OpenRM driver offloads a binary blob containing the RM Core to the <a rel="nofollow" class="external text" href="GPU_Firmware.html#GSP">GPU System Processor (GSP)</a> which is likely to contain a more recent version than the cached version contained in on-board SPI flash. +</p> +<h3><span class="mw-headline" id="Scheduling_3">Scheduling</span></h3> +<p>There are several abstractions for GPU virtual machine scheduling. Those are as follows: +</p> +<ul><li>Guest kernel (nvidia.ko)</li> +<li>Host kernel (nvidia.ko)</li> +<li>Host usermode (gpu-mgr / libnvidiavgpu.so)</li> +<li>Device Firmware (GSP)</li></ul> +<h4><span class="mw-headline" id="Command_Submission">Command Submission</span></h4> +<h5><span class="mw-headline" id="Runlist">Runlist</span></h5> +<h4><span class="mw-headline" id="In-VM_Scheduling_3">In-VM Scheduling</span></h4> +<p>Virtual machines contain their own GPU scheduling within the Nvidia kernel module in the guest OS. +</p> +<h5><span id="Guest_kernel_.28nvidia.ko.29"></span><span class="mw-headline" id="Guest_kernel_(nvidia.ko)">Guest kernel (nvidia.ko)</span></h5> +<p>Within a virtual machine running the Nvidia driver messages to the GPU are first sent to the guest nvidia.ko kernel module. +</p><p> +The guest then determines whether a vRPC (virtual Remote Procedure Call) or a pRPC (physical Remote Procedure Call) should be sent. Both pRPCs and vRPCs are sent through the host RM driver (Resource Manager).</p><blockquote><p><i>Note: Unclear on execution pathway for pRPCs vs vRPCs. pRPCs may go directly to device.</i></p></blockquote> +<h4><span class="mw-headline" id="Between-VM_Scheduling_3">Between-VM Scheduling</span></h4> +<p>In addition to scheduling which occurs within the virtual machine the Resource Manager driver also schedules messages to the GPU between GPU-accelerated virtual machines and host processes. +</p> +<h5><span id="Host_kernel_.28nvidia.ko.29"></span><span class="mw-headline" id="Host_kernel_(nvidia.ko)">Host kernel (nvidia.ko)</span></h5> +<p>Messages sent by the guest (via vRPC or pRPC) are received by the host Nvidia.ko driver. +</p><p>Nvidia.ko contains a virtual GPU state machine which contains status information for the virtual GPU. +</p><p>Nvidia.ko also contains a virtual GPU kernel scheduler which interacts with virtual GPU objects. +</p><p>Nvidia.ko also contains an RM Call scheduler which schedules calls on an RM class. +</p><p>The Nividia.ko kernel module exits to userspace to execute the nvidia-vgpu-mgr and VMIOP (Virtual Machine Input Output Plugin). +</p> +<h5><span id="Host_usermode_.28nvidia-vgpu-mgr_.2F_libnvidia-vgpu.so.29"></span><span class="mw-headline" id="Host_usermode_(nvidia-vgpu-mgr_/_libnvidia-vgpu.so)">Host usermode (nvidia-vgpu-mgr / libnvidia-vgpu.so)</span></h5> +<p>After exiting to userspace a daemon process (the nvidia-vgpu-mgr, and it's library libnvidia-vgpu.so) are executed to schedule VM-exits described below. +</p> +<h5><span class="mw-headline" id="nvidia-vgpu-mgr">nvidia-vgpu-mgr</span></h5> +<p>The nvidia-vgpu-mgr is a process which provides the spawning of virtual GPU stubs and population with capability information. +</p><p>This daemon process interacts with the libnvidia-vgpu.so, nvidia.ko, and nvidia-vgpu-vfio.ko components. +</p><p>This process and the libnvidia-vgpu.so contain, and execute the VMIOP. +</p><p>This process (and the VMIOP) schedules RPCs sent by the guest, receives VFIO BAR-exits, and relays requests to allocate, deallocate, pin, unpin, map, unmap to the <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_Core">RM Core</a>. +</p> +<h6><span class="mw-headline" id="vmiop">vmiop</span></h6> +<p>VMIOP (Virtual Machine Input Output Plugin) handles presenting virtualized functionality into the guest. +</p><p>The Virtual Machine Input Output Plugin software handles virtual displays, compute API offload, and most importantly <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#VFIO_Quirks_(region_traps)">BAR (Base Address Register) quirks</a>. +</p><p>The VMIOP is an <a href="https://en.wikipedia.org/wiki/Software_development_kit" class="extiw" title="wikipedia:Software development kit">SDK (Software Development Kit)</a> provided in binary format split between the libnvidiavgpu.so and nvidia-vgpu-mgr which provides userland helper functions for GPU virtualization. +</p><p>Messages to the VMIOP are scheduled by Linux kernel <a rel="nofollow" class="external text" href="https://www.learnlinux.org.za/courses/build/internals/ch07s02.html">niceness</a> (scheduling abstraction). +</p> +<h5><span id="Device_Firmware_.28GSP.29"></span><span class="mw-headline" id="Device_Firmware_(GSP)">Device Firmware (GSP)</span></h5> +<p>Messages received by the host RM driver (Resource Manager) are then scheduled by the RM Core contained within the GSP (GPU System Processor). The GSP handles the device's internal scheduling model. +</p> +<h3><span class="mw-headline" id="Memory_Management_3">Memory Management</span></h3> +<p>Managing virtual machine memory is very important to the security of virtualization. +</p><p>This section will cover the method by which secure memory "enclaves" or <a rel="nofollow" class="external text" href="https://terenceli.github.io/%E6%8A%80%E6%9C%AF/2019/08/04/iommu-introduction">IO Virtual Addresses (IOVAs)</a> may be provisioned and separation enforced by hardware constructs within the GPU. +</p> +<h5><span class="mw-headline" id="Programming_the_MMU">Programming the MMU</span></h5> +<p>In order to hardware enforce separation between memory allocated to Virtual Machines (VMs) virtualization software must program the GPU's MMU (GMMU controller) to create IO Virtual Addresses (IOVAs). +</p><p>In order to create such configurations several abstractions are used to translate high level representations of virtualization programmed via the vmiop and gpu-mgr into practical, architecture specific instructions. +</p> +<h6><span class="mw-headline" id="AMAPLibrary">AMAPLibrary</span></h6> +<p>The AMAPLibrary acts as a device abstraction framework for GPU driver software to program using high level representations of MMU configuration. +</p><p>The AMAPLibrary translates high level representations of GPU virtualization into graphics architecture-specific logic contained within architecture HALs (Hardware Abstraction Layers). +</p> +<h6><span class="mw-headline" id="Architecture_HALs">Architecture HALs</span></h6> +<p>GPU <a rel="nofollow" class="external text" href="https://archive.ll.mit.edu/HPEC/agendas/proc07/Day3/10_Hensley_Abstract.pdf">Hardware Abstraction Layers (HALs)</a> contain logic specific to graphics architectures, for instance the precise method by which the GPU driver may interact with the Falcon to provision MMU protected memory. +</p> +<h6><span id="DMA_from_Falcon_.2F_NvRISC-V_to_Frame_Buffer_Interface_.28FBIF.29"></span><span class="mw-headline" id="DMA_from_Falcon_/_NvRISC-V_to_Frame_Buffer_Interface_(FBIF)">DMA from Falcon / NvRISC-V to Frame Buffer Interface (FBIF)</span></h6> +<p>The Falcon (FAst Logic CONtroller) / NvRISC-V embedded controller emits DMAs to the Frame Buffer Interface (FBIF) in order to interact with the device's GMMU controller. +</p><p>User programs and VMs have their memory translated through the GMMU. +</p><p>Once created memory translations within a virtual machine's IO Virtual Address (IOVA) will be protected by the device's GMMU controller. +</p> +<h5><span class="mw-headline" id="Translation_Tables_2">Translation Tables</span></h5> +<h6><span class="mw-headline" id="vmiop_gva">vmiop_gva</span></h6> +<h3><span class="mw-headline" id="Display_Surface_Virtualization_4">Display Surface Virtualization</span></h3> +<h2><span class="mw-headline" id="amdgpu">amdgpu</span></h2> +<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://01.org/linuxgraphics/documentation/hardware-specification-prms">Intel Graphics Programmer's Reference Manuals (PRM)</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2013/1/i915-hardware-contexts-and-some-bits-about-batchbuffers/">i915: Hardware Contexts (and some bits about batchbuffers)</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/6/the-global-gtt-part-1/">i915: The Global GTT Part 1</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/6/aliasing-ppgtt-part-2/">i915: Aliasing PPGTT Part 2</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/7/true-ppgtt-part-3/">i915: True PPGTT Part 3</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/7/future-ppgtt-part-4-dynamic-page-table-allocations-64-bit-address-space-gpu-mirroring-and-yeah-something-about-relocs-too/">i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)</a></li> +<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">i915: Security of the Intel Graphics Stack - Part 1 - Introduction</a></li> +<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/24/graphics-part2.html">i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf">i915: An Introduction to Intel GVT-g (with new architecture)</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/Articles/758903/">lwn.net: Add udmabuf misc device</a></li> +<li><a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf">Nvidia RISC-v Story</a></li> +<li><a rel="nofollow" class="external text" href="https://terenceli.github.io/%E6%8A%80%E6%9C%AF/2019/08/04/iommu-introduction">IOMMU Introduction</a></li> +<li><a rel="nofollow" class="external text" href="https://archive.ll.mit.edu/HPEC/agendas/proc07/Day3/10_Hensley_Abstract.pdf">Hardware and Compute Abstraction Layers For Accelerated Computing Using Graphics Hardware and Conventional CPUs</a></li> +<li><a rel="nofollow" class="external text" href="https://envytools.readthedocs.io/en/latest/hw/intro.html">nVidia GPU Introduction (envytools)</a></li> +<li><a rel="nofollow" class="external text" href="https://on-demand.gputechconf.com/gtc/2014/presentations/S4725-hi-perf-graphics-nvidia-grid-virtual-gpus.pdf">Delivering High Performance Remote Graphics With Nvidia GRID Virtual GPU</a></li> +<li><a rel="nofollow" class="external text" href="https://nehajoshi.dev/post/nvidia_mig_feature/">NVIDIA Multi-Instance GPU</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol05-memory_views.pdf">i915: Kaby Lake Intel Graphics Programmer's Reference Manual [Volume 5: Memory Views]</a></li> +<li><a rel="nofollow" class="external text" href="https://developer.nvidia.com/content/life-triangle-nvidias-logical-pipeline">Lifecycle of a Triangle - Nvidia's logical pipeline</a></li> +<li><a rel="nofollow" class="external text" href="https://docs.nvidia.com/cuda/parallel-thread-execution/">Nvidia Parallel Thread Execution (PTX)</a></li> +<li><a rel="nofollow" class="external text" href="https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html">i915/GEM Crashcourse</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/Articles/292583/">drm: Add GEM ("graphics execution manager") to i915 driver.</a></li></ol> +<!-- +NewPP limit report +Cached time: 20260911155604 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.057 seconds +Real time usage: 0.061 seconds +Preprocessor visited node count: 264/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 94/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:4505-0!canonical and timestamp 20260911155604 and revision id 23791. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/GPU_Firmware.html b/wiki/open-iov.org/index.php/GPU_Firmware.html new file mode 100644 index 0000000..d4e0282 --- /dev/null +++ b/wiki/open-iov.org/index.php/GPU_Firmware.html @@ -0,0 +1,453 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>GPU Firmware - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"5a727119f3b74662049f50a2","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"GPU_Firmware","wgTitle":"GPU Firmware","wgCurRevisionId":23779,"wgRevisionId":23779,"wgArticleId":94,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"GPU_Firmware","wgRelevantArticleId":94,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr", +"pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","mediawiki.toc","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="../load.php%3Flang=en&modules=ext.visualEditor.desktopArticleTarget.noscript|skins.vector.styles.legacy&only=styles&skin=vector.css"/> +<script async="" src="../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-GPU_Firmware rootpage-GPU_Firmware skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >GPU Firmware</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="GPU_Firmware.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="GPU_Firmware.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="GPU_Firmware.html#Intel"><span class="tocnumber">1</span> <span class="toctext">Intel</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="GPU_Firmware.html#Firmware_Images"><span class="tocnumber">1.1</span> <span class="toctext">Firmware Images</span></a> +<ul> +<li class="toclevel-3 tocsection-3"><a href="GPU_Firmware.html#Intel_Firmware_Support_Package_(FSP)"><span class="tocnumber">1.1.1</span> <span class="toctext">Intel Firmware Support Package (FSP)</span></a> +<ul> +<li class="toclevel-4 tocsection-4"><a href="GPU_Firmware.html#FSP_Configuration"><span class="tocnumber">1.1.1.1</span> <span class="toctext">FSP Configuration</span></a> +<ul> +<li class="toclevel-5 tocsection-5"><a href="GPU_Firmware.html#Editing_FSP_Configuration"><span class="tocnumber">1.1.1.1.1</span> <span class="toctext">Editing FSP Configuration</span></a></li> +</ul> +</li> +<li class="toclevel-4 tocsection-6"><a href="GPU_Firmware.html#FSP_Binary_Format"><span class="tocnumber">1.1.1.2</span> <span class="toctext">FSP Binary Format</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-7"><a href="GPU_Firmware.html#Known_Firmware_Package_Variations"><span class="tocnumber">1.1.2</span> <span class="toctext">Known Firmware Package Variations</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-8"><a href="GPU_Firmware.html#Embedded_Controllers"><span class="tocnumber">1.2</span> <span class="toctext">Embedded Controllers</span></a> +<ul> +<li class="toclevel-3 tocsection-9"><a href="GPU_Firmware.html#GuC"><span class="tocnumber">1.2.1</span> <span class="toctext">GuC</span></a> +<ul> +<li class="toclevel-4 tocsection-10"><a href="GPU_Firmware.html#Hardware_Architecture"><span class="tocnumber">1.2.1.1</span> <span class="toctext">Hardware Architecture</span></a></li> +<li class="toclevel-4 tocsection-11"><a href="GPU_Firmware.html#Software_Architecture"><span class="tocnumber">1.2.1.2</span> <span class="toctext">Software Architecture</span></a> +<ul> +<li class="toclevel-5 tocsection-12"><a href="GPU_Firmware.html#GuC_Blob_Checksum_&_Code_Signing"><span class="tocnumber">1.2.1.2.1</span> <span class="toctext">GuC Blob Checksum & Code Signing</span></a></li> +</ul> +</li> +</ul> +</li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-1 tocsection-13"><a href="GPU_Firmware.html#Nvidia"><span class="tocnumber">2</span> <span class="toctext">Nvidia</span></a> +<ul> +<li class="toclevel-2 tocsection-14"><a href="GPU_Firmware.html#Firmware_Images_2"><span class="tocnumber">2.1</span> <span class="toctext">Firmware Images</span></a></li> +<li class="toclevel-2 tocsection-15"><a href="GPU_Firmware.html#Embedded_Controllers_2"><span class="tocnumber">2.2</span> <span class="toctext">Embedded Controllers</span></a> +<ul> +<li class="toclevel-3 tocsection-16"><a href="GPU_Firmware.html#Falcon_/_NV-RISCV"><span class="tocnumber">2.2.1</span> <span class="toctext">Falcon / NV-RISCV</span></a></li> +<li class="toclevel-3 tocsection-17"><a href="GPU_Firmware.html#GSP"><span class="tocnumber">2.2.2</span> <span class="toctext">GSP</span></a> +<ul> +<li class="toclevel-4 tocsection-18"><a href="GPU_Firmware.html#GSP_Initialization_&_Offload"><span class="tocnumber">2.2.2.1</span> <span class="toctext">GSP Initialization & Offload</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-19"><a href="GPU_Firmware.html#CMU"><span class="tocnumber">2.2.3</span> <span class="toctext">CMU</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-1 tocsection-20"><a href="GPU_Firmware.html#AMD"><span class="tocnumber">3</span> <span class="toctext">AMD</span></a></li> +<li class="toclevel-1 tocsection-21"><a href="GPU_Firmware.html#References_(Talks_&_Reading_Material)"><span class="tocnumber">4</span> <span class="toctext">References (Talks & Reading Material)</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="Intel">Intel</span></h2> +<h3><span class="mw-headline" id="Firmware_Images">Firmware Images</span></h3><p> +This section will cover firmware images used in Intel GPUs.</p><div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html" class="image"><img alt="Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification." src="../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/300px-Screen_Shot_2022-11-18_at_4.14.32_PM.png" decoding="async" width="300" height="261" class="thumbimage" srcset="../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/450px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 1.5x, ../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/600px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html" class="internal" title="Enlarge"></a></div>Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. <a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/736809">Source</a></div></div></div> +<h4><span id="Intel_Firmware_Support_Package_.28FSP.29"></span><span class="mw-headline" id="Intel_Firmware_Support_Package_(FSP)">Intel Firmware Support Package (FSP)</span></h4> +<p>Much like CPUs Intel's GPUs also contain a Firmware Support Package (FSP). +</p><p>The Coreboot project provides public domain information on the FSP <a rel="nofollow" class="external text" href="https://doc.coreboot.org/soc/intel/fsp/index.html">here</a>. +</p> +<h5><span class="mw-headline" id="FSP_Configuration">FSP Configuration</span></h5> +<p>In the context of GPUs the FSP configures several functions of the device. +</p><p>Those functions are as follows: +</p> +<table class="wikitable"> +<caption>GPU Firmware Support Package +</caption> +<tbody><tr> +<th>FSP Parameter +</th> +<th>Possible Values +</th></tr> +<tr> +<td>GFSP Status +</td> +<td>0x00 +</td></tr> +<tr> +<td>FIVR SSC Value +</td> +<td>*.*% +</td></tr> +<tr> +<td>FIVR RFI Value +</td> +<td>*.*MHz +</td></tr> +<tr> +<td>GT Subsystem Vendor ID +</td> +<td>0x8086 +</td></tr> +<tr> +<td>GT Subsystem Device ID +</td> +<td>0x** +</td></tr> +<tr> +<td>HDA Subsystem Vendor ID +</td> +<td>0x0000 +</td></tr> +<tr> +<td>HDA Subsystem Device ID +</td> +<td>0x0000 +</td></tr> +<tr> +<td>P2SB Enable +</td> +<td>Yes/No +</td></tr> +<tr> +<td>LMEBAR +</td> +<td>Max +</td></tr> +<tr> +<td>GTMMADDR Prefetch Capability +</td> +<td>Prefetch Enabled +</td></tr> +<tr> +<td><a rel="nofollow" class="external text" href="Merged_Drivers.html">Display Present</a> +</td> +<td>Enabled/Disabled +</td></tr> +<tr> +<td>I2C For Third Party Devices +</td> +<td>Enabled/Disabled +</td></tr> +<tr> +<td>I2C Device Address 1 +</td> +<td>0x0000 +</td></tr> +<tr> +<td>I2C Device Address 2 +</td> +<td>0x0000 +</td></tr> +<tr> +<td>I2C Bus Speed +</td> +<td>Standard mode (0 to 100Kbps) +</td></tr></tbody></table> +<h6><span class="mw-headline" id="Editing_FSP_Configuration">Editing FSP Configuration</span></h6> +<p>The FSP configuration editor can be downloaded <a rel="nofollow" class="external text" href="https://github.com/tianocore/edk2/tree/master/IntelFsp2Pkg/Tools/ConfigEditor">here</a> and it's user manual is available <a rel="nofollow" class="external text" href="https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManuals/ConfigEditorUserManual.md">here</a>. +</p> +<h5><span class="mw-headline" id="FSP_Binary_Format">FSP Binary Format</span></h5> +<p>The FSP's binary layout is detailed within the <a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/736809">Intel® FSP External Architecture Specification v2.4</a> on page 14. +</p> +<h4><span class="mw-headline" id="Known_Firmware_Package_Variations">Known Firmware Package Variations</span></h4> +<p>Some firmware packages may include an **End of Manufacturing Flash Protection Mode** status of Protected or Unprotected. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html" class="image"><img alt="Figure 2: Firmware status information for an Intel DG2 device." src="../images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/300px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png" decoding="async" width="300" height="613" class="thumbimage" srcset="../images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/450px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 1.5x, ../images/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html" class="internal" title="Enlarge"></a></div>Figure 2: Firmware status information for an Intel DG2 device.</div></div></div> +<p>Similar <a rel="nofollow" class="external text" href="https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/">SPI Write Protection</a> functionality is made available through Intel CPUs under <a href="https://en.wikipedia.org/wiki/System_Management_Mode" class="extiw" title="wikipedia:System Management Mode">System Management Mode (SMM)</a>. +</p> +<h3><span class="mw-headline" id="Embedded_Controllers">Embedded Controllers</span></h3> +<p>This section will cover firmware images as they apply to various embedded controllers within the Intel GPU. +</p> +<h4><span class="mw-headline" id="GuC">GuC</span></h4> +<p>The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs. +</p> +<h5><span class="mw-headline" id="Hardware_Architecture">Hardware Architecture</span></h5> +<p><i>The following section is supported by <a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">igor-blue.github.io</a> (see reference <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&_Reading_Material)">1</a>, <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&_Reading_Material)">2</a>):</i> +</p><p><i>"The GuC - an embedded <a rel="nofollow" class="external text" href="https://www.wikiwand.com/en/I486">i486</a> core that supports graphics scheduling, power management and firmware attestation."</i> +</p> +<h5><span class="mw-headline" id="Software_Architecture">Software Architecture</span></h5> +<p><i>The following section is supported by <a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">igor-blue.github.io</a> (see reference <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&_Reading_Material)">1</a>, <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&_Reading_Material)">2</a>):</i> +</p><p><i>"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."</i> +</p><p><i>"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."</i> +</p> +<h6><span id="GuC_Blob_Checksum_.26_Code_Signing"></span><span class="mw-headline" id="GuC_Blob_Checksum_&_Code_Signing">GuC Blob Checksum & Code Signing</span></h6> +<p><i>"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."</i> +</p> +<h2><span class="mw-headline" id="Nvidia">Nvidia</span></h2> +<h3><span class="mw-headline" id="Firmware_Images_2">Firmware Images</span></h3> +<p>This section will cover firmware images used in Nvidia GPUs. +</p> +<h3><span class="mw-headline" id="Embedded_Controllers_2">Embedded Controllers</span></h3> +<p>This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU. +</p> +<h4><span id="Falcon_.2F_NV-RISCV"></span><span class="mw-headline" id="Falcon_/_NV-RISCV">Falcon / NV-RISCV</span></h4> +<p>The Fast Logic CONtroller (Falcon) and Nvidia RISC-V (<a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf">NV-RISCV</a>) processors run the NvOS. +</p> +<h4><span class="mw-headline" id="GSP">GSP</span></h4> +<p>The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core. +</p><p>The GSP runs <a rel="nofollow" class="external text" href="https://lwn.net/Articles/637658/">Library Operating System (LibOS)</a>. +</p> +<h5><span id="GSP_Initialization_.26_Offload"></span><span class="mw-headline" id="GSP_Initialization_&_Offload">GSP Initialization & Offload</span></h5> +<p>The <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#Initialization_3">GSP is initialized multiple times</a> during the system's bring up and runtime. +</p><p>GSP offload may occur during: +</p> +<ul><li>Hardware bring up when a cached version of the RM Core is loaded from SPI flash</li></ul> +<ul><li>During host driver bring up when the RM Core is offloaded by the <a rel="nofollow" class="external text" href="OpenRM.html">OpenRM driver</a>.</li> +<li>During guest driver bring up when the RM Core is offloaded.</li></ul> +<table class="wikitable"> +<caption>Possible GSP Offloads +</caption> +<tbody><tr> +<th>Load Source +</th> +<th>Payload +</th> +<th>Notes +</th></tr> +<tr> +<td><a rel="nofollow" class="external text" href="https://wiki.segger.com/SPI_Flash">SPI Flash</a> +</td> +<td>Cached RM Core +</td> +<td>Used as a fallback in case of no rm offload. +</td></tr> +<tr> +<td>OpenRM +</td> +<td>RM Core +</td> +<td>This is the RM Core which was traditionally contained in the proprietary RM driver. +</td></tr> +<tr> +<td>VGX Guest +</td> +<td>Guest RM Core +</td> +<td>Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via <a rel="nofollow" class="external text" href="https://github.com/NVIDIA/open-gpu-kernel-modules/blob/758b4ee8189c5198504cb1c3c5bc29027a9118a3/src/common/sdk/nvidia/inc/ctrl/ctrla081.h#L102">gspHeapSize</a>?). +</td></tr></tbody></table> +<h4><span class="mw-headline" id="CMU">CMU</span></h4> +<h2><span class="mw-headline" id="AMD">AMD</span></h2> +<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">Security of the Intel Graphics Stack - Part 1 - Introduction</a></li> +<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/24/graphics-part2.html">Security of the Intel Graphics Stack - Part 2 - FW <-> GuC</a></li> +<li><a rel="nofollow" class="external text" href="https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/">Firmware Security Realizations Part 3: SPI Write Protections</a></li> +<li><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/fsp-firmware-solutions-iot-video.html">Intel® FSP: Firmware Solutions for the Internet of Things</a></li></ol> +<!-- +NewPP limit report +Cached time: 20260911202653 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.026 seconds +Real time usage: 0.029 seconds +Preprocessor visited node count: 66/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:94-0!canonical and timestamp 20260911202653 and revision id 23779. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html b/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html new file mode 100644 index 0000000..ae9ec87 --- /dev/null +++ b/wiki/open-iov.org/index.php/GPU_Software_Bill_Of_Materials_(SBOM).html @@ -0,0 +1,528 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>GPU Software Bill Of Materials (SBOM) - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"af0587608ec3ae8a843f8186","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"GPU_Software_Bill_Of_Materials_(SBOM)","wgTitle":"GPU Software Bill Of Materials (SBOM)","wgCurRevisionId":23786,"wgRevisionId":23786,"wgArticleId":4506,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"GPU_Software_Bill_Of_Materials_(SBOM)","wgRelevantArticleId":4506,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[], +"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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This driver is commonly replaced with a vendor built VFIO interface with differing memory management and/or page pinning mechanisms which are specific to the vGPU software internals. +</td></tr> +<tr> +<td>Mediated Core (mdev.ko) +</td> +<td>Driver +</td> +<td>6.2-rc1 +</td> +<td>OSS +</td> +<td>0.044 MB +</td> +<td><a rel="nofollow" class="external text" href="https://docs.kernel.org/driver-api/vfio-mediated-device.html">kernel.org</a> +</td> +<td>2016.xx.xx +</td> +<td><a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Instruction_Execution">irqfd</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Instruction_Execution">ioeventfd</a>, <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_DMA_Translations">Type 1 IOMMU</a> +</td> +<td>The Mediated Core driver provides a common interface for mediated device management that can be used by drivers of different devices. It is an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment (based on VFIO). +</td></tr> +<tr> +<td rowspan="2"> +</td> +<td>guest communication daemon +</td> +<td rowspan="2">Daemon +</td> +<td>0.1.0 +</td> +<td><a rel="nofollow" class="external text" href="https://">OSS</a> +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href=""></a> +</td> +<td>2023.02.08 +</td> +<td><a rel="nofollow" class="external text" href="https://fedoraproject.org/wiki/Features/VirtioSerial">Virtio-Serial</a>, CLI +</td> +<td>Handles IO to and from guests and the host using Virtio-Serial to handle multiple different guest modules. +</td></tr> +<tr> +<td>mdev management CLI +</td> +<td>1.0 +</td> +<td><a rel="nofollow" class="external text" href="https://">OSS</a> +</td> +<td>0.084 MB +</td> +<td><a rel="nofollow" class="external text" href=""></a> +</td> +<td>2023.01.06 +</td> +<td>CLI, <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_API">RMAPI</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_Core">Mediated Core</a> +</td> +<td>Configures the the <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#nvidia-vgpu-mgr">nvidia-vgpu-mgr</a> process. +</td></tr> +<tr> +<td rowspan="4">Intel +</td> +<td>i915 SR-IOV +</td> +<td>Driver +</td> +<td rowspan="3"><a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/tree/5.15/ADL-linux-ER">5.15</a> +</td> +<td>OSS +</td> +<td>in-kernel +</td> +<td> +</td> +<td> +</td> +<td> +</td> +<td>Intel's open source GPU driver for <a rel="nofollow" class="external text" href="GPU_Firmware.html#GuC">GuC</a>-equipped graphics accelerators. +</td></tr> +<tr> +<td><a rel="nofollow" class="external text" href="GPU_Firmware.html#GuC">GuC</a> μOS +</td> +<td rowspan="2">Firmware +</td> +<td rowspan="2">Blob +</td> +<td> +</td> +<td> +</td> +<td> +</td> +<td>IOMMU Interrupts, Power Management Interrupts, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#GTT_(Graphics_Translation_Table)">GTT</a> +</td> +<td>Handles scheduling, and power management. +</td></tr> +<tr> +<td>HuC +</td> +<td> +</td> +<td> +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#GTT_(Graphics_Translation_Table)">GTT</a> +</td> +<td>Handles video encoding/decoding. +</td></tr> +<tr> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#Display_Surface_Virtualization_2">Display Virtualization for Windows OS</a> +</td> +<td>Driver +</td> +<td><a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS/releases/">791</a> +</td> +<td><a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS">OSS</a> +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="https://github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt">github.com/intel/Display-Virtualization-for-Windows-OS/blob/main/Readme.txt</a> +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="https://github.com/ikwzm/udmabuf">udmabuf</a>, <a rel="nofollow" class="external text" href="https://learn.microsoft.com/en-us/windows-hardware/drivers/wdf/overview-of-the-umdf">UMDF</a>, <a rel="nofollow" class="external text" href="https://learn.microsoft.com/en-us/windows-hardware/drivers/kernel/">KMDF</a> +</td> +<td>Intel's 'Display Virtualization for Windows OS' provides a virtual pixel surface used for hardware graphics rendering using Microsoft's open source 'Indirect Display Driver (IDD)'. Display virtualization for Windows OS makes use of display memory sharing primitives provided in-driver by the i915 host. +</td></tr> +<tr> +<td rowspan="7">Nvidia +</td> +<td><a href="OpenRM.html" title="OpenRM">OpenRM</a> +</td> +<td>Driver +</td> +<td rowspan="2">525.85.12 +</td> +<td>OSS +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="https://github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md">github.com/NVIDIA/open-gpu-kernel-modules/blob/main/README.md</a> +</td> +<td>2023.01.31 +</td> +<td> +</td> +<td>Nvidia's open source GPU driver for <a rel="nofollow" class="external text" href="GPU_Firmware.html#GSP">GSP</a>-equipped graphics accelerators. +</td></tr> +<tr> +<td><a rel="nofollow" class="external text" href="GPU_Firmware.html#GSP">GSP</a> RM (uproc) +</td> +<td rowspan="2">Firmware +</td> +<td rowspan="2">Blob +</td> +<td> +</td> +<td> +</td> +<td>2023.01.31 +</td> +<td>RPC +</td> +<td>Embedded firmware based on <a rel="nofollow" class="external text" href="https://lwn.net/Articles/637658/">LibOS</a> containing the <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_Core">RM Core</a>. +</td></tr> +<tr> +<td>Falcon/NvRISC (uproc) +</td> +<td> +</td> +<td> +</td> +<td> +</td> +<td> +</td> +<td>FBIF (Frame Buffer Interface) / GMMU +</td> +<td>Embedded firmware which handles many aspects of the device including configuring the GPU's GMMU controller. +</td></tr> +<tr> +<td>nvidia-vgpud +</td> +<td rowspan="2">Daemon +</td> +<td rowspan="4"><a rel="nofollow" class="external text" href="https://docs.nvidia.com/grid/15.0/whats-new-vgpu/index.html">v15.2</a> +</td> +<td rowspan="4">Blob +</td> +<td>0.108 MB +</td> +<td rowspan="4"><a rel="nofollow" class="external text" href="https://docs.nvidia.com/grid/index.html">docs.nvidia.com/grid</a> +</td> +<td>2023.01.xx +</td> +<td>CLI, <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_API">RMAPI</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_Core">Mediated Core</a> +</td> +<td>Configures the the <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#nvidia-vgpu-mgr">nvidia-vgpu-mgr</a> process. +</td></tr> +<tr> +<td>nvidia-vgpu-mgr +</td> +<td>0.132 MB +</td> +<td>2023.01.xx +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#vmiop">vmiop</a>, <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_API">RMAPI</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#Guest_kernel_(nvidia.ko)">vRPC</a>, pRPC, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_Core">Mediated Core</a> +</td> +<td>Handles IO to and from guest RM, host RM, and hardware. +</td></tr> +<tr> +<td>libnvidia-vgpu.so +</td> +<td>Library +</td> +<td>3.1 MB +</td> +<td>2023.01.xx +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#vmiop">vmiop</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#RM_API">RMAPI</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_Core">Mediated Core</a> +</td> +<td>Handles IO to and from guest RM, host RM, and hardware. Contains circular dependancies with <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#nvidia-vgpu-mgr">nvidia-vgpu-mgr</a>. +</td></tr> +<tr> +<td>nvidia-vgpu-vfio.ko +</td> +<td>Driver +</td> +<td>0.108 MB +</td> +<td>2023.01.xx +</td> +<td><a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_DMA_Translations">Type 1 IOMMU</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Instruction_Execution">irqfd, ioeventfd</a>, <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mediated_Core">Mediated Core</a> +</td> +<td>Handles incremental memory mapping (non-page pinning per the standard vfio-pci driver). +</td></tr></tbody></table> +<h2><span class="mw-headline" id="More_Information">More Information</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf">Nvidia RISC-V Story</a></li> +<li><a rel="nofollow" class="external text" href=""></a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/linuxgraphics/documentation/hardware-specification-prms">Intel Graphics Programmer's Reference Manuals (PRM)</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2013/1/i915-hardware-contexts-and-some-bits-about-batchbuffers/">i915: Hardware Contexts (and some bits about batchbuffers)</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/6/the-global-gtt-part-1/">i915: The Global GTT Part 1</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/6/aliasing-ppgtt-part-2/">i915: Aliasing PPGTT Part 2</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/7/true-ppgtt-part-3/">i915: True PPGTT Part 3</a></li> +<li><a rel="nofollow" class="external text" href="https://bwidawsk.net/blog/2014/7/future-ppgtt-part-4-dynamic-page-table-allocations-64-bit-address-space-gpu-mirroring-and-yeah-something-about-relocs-too/">i915: Future PPGTT Part 4 (Dynamic page table allocations, 64 bit address space, GPU "mirroring", and yeah, something about relocs too)</a></li> +<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">i915: Security of the Intel Graphics Stack - Part 1 - Introduction</a></li> +<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/24/graphics-part2.html">i915: Security of the Intel Graphics Stack - Part 2 - FW <-> GuC</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf">i915: An Introduction to Intel GVT-g (with new architecture)</a></li></ol> +<!-- +NewPP limit report +Cached time: 20260911202653 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.016 seconds +Real time usage: 0.017 seconds +Preprocessor visited node count: 4/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:4506-0!canonical and timestamp 20260911202653 and revision id 23786. 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+</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-GPU_Support rootpage-GPU_Support skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >GPU Support</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="GPU_Support.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="GPU_Support.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="GPU_Support.html#Abstract"><span class="tocnumber">1</span> <span class="toctext">Abstract</span></a></li> +<li class="toclevel-1 tocsection-2"><a href="GPU_Support.html#Overview"><span class="tocnumber">2</span> <span class="toctext">Overview</span></a></li> +<li class="toclevel-1 tocsection-3"><a href="GPU_Support.html#Intel"><span class="tocnumber">3</span> <span class="toctext">Intel</span></a> +<ul> +<li class="toclevel-2 tocsection-4"><a href="GPU_Support.html#Hardware"><span class="tocnumber">3.1</span> <span class="toctext">Hardware</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="GPU_Support.html#Drivers"><span class="tocnumber">3.2</span> <span class="toctext">Drivers</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-6"><a href="GPU_Support.html#Nvidia"><span class="tocnumber">4</span> <span class="toctext">Nvidia</span></a> +<ul> +<li class="toclevel-2 tocsection-7"><a href="GPU_Support.html#Hardware_2"><span class="tocnumber">4.1</span> <span class="toctext">Hardware</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="GPU_Support.html#Drivers_2"><span class="tocnumber">4.2</span> <span class="toctext">Drivers</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-9"><a href="GPU_Support.html#AMD"><span class="tocnumber">5</span> <span class="toctext">AMD</span></a> +<ul> +<li class="toclevel-2 tocsection-10"><a href="GPU_Support.html#Hardware_3"><span class="tocnumber">5.1</span> <span class="toctext">Hardware</span></a></li> +<li class="toclevel-2 tocsection-11"><a href="GPU_Support.html#Drivers_3"><span class="tocnumber">5.2</span> <span class="toctext">Drivers</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Abstract">Abstract</span></h2><p> +The following document will detail GPU Support for SR-IOV, SIOV, and VFIO-Mdev functionality.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<h2><span class="mw-headline" id="Overview">Overview</span></h2> +<table class="wikitable"> +<caption>Feature Matrix +</caption> +<tbody><tr> +<th colspan="3">Hardware +</th> +<th colspan="4">Drivers +</th> +<th colspan="3"><a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals">Virtual I/O Assistance Modes</a> +</th> +<th colspan="2">Userspace +</th></tr> +<tr> +<th>Vendor +</th> +<th>Architecture +</th> +<th>Model +</th> +<th><a rel="nofollow" class="external text" href="https://www.fsf.org/about/what-is-free-software">Libre</a> Drivers +</th> +<th>Blob Drivers +</th> +<th><a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Merged_Drivers">'Merged' Host+Guest Acceleration</a> +</th> +<th>Manufacturer Support +</th> +<th><a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals#Mdev_Mode">Mdev Support</a> +</th> +<th><a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals#SR-IOV_Mode">SR-IOV Support</a> +</th> +<th><a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals#SIOV_Mode">SIOV Support</a> +</th> +<th><a rel="nofollow" class="external text" href="">mdev management CLI Support</a> +</th> +<th><a rel="nofollow" class="external text" href=""> Support</a> +</th></tr> +<tr> +<td>Intel +</td> +<td>6th Generation (Skylake) +</td> +<td>*HD +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes (<a rel="nofollow" class="external text" href="https://community.intel.com/t5/Graphics/Graphics-Driver-Support-Update-for-10th-Generation-and-Older/m-p/1403969/thread-id/108899">Legacy</a>) +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>Intel +</td> +<td>7th Generation (Kaby Lake) +</td> +<td>*HD +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes (<a rel="nofollow" class="external text" href="https://community.intel.com/t5/Graphics/Graphics-Driver-Support-Update-for-10th-Generation-and-Older/m-p/1403969/thread-id/108899">Legacy</a>) +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>Intel +</td> +<td>8th Generation (Coffee Lake) +</td> +<td>*HD +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes (<a rel="nofollow" class="external text" href="https://community.intel.com/t5/Graphics/Graphics-Driver-Support-Update-for-10th-Generation-and-Older/m-p/1403969/thread-id/108899">Legacy</a>) +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>Intel +</td> +<td>9th Generation (Cannon Lake) +</td> +<td>*HD +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes (<a rel="nofollow" class="external text" href="https://community.intel.com/t5/Graphics/Graphics-Driver-Support-Update-for-10th-Generation-and-Older/m-p/1403969/thread-id/108899">Legacy</a>) +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>Intel +</td> +<td>10th Generation (Ice Lake) +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>No +</td> +<td>Yes (<a rel="nofollow" class="external text" href="https://community.intel.com/t5/Graphics/Graphics-Driver-Support-Update-for-10th-Generation-and-Older/m-p/1403969/thread-id/108899">Legacy</a>) +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td></tr> +<tr> +<td>Intel +</td> +<td>11th Generation (Tiger Lake) +</td> +<td>Xe* +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="https://archive.ph/0McAE#selection-4883.0-4943.35">Yes</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Intel +</td> +<td>12th Generation (Alder Lake) +</td> +<td>Xe* +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#i915">i915</a> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes +</td> +<td> +</td> +<td><a rel="nofollow" class="external text" href="https://archive.ph/0McAE#selection-4883.0-4943.35">Yes</a> +</td> +<td>In Development +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Maxell +</td> +<td>*(see exceptions below) +</td> +<td><a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/">Nouveau</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td>RM +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Pascal +</td> +<td>* +</td> +<td><a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/">Nouveau</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td>RM +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Turing +</td> +<td>* +</td> +<td><a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/">Nouveau</a>, <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td>RM +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Ampere +</td> +<td>A* +</td> +<td><a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/">Nouveau</a> (<a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/FeatureMatrix.html">Development</a>), <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td>RM +</td> +<td>No (<a rel="nofollow" class="external text" href="https://developer.nvidia.com/displaymodeselector">DisplayModeSelector</a>) +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>In Development +</td> +<td>Yes +</td> +<td>Yes +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Ampere +</td> +<td>RTX 30** +</td> +<td><a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/">Nouveau</a> (<a rel="nofollow" class="external text" href="https://nouveau.freedesktop.org/FeatureMatrix.html">Development</a>), <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td>RM +</td> +<td>In Development +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>No +</td> +<td>In Development +</td> +<td>In Development +</td> +<td>In Development +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Ada Lovelace +</td> +<td>* +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>In Development +</td> +<td>In Development +</td> +<td>In Development +</td></tr> +<tr> +<td>Nvidia +</td> +<td>Hopper +</td> +<td>* +</td> +<td><a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#OpenRM">OpenRM</a> +</td> +<td> +</td> +<td> +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>In Development +</td> +<td> +</td> +<td> +</td></tr> +<tr> +<td>AMD +</td> +<td>Tonga +</td> +<td>W7100 +</td> +<td>AMDGPU, <a rel="nofollow" class="external text" href="https://github.com/GPUOpen-LibrariesAndSDKs/MxGPU-Virtualization">MxGPU / GIM / GPU-IOV Module (Deprecated)</a> +</td> +<td>AMDGPU-Pro +</td> +<td>No +</td> +<td><a href="https://en.wikipedia.org/wiki/End-of-life_product" class="extiw" title="wikipedia:End-of-life product">EOL</a> (2017) +</td> +<td>No +</td> +<td>Yes +<p>(<a rel="nofollow" class="external text" href="https://forum.level1techs.com/t/how-to-sr-iov-mod-the-w7100-gpu/164186">patched</a>) +</p> +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>AMD +</td> +<td>Tonga +</td> +<td>S71** +</td> +<td>AMDGPU, <a rel="nofollow" class="external text" href="https://github.com/GPUOpen-LibrariesAndSDKs/MxGPU-Virtualization">MxGPU / GIM / GPU-IOV Module (Deprecated)</a> +</td> +<td>AMDGPU-Pro +</td> +<td>No +</td> +<td><a href="https://en.wikipedia.org/wiki/End-of-life_product" class="extiw" title="wikipedia:End-of-life product">EOL</a> (2017) +</td> +<td>No +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>Yes +</td></tr> +<tr> +<td>AMD +</td> +<td>Vega +</td> +<td>* +</td> +<td>AMDGPU +</td> +<td>AMDGPU-Pro +</td> +<td>No +</td> +<td><a rel="nofollow" class="external text" href="GPU_Support.html#Drivers_3">Partial</a> +</td> +<td>Unknown +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td></tr> +<tr> +<td>AMD +</td> +<td>Navi +</td> +<td>* +</td> +<td>AMDGPU +</td> +<td>AMDGPU-Pro +</td> +<td>No +</td> +<td><a rel="nofollow" class="external text" href="GPU_Support.html#Drivers_3">Partial</a> +</td> +<td>Unknown +</td> +<td>Yes +</td> +<td>No +</td> +<td>No +</td> +<td>No +</td></tr></tbody></table> +<h2><span class="mw-headline" id="Intel">Intel</span></h2> +<p>This section will cover Mdev support on Intel GPUs. +</p> +<h4><span class="mw-headline" id="Hardware">Hardware</span></h4> +<p>GPUs supporting GVT-g (software based mediation)<a rel="nofollow" class="external autonumber" href="https://www.intel.com/content/www/us/en/support/articles/000058558/graphics.html">[1]</a>: +</p> +<ul><li>Intel HD Graphics 5500</li> +<li>Intel HD Graphics 6000</li> +<li>Intel HD Graphics 510</li> +<li>Intel HD Graphics 520</li> +<li>Intel HD Graphics 530</li> +<li>Intel HD Graphics 620</li> +<li>Intel HD Graphics 630</li> +<li>Intel UHD Graphics 620</li> +<li>Intel UHD Graphics 630</li></ul> +<p>GPUs supporting SR-IOV (hardware based mediation): +</p> +<ul><li>Intel Iris Xe Graphics <a rel="nofollow" class="external autonumber" href="https://archive.ph/0McAE#selection-4883.0-4943.35">[2]</a><a rel="nofollow" class="external autonumber" href="https://old.reddit.com/r/VFIO/comments/o7l2zr/sriov_on_intel_xe_graphics/">[3]</a></li> +<li>Intel Iris Xe MAX Graphics</li></ul> +<h4><span class="mw-headline" id="Drivers">Drivers</span></h4> +<p>Drivers with GVT-g support (6th - 9th gen): +</p> +<ul><li><b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/i915">i915 mainline</a></b></li></ul> +<p>Drivers with SR-IOV support (11th gen+): +</p> +<ul><li><b><a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/commit/41ef979f0894326c202473807a56b599a2f3d04e">i915 upstreaming</a></b></li></ul> +<h2><span class="mw-headline" id="Nvidia">Nvidia</span></h2> +<p>This section will cover Mdev support on Nvidia GPUs. +</p> +<h4><span class="mw-headline" id="Hardware_2">Hardware</span></h4> +<ul><li>All(?) Volta based GPUs (V-series)</li> +<li>All(?) Turing based GPUs (20-series)</li> +<li>All(?) Pascal based GPUs (10-series)</li> +<li>Most Maxwell based GPUs (9-series) with the following notable exceptions: +<ul><li>GTX 970 (mixed FB regions)</li> +<li>Quadro M2000 (mixed FB regions)</li> +<li>Tesla M40 <a rel="nofollow" class="external autonumber" href="https://github.com/DualCoder/vgpu_unlock/issues/62">[4]</a></li></ul></li></ul> +<ul><li>NVIDIA A100 HGX 80GB</li> +<li>NVIDIA A100 PCIe 80GB (SR-IOV: 20VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/PB-10577-001_v02.pdf">[5]</a>)</li> +<li>NVIDIA A100X</li> +<li>NVIDIA A100 HGX 40GB</li> +<li>NVIDIA A100 PCIe 40GB (SR-IOV: 16VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/A100-PCIE-Prduct-Brief.pdf">[6]</a>)</li> +<li>NVIDIA A40 (SR-IOV: 32VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a40/NVIDIA%20A40%20Product%20Brief.pdf">[7]</a>)</li> +<li>NVIDIA A30 (SR-IOV: 8VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-product-brief.pdf">[8]</a>)</li> +<li>NVIDIA A30X</li> +<li>NVIDIA A16 (SR-IOV: 16VF <a rel="nofollow" class="external autonumber" href="https://images.nvidia.com/content/Solutions/data-center/vgpu-a16-product-brief.pdf">[9]</a>)</li> +<li>NVIDIA A10 (SR-IOV: 32VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a10/pdf/A10-Product-Brief.pdf">[10]</a>)</li> +<li>NVIDIA A2 (SR-IOV: 16VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/solutions/data-center/a2/pdf/a2-product-brief.pdf">[11]</a>)</li> +<li>NVIDIA RTX A6000</li> +<li>NVIDIA RTX A5000</li> +<li>Quadro RTX 8000 (SR-IOV: 24 VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/NVIDIA-Quadro-RTX-8000-PCIe-Server-Card-PB-FINAL-1219.pdf">[12]</a>)</li> +<li>Quadro RTX 8000 passive</li> +<li>Quadro RTX 6000 (SR-IOV: 24 VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/NVIDIA-Quadro-RTX-6000-PCIe-Server-Card-PB-FINAL-1219.pdf">[13]</a>)</li> +<li>Quadro RTX 6000 passive</li> +<li>Tesla V100</li> +<li>Tesla T4 (SR-IOV: 16VF <a rel="nofollow" class="external autonumber" href="https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-t4/t4-tensor-core-product-brief.pdf">[14]</a>)</li> +<li>Tesla P100</li> +<li>Tesla P40</li> +<li>Tesla P6</li> +<li>Tesla P4</li> +<li>Tesla M60</li> +<li>Tesla M10</li> +<li>Tesla M6</li> +<li>GRID K2 (Citrix XenServer and VMware ESXi only)</li> +<li>GRID K1 (Citrix XenServer and VMware ESXi only)</li></ul> +<h4><span class="mw-headline" id="Drivers_2">Drivers</span></h4> +<p>The most widely used method of enabling Mdev functionality on Nvidia GPUs is via the use of Nvidia's proprietary driver package. +</p><p>Nvidia's proprietary Mdev driver supports both SR-IOV as well as software based mediation. The appropriate mode is chosen between the two methods based on hardware architecture. +</p> +<h2><span class="mw-headline" id="AMD">AMD</span></h2> +<p>This section will cover Mdev support on AMD GPUs. +</p> +<h4><span class="mw-headline" id="Hardware_3">Hardware</span></h4> +<p>Supported GPUs: +</p> +<ul><li>AMD FirePro S7150</li> +<li>AMD Radeon Pro V520 <a rel="nofollow" class="external autonumber" href="https://www.amd.com/en/graphics/workstation-virtual-graphics">[15]</a></li> +<li>AMD FirePro W7100 <a rel="nofollow" class="external text" href="https://forum.level1techs.com/t/how-to-sr-iov-mod-the-w7100-gpu/164186">[15]</a></li></ul> +<h4><span class="mw-headline" id="Drivers_3">Drivers</span></h4> +<p>The open source <a rel="nofollow" class="external text" href="https://github.com/GPUOpen-LibrariesAndSDKs/MxGPU-Virtualization">GIM driver</a> supports AMD Tonga architecture GPUs such as the FirePro S7150 & W7100. +</p><p>To make use of the MxGPU GIM driver on modern kernel versions you will require <a rel="nofollow" class="external text" href="https://github.com/GPUOpen-LibrariesAndSDKs/MxGPU-Virtualization/pull/24">pull request 24</a>. +</p><p>Virtualization driver support beyond AMD's Tonga architecture is unclear. +</p> +<!-- +NewPP limit report +Cached time: 20260911155139 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.038 seconds +Real time usage: 0.040 seconds +Preprocessor visited node count: 39/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 4/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:21-0!canonical and timestamp 20260911155139 and revision id 23752. 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+ <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Glossary.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Glossary.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Glossary.html#Definitions"><span class="tocnumber">1</span> <span class="toctext">Definitions</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Glossary.html#VFIO"><span class="tocnumber">1.1</span> <span class="toctext">VFIO</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="Glossary.html#Mdev"><span class="tocnumber">1.2</span> <span class="toctext">Mdev</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="Glossary.html#Virtual_CPU_(vCPU)"><span class="tocnumber">1.3</span> <span class="toctext">Virtual CPU (vCPU)</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Glossary.html#Virtual_GPU_(vGPU)"><span class="tocnumber">1.4</span> <span class="toctext">Virtual GPU (vGPU)</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Glossary.html#IVSHMEM"><span class="tocnumber">1.5</span> <span class="toctext">IVSHMEM</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Glossary.html#KVMFR_(Looking_Glass)"><span class="tocnumber">1.6</span> <span class="toctext">KVMFR (Looking Glass)</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="Glossary.html#NUMA_Node"><span class="tocnumber">1.7</span> <span class="toctext">NUMA Node</span></a></li> +<li class="toclevel-2 tocsection-9"><a href="Glossary.html#Application_Binary_Interface_(ABI)"><span class="tocnumber">1.8</span> <span class="toctext">Application Binary Interface (ABI)</span></a></li> +<li class="toclevel-2 tocsection-10"><a href="Glossary.html#SR-IOV"><span class="tocnumber">1.9</span> <span class="toctext">SR-IOV</span></a></li> +<li class="toclevel-2 tocsection-11"><a href="Glossary.html#GVT-g"><span class="tocnumber">1.10</span> <span class="toctext">GVT-g</span></a></li> +<li class="toclevel-2 tocsection-12"><a href="Glossary.html#VirGL"><span class="tocnumber">1.11</span> <span class="toctext">VirGL</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Definitions">Definitions</span></h2> +<p>This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +</p><p>If you have suggestions on how to improve the glossary you can <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Main_Page#Getting_Started_Contributing_to_Open-IOV"><b>contribute</b></a> or join our <a rel="nofollow" class="external text" href="https://discord.gg/Rb9K9DYxKK"><b>community discussion thread</b></a> to make suggestions. +</p> +<h3><span class="mw-headline" id="VFIO">VFIO</span></h3> +<blockquote><p>Kernel.org defines VFIO or Virtual Function Input Output as <b>"an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/Documentation/vfio.txt">[1]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:VFIO_Diagram.png.html" class="image"><img alt="" src="../images/thumb/4/43/VFIO_Diagram.png/300px-VFIO_Diagram.png" decoding="async" width="300" height="397" class="thumbimage" srcset="../images/4/43/VFIO_Diagram.png 1.5x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:VFIO_Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting direct VFIO passthrough of a GPU adapter.</div></div></div> +<h3><span class="mw-headline" id="Mdev">Mdev</span></h3> +<blockquote><p>Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: <b>"an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294">[2]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:VFIO-Mdev_Diagram.png.html" class="image"><img alt="" src="../images/thumb/c/c7/VFIO-Mdev_Diagram.png/300px-VFIO-Mdev_Diagram.png" decoding="async" width="300" height="397" class="thumbimage" srcset="../images/thumb/c/c7/VFIO-Mdev_Diagram.png/450px-VFIO-Mdev_Diagram.png 1.5x, ../images/c/c7/VFIO-Mdev_Diagram.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:VFIO-Mdev_Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting VFIO Mediated Device interacting with two vGPU guests.</div></div></div> +<h3><span id="Virtual_CPU_.28vCPU.29"></span><span class="mw-headline" id="Virtual_CPU_(vCPU)">Virtual CPU (vCPU)</span></h3> +<blockquote><p>A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.</p></blockquote> +<h3><span id="Virtual_GPU_.28vGPU.29"></span><span class="mw-headline" id="Virtual_GPU_(vGPU)">Virtual GPU (vGPU)</span></h3> +<blockquote><p>A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2023-0/intel-iris-xe-gpu-architecture.html">EUs</a>, or <a rel="nofollow" class="external text" href="https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf">SMs</a>) and/or a partition of the device's Video Random Access Memory (VRAM).</p></blockquote> +<h3><span class="mw-headline" id="IVSHMEM">IVSHMEM</span></h3> +<blockquote><p>According to QEMU's GitHub repo: <b>"The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR."</b> <b><a rel="nofollow" class="external text" href="https://github.com/qemu/qemu/blob/master/docs/specs/ivshmem-spec.txt">[3]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:IVSHMEM.png.html" class="image"><img alt="" src="../images/thumb/d/d3/IVSHMEM.png/300px-IVSHMEM.png" decoding="async" width="300" height="203" class="thumbimage" srcset="../images/thumb/d/d3/IVSHMEM.png/450px-IVSHMEM.png 1.5x, ../images/thumb/d/d3/IVSHMEM.png/600px-IVSHMEM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:IVSHMEM.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.</div></div></div> +<h3><span id="KVMFR_.28Looking_Glass.29"></span><span class="mw-headline" id="KVMFR_(Looking_Glass)">KVMFR (Looking Glass)</span></h3> +<blockquote><p>looking-glass.io defines Looking Glass as: <b>"an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse."</b> <b><a rel="nofollow" class="external text" href="https://looking-glass.io/">[4]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:KVMFR_Looking_Glass.png.html" class="image"><img alt="" src="../images/thumb/8/8a/KVMFR_Looking_Glass.png/300px-KVMFR_Looking_Glass.png" decoding="async" width="300" height="179" class="thumbimage" srcset="../images/thumb/8/8a/KVMFR_Looking_Glass.png/450px-KVMFR_Looking_Glass.png 1.5x, ../images/thumb/8/8a/KVMFR_Looking_Glass.png/600px-KVMFR_Looking_Glass.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:KVMFR_Looking_Glass.png.html" class="internal" title="Enlarge"></a></div>A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.</div></div></div> +<h3><span class="mw-headline" id="NUMA_Node">NUMA Node</span></h3> +<blockquote><p>Infogalactic defines NUMA as: <b>"<i>Non-uniform memory access (NUMA) is a</i> computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Non-uniform_memory_access">[5]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:NUMA_Node.png.html" class="image"><img alt="" src="../images/thumb/7/73/NUMA_Node.png/300px-NUMA_Node.png" decoding="async" width="300" height="151" class="thumbimage" srcset="../images/thumb/7/73/NUMA_Node.png/450px-NUMA_Node.png 1.5x, ../images/thumb/7/73/NUMA_Node.png/600px-NUMA_Node.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:NUMA_Node.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting Non-Uniform Memory Access (NUMA) nodes.</div></div></div> +<h3><span id="Application_Binary_Interface_.28ABI.29"></span><span class="mw-headline" id="Application_Binary_Interface_(ABI)">Application Binary Interface (ABI)</span></h3> +<blockquote><p>Infogalactic defines an ABI as <b>"the interface between two program modules, one of which is often a library or operating system, at the level of machine code."</b> <b><a rel="nofollow" class="external text" href="https://infogalactic.com/info/Application_binary_interface">[6]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Application_Binary_Interface_(ABI).png.html" class="image"><img alt="" src="../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/300px-Application_Binary_Interface_(ABI).png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/450px-Application_Binary_Interface_(ABI).png 1.5x, ../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/600px-Application_Binary_Interface_(ABI).png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Application_Binary_Interface_(ABI).png.html" class="internal" title="Enlarge"></a></div>A diagram contrasting API and ABI as well as their respective roles in software compatibility.</div></div></div> +<h3><span class="mw-headline" id="SR-IOV">SR-IOV</span></h3> +<blockquote><p>docs.microsoft.com defines SR-IOV as <b>"The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." <a rel="nofollow" class="external text" href="https://archive.is/FcDoK">[7]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:SR-IOV.png.html" class="image"><img alt="" src="../images/thumb/6/65/SR-IOV.png/300px-SR-IOV.png" decoding="async" width="300" height="238" class="thumbimage" srcset="../images/thumb/6/65/SR-IOV.png/450px-SR-IOV.png 1.5x, ../images/thumb/6/65/SR-IOV.png/600px-SR-IOV.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:SR-IOV.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.</div></div></div> +<h3><span class="mw-headline" id="GVT-g">GVT-g</span></h3> +<blockquote><p>wiki.archlinux.org defines Intel GVT-g as <b>"a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." <a rel="nofollow" class="external text" href="https://wiki.archlinux.org/title/Intel_GVT-g">[8]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:SR-IOV-Diagram.png.html" class="image"><img alt="" src="../images/thumb/d/df/SR-IOV-Diagram.png/300px-SR-IOV-Diagram.png" decoding="async" width="300" height="258" class="thumbimage" srcset="../images/thumb/d/df/SR-IOV-Diagram.png/450px-SR-IOV-Diagram.png 1.5x, ../images/thumb/d/df/SR-IOV-Diagram.png/600px-SR-IOV-Diagram.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:SR-IOV-Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram of Intel's GVT-g (Graphics Virtualization Technology g).</div></div></div> +<h3><span class="mw-headline" id="VirGL">VirGL</span></h3> +<blockquote><div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Virgl.png.html" class="image"><img alt="" src="../images/thumb/b/b4/Virgl.png/300px-Virgl.png" decoding="async" width="300" height="398" class="thumbimage" srcset="../images/b/b4/Virgl.png 1.5x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Virgl.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting GPU instruction redirects to a single host graphics driver.</div></div></div><p>lwn.net defines Virgl as: <b>"a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host."</b> <b><a rel="nofollow" class="external text" href="https://lwn.net/Articles/767970/">[9]</a></b></p></blockquote> +<!-- +NewPP limit report +Cached time: 20260911202651 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.022 seconds +Real time usage: 0.024 seconds +Preprocessor visited node count: 87/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 27/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:13-0!canonical and timestamp 20260911202651 and revision id 23763. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Hypervisor_Support.html b/wiki/open-iov.org/index.php/Hypervisor_Support.html new file mode 100644 index 0000000..0ae37b4 --- /dev/null +++ b/wiki/open-iov.org/index.php/Hypervisor_Support.html @@ -0,0 +1,332 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Hypervisor Support - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"76a186b5bc7d8d06a8f88662","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Hypervisor_Support","wgTitle":"Hypervisor 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+</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Hypervisor_Support rootpage-Hypervisor_Support skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Hypervisor Support</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Hypervisor_Support.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Hypervisor_Support.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th>Platform Hypervisor +</th> +<th>Virtual GPU support +</th> +<th>Memory Sharing APIs +</th> +<th>IOMMU Groups support +</th> +<th>PCI forwarding +</th> +<th>Mdev Support +</th> +<th>SR-IOV Support +</th> +<th>SIOV Support +</th></tr> +<tr> +<td>KVM +</td> +<td>Yes +</td> +<td>IVSHMEM +</td> +<td>Yes +</td> +<td>Yes (via VFIO) +</td> +<td>Yes +</td> +<td>Yes +</td> +<td>In Development +</td></tr> +<tr> +<td>Xen +</td> +<td>Yes +</td> +<td>Grant Tables +</td> +<td>No +</td> +<td>Yes (via <a rel="nofollow" class="external text" href="https://wiki.xenproject.org/wiki/Xen_PCI_Passthrough">xen-pciback</a>) +</td> +<td>No +</td> +<td>Yes +</td> +<td>Unknown +</td></tr> +<tr> +<td>NVMM +</td> +<td>Unknown +</td> +<td>Unknown +</td> +<td>No +</td> +<td>Unknown +</td> +<td>No +</td> +<td>Unknown +</td> +<td>No +</td></tr></tbody></table> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Hypervisor_Support.html#KVM"><span class="tocnumber">1</span> <span class="toctext">KVM</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Hypervisor_Support.html#Missing_Functionality"><span class="tocnumber">1.1</span> <span class="toctext">Missing Functionality</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-3"><a href="Hypervisor_Support.html#Xen"><span class="tocnumber">2</span> <span class="toctext">Xen</span></a> +<ul> +<li class="toclevel-2 tocsection-4"><a href="Hypervisor_Support.html#Mdev_drivers_outside_Dom0"><span class="tocnumber">2.1</span> <span class="toctext">Mdev drivers outside Dom0</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Hypervisor_Support.html#Missing_Functionality_2"><span class="tocnumber">2.2</span> <span class="toctext">Missing Functionality</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Hypervisor_Support.html#Additional_Documentation"><span class="tocnumber">2.3</span> <span class="toctext">Additional Documentation</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-7"><a href="Hypervisor_Support.html#NVMM"><span class="tocnumber">3</span> <span class="toctext">NVMM</span></a> +<ul> +<li class="toclevel-2 tocsection-8"><a href="Hypervisor_Support.html#Missing_Functionality_3"><span class="tocnumber">3.1</span> <span class="toctext">Missing Functionality</span></a></li> +<li class="toclevel-2 tocsection-9"><a href="Hypervisor_Support.html#Additional_Documentation_2"><span class="tocnumber">3.2</span> <span class="toctext">Additional Documentation</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="KVM">KVM</span></h2> +<p>This section will cover existing support in KVM for VFIO-Mdev and ongoing issues with it's existing implementation. +</p> +<h3><span class="mw-headline" id="Missing_Functionality">Missing Functionality</span></h3> +<p>Nested SR-IOV. +</p> +<h2><span class="mw-headline" id="Xen">Xen</span></h2> +<p>This section will cover efforts to support the Xen hypervisor with open device mediation software. +</p><p>XAPI docs for virtual GPUs can be read <a rel="nofollow" class="external text" href="https://xapi-project.github.io/xen-api/classes/vgpu_type.html">here</a>. +</p> +<h3><span class="mw-headline" id="Mdev_drivers_outside_Dom0">Mdev drivers outside Dom0</span></h3> +<p><a rel="nofollow" class="external text" href="https://xenbits.xen.org/docs/unstable/designs/launch/hyperlaunch.html">Xen Hyperlaunch</a> aims to disaggregate Dom0's monolithic functions. This includes a discrete domain for device drivers. +</p> +<h3><span class="mw-headline" id="Missing_Functionality_2">Missing Functionality</span></h3> +<p>IOMMU Groups (discussions around extending or reworking Xen's IOMMU to include IOMMU Groups is ongoing). +</p> +<h3><span class="mw-headline" id="Additional_Documentation">Additional Documentation</span></h3> +<p>For additional documentation check the <a rel="nofollow" class="external text" href="https://wiki.xenproject.org/wiki/Main_Page">XenProject Wiki</a>. +</p> +<h2><span class="mw-headline" id="NVMM">NVMM</span></h2> +<p>This section will cover NetBSD's NVMM. +</p> +<h3><span class="mw-headline" id="Missing_Functionality_3">Missing Functionality</span></h3> +<p>VFIO. +</p> +<h3><span class="mw-headline" id="Additional_Documentation_2">Additional Documentation</span></h3> +<p>For additional documentation read <a rel="nofollow" class="external text" href="https://blog.netbsd.org/tnf/entry/from_zero_to_nvmm">From Zero to NVMM</a>. +</p> +<!-- +NewPP limit report +Cached time: 20260911202653 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.010 seconds +Real time usage: 0.011 seconds +Preprocessor visited node count: 27/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:23-0!canonical and timestamp 20260911202653 and revision id 751. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Intel.html b/wiki/open-iov.org/index.php/Intel.html new file mode 100644 index 0000000..e083ac2 --- /dev/null +++ b/wiki/open-iov.org/index.php/Intel.html @@ -0,0 +1,214 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Intel - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"f5c2c201f0da4bb4fbafffdb","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Intel","wgTitle":"Intel","wgCurRevisionId":23757,"wgRevisionId":23757,"wgArticleId":73,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"Intel","wgRelevantArticleId":73,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"}, +"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="../load.php%3Flang=en&modules=ext.visualEditor.desktopArticleTarget.noscript|skins.vector.styles.legacy&only=styles&skin=vector.css"/> +<script async="" src="../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Intel rootpage-Intel skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Intel</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Intel.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Intel.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>This page will document points of integration for virtualization in the Intel i915 driver. +</p><p>The i915 added <b>SR-IOV feature enablement</b> in <a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/commit/41ef979f0894326c202473807a56b599a2f3d04e">this commit (April 26th 2022)</a>. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Intel_SR-IOV_APIs.html b/wiki/open-iov.org/index.php/Intel_SR-IOV_APIs.html new file mode 100644 index 0000000..12bc697 --- /dev/null +++ b/wiki/open-iov.org/index.php/Intel_SR-IOV_APIs.html @@ -0,0 +1,215 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Intel - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"d80f3527211207bc615106f6","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Intel","wgTitle":"Intel","wgCurRevisionId":23757,"wgRevisionId":23757,"wgArticleId":73,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"Intel","wgRelevantArticleId":73,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRedirectedFrom":"Intel_SR-IOV_APIs","wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr", +"pageVariantFallbacks":"en"},"wgInternalRedirectTargetUrl":"/index.php/Intel","wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["mediawiki.action.view.redirect","site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="../load.php%3Flang=en&modules=ext.visualEditor.desktopArticleTarget.noscript|skins.vector.styles.legacy&only=styles&skin=vector.css"/> +<script async="" src="../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +<link rel="canonical" href="Intel.html"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Intel rootpage-Intel skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Intel</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"><span class="mw-redirectedfrom">(Redirected from <a href="../index.php%3Ftitle=Intel_SR-IOV_APIs&redirect=no.html" class="mw-redirect" title="Intel SR-IOV APIs">Intel SR-IOV APIs</a>)</span></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Intel_SR-IOV_APIs.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Intel_SR-IOV_APIs.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>This page will document points of integration for virtualization in the Intel i915 driver. +</p><p>The i915 added <b>SR-IOV feature enablement</b> in <a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/commit/41ef979f0894326c202473807a56b599a2f3d04e">this commit (April 26th 2022)</a>. Work is ongoing to upstream this code to <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/i915">i915 in the mainline Linux kernel</a>. +</p><p>Driver API documentation can be read here: <a rel="nofollow" class="external free" href="https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html">https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html</a> +</p> +<!-- +NewPP limit report +Cached time: 20260911202652 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.001 seconds +Real time usage: 0.002 seconds +Preprocessor visited node count: 1/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 1/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:73-0!canonical and timestamp 20260911202652 and revision id 23757. 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It will aim to give you a sense of primitives or foundational concepts used for GPU Virtualization. +</p> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Introduction.html#Terminology"><span class="tocnumber">1</span> <span class="toctext">Terminology</span></a></li> +<li class="toclevel-1 tocsection-2"><a href="Introduction.html#Primitives"><span class="tocnumber">2</span> <span class="toctext">Primitives</span></a> +<ul> +<li class="toclevel-2 tocsection-3"><a href="Introduction.html#PCI_BAR"><span class="tocnumber">2.1</span> <span class="toctext">PCI BAR</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="Introduction.html#GPU_Drivers"><span class="tocnumber">2.2</span> <span class="toctext">GPU Drivers</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Introduction.html#IOMMU"><span class="tocnumber">2.3</span> <span class="toctext">IOMMU</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Introduction.html#Virtualization_vs._Paravirtualization"><span class="tocnumber">2.4</span> <span class="toctext">Virtualization vs. Paravirtualization</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Introduction.html#Unassisted_vs._Assisted"><span class="tocnumber">2.5</span> <span class="toctext">Unassisted vs. Assisted</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-8"><a href="Introduction.html#Further_Reading"><span class="tocnumber">3</span> <span class="toctext">Further Reading</span></a> +<ul> +<li class="toclevel-2 tocsection-9"><a href="Introduction.html#Virtualization_Fundamentals"><span class="tocnumber">3.1</span> <span class="toctext">Virtualization Fundamentals</span></a></li> +<li class="toclevel-2 tocsection-10"><a href="Introduction.html#Virtual_I/O_Internals"><span class="tocnumber">3.2</span> <span class="toctext">Virtual I/O Internals</span></a></li> +<li class="toclevel-2 tocsection-11"><a href="Introduction.html#GPU_Driver_Internals"><span class="tocnumber">3.3</span> <span class="toctext">GPU Driver Internals</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Terminology">Terminology</span></h2> +<p>To get started with basic terminology around IO Virtualization read the <a href="Glossary.html" title="Glossary">Glossary</a> page. This will get you familiar with a few terms and concepts used in IO Virtualization documentation. +</p> +<h2><span class="mw-headline" id="Primitives">Primitives</span></h2> +<p>The primitives section will cover a few notes on the basics of virtualizing a GPU or IO device. +</p> +<h3><span class="mw-headline" id="PCI_BAR">PCI BAR</span></h3> +<p>PCI-e devices such as GPUs are used for input and output to and from a computer system. This input and output occurs using <a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1">TLPs or Transaction Layer Packets</a> over the PCI-e packet network. The IO device is presented to the host operating system as <a rel="nofollow" class="external text" href="https://wiki.osdev.org/PCI#Base_Address_Registers">BARs or Base Address Registers</a>. +</p> +<h3><span class="mw-headline" id="GPU_Drivers">GPU Drivers</span></h3> +<p>GPUs need software to communicate from a host computer system to the device - this software is called a GPU Driver and it typically interacts with the device using <a href="https://en.wikipedia.org/wiki/Memory-mapped_I/O" class="extiw" title="wikipedia:Memory-mapped I/O">MMIO or Memory Mapped IO</a>. MMIO is a set of operations used to allow normal CPU instructions to address registers in RAM in order to communicate with the PCI-e device. In the context of virtualization these registers must be presented into the device in a way that the guest operating system expects. Typically this is accomplished using <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#All_Modes">VFIO or Virtual Function IO</a>. VFIO is used for many methods of virtualizing the device including discrete assignment of a physical device, or virtual (partitioned) device assignment created with or without hardware assistance. +</p> +<h3><span class="mw-headline" id="IOMMU">IOMMU</span></h3> +<p><a href="https://en.wikipedia.org/wiki/Memory_management_unit" class="extiw" title="wikipedia:Memory management unit">MMU or Memory Management Units</a> handle hardware enforced access to <a href="https://en.wikipedia.org/wiki/Memory_paging" class="extiw" title="wikipedia:Memory paging">memory paging</a> in computer systems. In the context of virtualized MMIO (Memory Mapped Input Output) devices an MMU is required to hardware enforce access to virtual devices (a <a href="https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit" class="extiw" title="wikipedia:Input–output memory management unit">Memory Management Unit for Input Output is known as an IOMMU</a>). In the case of VFIO, groups of IOMMU devices (<a rel="nofollow" class="external text" href="https://vfio.blogspot.com/2014/08/iommu-groups-inside-and-out.html">IOMMU Groups</a>) are used to control access to the device. These IOMMU Groups often represent individual devices or sub-devices (in the context of <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Mdev_Mode">Unassisted Virtualization (VFIO-Mdev)</a>, <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#SR-IOV_Mode">Hardware-Assisted Virtualization (SR-IOV)</a>, or <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#SIOV_Mode">Hardware-Assisted Paravirtualization</a>) which may be bound to a VFIO bus driver (such as <a rel="nofollow" class="external text" href="https://docs.kernel.org/driver-api/vfio.html#vfio-bus-driver-api">vfio-pci</a>) which results in a <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#Binding_VFIO_devices">VFIO Group</a> (unit of ownership). +</p> +<h3><span class="mw-headline" id="Virtualization_vs._Paravirtualization">Virtualization vs. Paravirtualization</span></h3> +<p><a href="https://en.wikipedia.org/wiki/Virtualization" class="extiw" title="wikipedia:Virtualization">Virtualization</a> provides support for unmodified guest software or drivers in the context of GPUs. +</p><p><a href="https://en.wikipedia.org/wiki/Paravirtualization" class="extiw" title="wikipedia:Paravirtualization">Paravirtualization</a> provides support for "enlightened" guests or modified software which is aware of virtualization. +</p> +<h3><span class="mw-headline" id="Unassisted_vs._Assisted">Unassisted vs. Assisted</span></h3> +<p>Similar to virtualization on CPUs with tools like Xen, IO devices can be virtualized on different kinds of computer hardware. Some devices provide hardware virtualization assistance (such as <a rel="nofollow" class="external text" href="https://wiki.xenproject.org/wiki/Xen_Project_Software_Overview#HVM_and_its_variants_.28x86.29">HVM mode in Xen</a>) and some do not (such as <a rel="nofollow" class="external text" href="https://wiki.xenproject.org/wiki/Xen_Project_Software_Overview#PV_.28x86.29">PV mode in Xen</a>), as a result an <a href="Virtual_I/O_Internals.html" title="Virtual I/O Internals">appropriate mode should be used</a> depending on the availability of assistance. +</p> +<h2><span class="mw-headline" id="Further_Reading">Further Reading</span></h2> +<p>This section will cover what you should read to obtain more information about virtualization. +</p> +<h3><span class="mw-headline" id="Virtualization_Fundamentals">Virtualization Fundamentals</span></h3> +<p>The <a href="Virtualization_Fundamentals.html" title="Virtualization Fundamentals">Virtualization Fundamentals</a> article provides links to some of the foundational work which underly modern virtualization industry and development today. If you'd like to understand both the theories on which virtualization builds as well as the history of industry you should read several articles here. Notable <i><a rel="nofollow" class="external text" href="https://en.m.wikipedia.org/wiki/Popek_and_Goldberg_virtualization_requirements">Popek and Goldberg Virtualization Requirements</a></i> as well as <i><a rel="nofollow" class="external text" href="https://www.cl.cam.ac.uk/research/srg/netos/papers/2003-xensosp.pdf">Xen and the Art of Virtualization</a></i> provide a great foundations-first approach to learning about virtualization. +</p> +<h3><span id="Virtual_I.2FO_Internals"></span><span class="mw-headline" id="Virtual_I/O_Internals">Virtual I/O Internals</span></h3> +<p>The <a href="Virtual_I/O_Internals.html" title="Virtual I/O Internals">Virtual I/O Internals</a> article provides a detailed look into the interface layers between IO driver internals, the hypervisor, and the guest OS. This is a great article to read if you'd like to better understand how virtual machines can interact with both discretely assigned devices as well as those which have been partitioned using software or firmware. +</p> +<h3><span class="mw-headline" id="GPU_Driver_Internals">GPU Driver Internals</span></h3> +<p>The <a href="GPU_Driver_Internals.html" title="GPU Driver Internals">GPU Driver Internals</a> article provides information on how GPU drivers are structured internally as well as how they achieve virtualization. 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class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Glossary</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"><span class="mw-redirectedfrom">(Redirected from <a href="../index.php%3Ftitle=Introductory_Concepts_&_Definitions&redirect=no.html" class="mw-redirect" title="Introductory Concepts & Definitions">Introductory Concepts & Definitions</a>)</span></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Introductory_Concepts_&_Definitions.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Introductory_Concepts_&_Definitions.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Introductory_Concepts_&_Definitions.html#Definitions"><span class="tocnumber">1</span> <span class="toctext">Definitions</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Introductory_Concepts_&_Definitions.html#VFIO"><span class="tocnumber">1.1</span> <span class="toctext">VFIO</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="Introductory_Concepts_&_Definitions.html#Mdev"><span class="tocnumber">1.2</span> <span class="toctext">Mdev</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="Introductory_Concepts_&_Definitions.html#Virtual_CPU_(vCPU)"><span class="tocnumber">1.3</span> <span class="toctext">Virtual CPU (vCPU)</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Introductory_Concepts_&_Definitions.html#Virtual_GPU_(vGPU)"><span class="tocnumber">1.4</span> <span class="toctext">Virtual GPU (vGPU)</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Introductory_Concepts_&_Definitions.html#IVSHMEM"><span class="tocnumber">1.5</span> <span class="toctext">IVSHMEM</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Introductory_Concepts_&_Definitions.html#KVMFR_(Looking_Glass)"><span class="tocnumber">1.6</span> <span class="toctext">KVMFR (Looking Glass)</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="Introductory_Concepts_&_Definitions.html#NUMA_Node"><span class="tocnumber">1.7</span> <span class="toctext">NUMA Node</span></a></li> +<li class="toclevel-2 tocsection-9"><a href="Introductory_Concepts_&_Definitions.html#Application_Binary_Interface_(ABI)"><span class="tocnumber">1.8</span> <span class="toctext">Application Binary Interface (ABI)</span></a></li> +<li class="toclevel-2 tocsection-10"><a href="Introductory_Concepts_&_Definitions.html#SR-IOV"><span class="tocnumber">1.9</span> <span class="toctext">SR-IOV</span></a></li> +<li class="toclevel-2 tocsection-11"><a href="Introductory_Concepts_&_Definitions.html#GVT-g"><span class="tocnumber">1.10</span> <span class="toctext">GVT-g</span></a></li> +<li class="toclevel-2 tocsection-12"><a href="Introductory_Concepts_&_Definitions.html#VirGL"><span class="tocnumber">1.11</span> <span class="toctext">VirGL</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Definitions">Definitions</span></h2> +<p>This article will attempt to provide a glossary of common terms that are either related to/or often used in connection with virtualization for those who may need more context. +</p><p>If you have suggestions on how to improve the glossary you can <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Main_Page#Getting_Started_Contributing_to_Open-IOV"><b>contribute</b></a> or join our <a rel="nofollow" class="external text" href="https://discord.gg/Rb9K9DYxKK"><b>community discussion thread</b></a> to make suggestions. +</p> +<h3><span class="mw-headline" id="VFIO">VFIO</span></h3> +<blockquote><p>Kernel.org defines VFIO or Virtual Function Input Output as <b>"an IOMMU/device agnostic framework for exposing direct device access to userspace, in a secure, IOMMU protected environment." <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/Documentation/vfio.txt">[1]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:VFIO_Diagram.png.html" class="image"><img alt="" src="../images/thumb/4/43/VFIO_Diagram.png/300px-VFIO_Diagram.png" decoding="async" width="300" height="397" class="thumbimage" srcset="../images/4/43/VFIO_Diagram.png 1.5x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:VFIO_Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting direct VFIO passthrough of a GPU adapter.</div></div></div> +<h3><span class="mw-headline" id="Mdev">Mdev</span></h3> +<blockquote><p>Kernel.org defines Virtual Function I/O (VFIO) Mediated devices as: <b>"an IOMMU/device-agnostic framework for exposing direct device access to user space in a secure, IOMMU-protected environment... mediated core driver provides a common interface for mediated device management that can be used by drivers of different devices." <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294">[2]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:VFIO-Mdev_Diagram.png.html" class="image"><img alt="" src="../images/thumb/c/c7/VFIO-Mdev_Diagram.png/300px-VFIO-Mdev_Diagram.png" decoding="async" width="300" height="397" class="thumbimage" srcset="../images/thumb/c/c7/VFIO-Mdev_Diagram.png/450px-VFIO-Mdev_Diagram.png 1.5x, ../images/c/c7/VFIO-Mdev_Diagram.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:VFIO-Mdev_Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting VFIO Mediated Device interacting with two vGPU guests.</div></div></div> +<h3><span id="Virtual_CPU_.28vCPU.29"></span><span class="mw-headline" id="Virtual_CPU_(vCPU)">Virtual CPU (vCPU)</span></h3> +<blockquote><p>A Virtual CPU (vCPU) is a CPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling.</p></blockquote> +<h3><span id="Virtual_GPU_.28vGPU.29"></span><span class="mw-headline" id="Virtual_GPU_(vGPU)">Virtual GPU (vGPU)</span></h3> +<blockquote><p>A Virtual GPU (vGPU) is a GPU which has been virtualized to represent a percentage of the total hardware resource via preemptive scheduling or thread pinning (to <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2023-0/intel-iris-xe-gpu-architecture.html">EUs</a>, or <a rel="nofollow" class="external text" href="https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf">SMs</a>) and/or a partition of the device's Video Random Access Memory (VRAM).</p></blockquote> +<h3><span class="mw-headline" id="IVSHMEM">IVSHMEM</span></h3> +<blockquote><p>According to QEMU's GitHub repo: <b>"The Inter-VM shared memory device (ivshmem) is designed to share a memory region between multiple QEMU processes running different guests and the host. In order for all guests to be able to pick up the shared memory area, it is modeled by QEMU as a PCI device exposing said memory to the guest as a PCI BAR."</b> <b><a rel="nofollow" class="external text" href="https://github.com/qemu/qemu/blob/master/docs/specs/ivshmem-spec.txt">[3]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:IVSHMEM.png.html" class="image"><img alt="" src="../images/thumb/d/d3/IVSHMEM.png/300px-IVSHMEM.png" decoding="async" width="300" height="203" class="thumbimage" srcset="../images/thumb/d/d3/IVSHMEM.png/450px-IVSHMEM.png 1.5x, ../images/thumb/d/d3/IVSHMEM.png/600px-IVSHMEM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:IVSHMEM.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting an inter-vm shared memory device being used by two separate virtual machines.</div></div></div> +<h3><span id="KVMFR_.28Looking_Glass.29"></span><span class="mw-headline" id="KVMFR_(Looking_Glass)">KVMFR (Looking Glass)</span></h3> +<blockquote><p>looking-glass.io defines Looking Glass as: <b>"an open source application that allows the use of a KVM (Kernel-based Virtual Machine) configured for VGA PCI Pass-through without an attached physical monitor, keyboard or mouse."</b> <b><a rel="nofollow" class="external text" href="https://looking-glass.io/">[4]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:KVMFR_Looking_Glass.png.html" class="image"><img alt="" src="../images/thumb/8/8a/KVMFR_Looking_Glass.png/300px-KVMFR_Looking_Glass.png" decoding="async" width="300" height="179" class="thumbimage" srcset="../images/thumb/8/8a/KVMFR_Looking_Glass.png/450px-KVMFR_Looking_Glass.png 1.5x, ../images/thumb/8/8a/KVMFR_Looking_Glass.png/600px-KVMFR_Looking_Glass.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:KVMFR_Looking_Glass.png.html" class="internal" title="Enlarge"></a></div>A image posted by Gnif (Creator of the Looking Glass project) to a changelog thread on the Level1techs forum - an active community of VFIO users.</div></div></div> +<h3><span class="mw-headline" id="NUMA_Node">NUMA Node</span></h3> +<blockquote><p>Infogalactic defines NUMA as: <b>"<i>Non-uniform memory access (NUMA) is a</i> computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory (memory local to another processor or memory shared between processors)." <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Non-uniform_memory_access">[5]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:NUMA_Node.png.html" class="image"><img alt="" src="../images/thumb/7/73/NUMA_Node.png/300px-NUMA_Node.png" decoding="async" width="300" height="151" class="thumbimage" srcset="../images/thumb/7/73/NUMA_Node.png/450px-NUMA_Node.png 1.5x, ../images/thumb/7/73/NUMA_Node.png/600px-NUMA_Node.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:NUMA_Node.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting Non-Uniform Memory Access (NUMA) nodes.</div></div></div> +<h3><span id="Application_Binary_Interface_.28ABI.29"></span><span class="mw-headline" id="Application_Binary_Interface_(ABI)">Application Binary Interface (ABI)</span></h3> +<blockquote><p>Infogalactic defines an ABI as <b>"the interface between two program modules, one of which is often a library or operating system, at the level of machine code."</b> <b><a rel="nofollow" class="external text" href="https://infogalactic.com/info/Application_binary_interface">[6]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Application_Binary_Interface_(ABI).png.html" class="image"><img alt="" src="../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/300px-Application_Binary_Interface_(ABI).png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/450px-Application_Binary_Interface_(ABI).png 1.5x, ../images/thumb/9/9d/Application_Binary_Interface_(ABI).png/600px-Application_Binary_Interface_(ABI).png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Application_Binary_Interface_(ABI).png.html" class="internal" title="Enlarge"></a></div>A diagram contrasting API and ABI as well as their respective roles in software compatibility.</div></div></div> +<h3><span class="mw-headline" id="SR-IOV">SR-IOV</span></h3> +<blockquote><p>docs.microsoft.com defines SR-IOV as <b>"The single root I/O virtualization (SR-IOV) interface is an extension to the PCI Express (PCIe) specification. SR-IOV allows a device, such as a network adapter, to separate access to its resources among various PCIe hardware functions." <a rel="nofollow" class="external text" href="https://archive.is/FcDoK">[7]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:SR-IOV.png.html" class="image"><img alt="" src="../images/thumb/6/65/SR-IOV.png/300px-SR-IOV.png" decoding="async" width="300" height="238" class="thumbimage" srcset="../images/thumb/6/65/SR-IOV.png/450px-SR-IOV.png 1.5x, ../images/thumb/6/65/SR-IOV.png/600px-SR-IOV.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:SR-IOV.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting host and guest interactions in a Single Root I/O Virtualization environment.</div></div></div> +<h3><span class="mw-headline" id="GVT-g">GVT-g</span></h3> +<blockquote><p>wiki.archlinux.org defines Intel GVT-g as <b>"a technology that provides mediated device passthrough for Intel GPUs (Broadwell and newer). It can be used to virtualize the GPU for multiple guest virtual machines, effectively providing near-native graphics performance in the virtual machine and still letting your host use the virtualized GPU normally." <a rel="nofollow" class="external text" href="https://wiki.archlinux.org/title/Intel_GVT-g">[8]</a></b></p></blockquote> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:SR-IOV-Diagram.png.html" class="image"><img alt="" src="../images/thumb/d/df/SR-IOV-Diagram.png/300px-SR-IOV-Diagram.png" decoding="async" width="300" height="258" class="thumbimage" srcset="../images/thumb/d/df/SR-IOV-Diagram.png/450px-SR-IOV-Diagram.png 1.5x, ../images/thumb/d/df/SR-IOV-Diagram.png/600px-SR-IOV-Diagram.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:SR-IOV-Diagram.png.html" class="internal" title="Enlarge"></a></div>A diagram of Intel's GVT-g (Graphics Virtualization Technology g).</div></div></div> +<h3><span class="mw-headline" id="VirGL">VirGL</span></h3> +<blockquote><div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Virgl.png.html" class="image"><img alt="" src="../images/thumb/b/b4/Virgl.png/300px-Virgl.png" decoding="async" width="300" height="398" class="thumbimage" srcset="../images/b/b4/Virgl.png 1.5x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Virgl.png.html" class="internal" title="Enlarge"></a></div>A diagram depicting GPU instruction redirects to a single host graphics driver.</div></div></div><p>lwn.net defines Virgl as: <b>"a way for guests running in a virtual machine (VM) to access the host GPU using OpenGL and other APIs... The virgl stack consists of an application running in the guest that sends OpenGL to the Mesa virgl driver, which uses the virtio-gpu driver in the guest kernel to communicate with QEMU on the host."</b> <b><a rel="nofollow" class="external text" href="https://lwn.net/Articles/767970/">[9]</a></b></p></blockquote> +<!-- +NewPP limit report +Cached time: 20260911202651 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.022 seconds +Real time usage: 0.024 seconds +Preprocessor visited node count: 87/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 27/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:13-0!canonical and timestamp 20260911202651 and revision id 23763. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/LIME_Is_Mediated_Emulation.html b/wiki/open-iov.org/index.php/LIME_Is_Mediated_Emulation.html new file mode 100644 index 0000000..bc7eb15 --- /dev/null +++ b/wiki/open-iov.org/index.php/LIME_Is_Mediated_Emulation.html @@ -0,0 +1,259 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>LIME Is Mediated Emulation - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"9ad8c169f123bd25676c2f07","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"LIME_Is_Mediated_Emulation","wgTitle":"LIME Is Mediated Emulation","wgCurRevisionId":786,"wgRevisionId":786,"wgArticleId":89,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"LIME_Is_Mediated_Emulation","wgRelevantArticleId":89,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en", +"pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","mediawiki.toc","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="../load.php%3Flang=en&modules=ext.visualEditor.desktopArticleTarget.noscript|skins.vector.styles.legacy&only=styles&skin=vector.css"/> +<script async="" src="../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-LIME_Is_Mediated_Emulation rootpage-LIME_Is_Mediated_Emulation skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >LIME Is Mediated Emulation</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="LIME_Is_Mediated_Emulation.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="LIME_Is_Mediated_Emulation.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>LIME Is Mediated Emulation is an in-development feature in <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/"></a> which enables the execution of full performance <a rel="nofollow" class="external text" href="https://docs.microsoft.com/en-us/windows/win32/winprog64/programming-guide-for-64-bit-windows">Win64</a> binaries with full compatibility for all current and future software making use of the Windows ABI. An initial demo of this technology can be viewed <a rel="nofollow" class="external text" href="https://streamable.com/ps3wdg">here</a>. +</p> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="LIME_Is_Mediated_Emulation.html#Design_Goals"><span class="tocnumber">1</span> <span class="toctext">Design Goals</span></a></li> +<li class="toclevel-1 tocsection-2"><a href="LIME_Is_Mediated_Emulation.html#Use-Cases"><span class="tocnumber">2</span> <span class="toctext">Use-Cases</span></a> +<ul> +<li class="toclevel-2 tocsection-3"><a href="LIME_Is_Mediated_Emulation.html#Win64_Subsystem"><span class="tocnumber">2.1</span> <span class="toctext">Win64 Subsystem</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="LIME_Is_Mediated_Emulation.html#Win64_Orchestration"><span class="tocnumber">2.2</span> <span class="toctext">Win64 Orchestration</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="LIME_Is_Mediated_Emulation.html#Compatibility_With_Other_ABIs"><span class="tocnumber">2.3</span> <span class="toctext">Compatibility With Other ABIs</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="LIME_Is_Mediated_Emulation.html#Quality_of_Service_(QoS)"><span class="tocnumber">2.4</span> <span class="toctext">Quality of Service (QoS)</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-7"><a href="LIME_Is_Mediated_Emulation.html#Development_Status"><span class="tocnumber">3</span> <span class="toctext">Development Status</span></a> +<ul> +<li class="toclevel-2 tocsection-8"><a href="LIME_Is_Mediated_Emulation.html#VirtIO-FS"><span class="tocnumber">3.1</span> <span class="toctext">VirtIO-FS</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Design_Goals">Design Goals</span></h2> +<p>LIME aims to provide similar functionality to <a rel="nofollow" class="external text" href="https://winehq.org/">WINE Is Not Emulation</a>, Valve's <a rel="nofollow" class="external text" href="https://github.com/ValveSoftware/Proton/">Proton</a> / <a rel="nofollow" class="external text" href="https://github.com/ValveSoftware/dxvk">DXVK</a> but with the use of graphics virtualization (vGPU/SR-IOV on consumer GPUs), a shared filesystem between host/guest, and <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Looking_Glass_KVMFR">KVM Frame Relay</a> (high performance graphics buffer sharing via <a rel="nofollow" class="external text" href="https://www.qemu.org/docs/master/system/devices/ivshmem.html">Inter-VM Shared Memory Device / IVSHMEM</a>). +</p><p>Compared to WINE, and Proton the benefits of this approach are that Win64 binaries execute without the incompatibilities introduced in new games taking advantage of the latest version of <a rel="nofollow" class="external text" href="https://docs.microsoft.com/en-us/windows/win32/directx">DirectX</a>, or when changes are introduced to the latest version of the Win64 <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Application_binary_interface">ABI</a>. +</p><p>This functionality is enabled via the use of <a rel="nofollow" class="external text" href="">GPU Virtual Machine</a> (for consumer GPU Virtualization), <a rel="nofollow" class="external text" href="https://virtio-fs.gitlab.io/design.html">VirtIO-FS</a> (for host <-> guest filesystem sharing), <a rel="nofollow" class="external text" href="https://looking-glass.io/">Looking Glass</a> (for host <-> guest shared frame buffer), and <a rel="nofollow" class="external text" href="https://github.com///tree/master//"></a> (for orchestration). +</p> +<h2><span class="mw-headline" id="Use-Cases">Use-Cases</span></h2> +<h3><span class="mw-headline" id="Win64_Subsystem">Win64 Subsystem</span></h3> +<p>LIME's most immediate use case is around ABI compatibility with Win64 programs in environments without native support. +</p><p><b>A blog post detailing the problems which lead to this work can be read here</b>. A summary of this post is traditional models for backwards compatibility with Application Binary Interfaces (ABIs) lock-in existing models for kernel/userland development and stagnate architectural innovation. On the other hand consumer oriented systems like those based on <a rel="nofollow" class="external text" href="https://github.com/apple/darwin-xnu">Darwin/XNU</a> break backwards compatibility with user programs version to version of the system in order to introduce architectural improvements in the kernel / userland (for instance micro-service device drivers which may recover from faults at OS runtime). +</p><p>These two approaches might be considered two discretely separable models for software development <i>'enterprise'</i> /<i>'consumer'</i> - LIME might then be considered a third approach which preserves the functions of both prior approaches (continual innovation afforded in the kernel-space and backwards compatibility with existing software libraries). +</p><p>ie: A method by which programs "import" a particular explicitly versioned ABI similar to how <a rel="nofollow" class="external text" href="https://docs.docker.com/engine/api/latest/">Docker</a> provisions <a rel="nofollow" class="external text" href="https://wiki.archlinux.org/title/Chroot">chroot</a> resources like configuration files and support libraries, but extended to drivers, and the kernel. +</p> +<h3><span class="mw-headline" id="Win64_Orchestration">Win64 Orchestration</span></h3> +<p>Because LIME necessarily provisions application data, program files, and <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Glossary#NUMA_Node">NUMA</a>-aware vCPU/vGPU resources (in the context of multi-GPU, multi-socket CPU systems) through for automatic execution by one or more VM guests LIME might provide an ideal architecture for orchestration of Win64 applications at scale. This could include execution of programs for game streaming in a server environment, or multiple applications in a single user environment for '<a rel="nofollow" class="external text" href="https://github.com/Qubes-Community/Contents/blob/master/docs/os/windows/windows-tools.md#using-windows-appvms-in-seamless-mode">seamless-mode</a>' execution of guest programs similar to that of <a rel="nofollow" class="external text" href="https://www.qubes-os.org/doc/">QubesOS</a> with hardware GPU acceleration added. +</p> +<h3><span class="mw-headline" id="Compatibility_With_Other_ABIs">Compatibility With Other ABIs</span></h3> +<p>To solve the problems of 'ABI lock-in' discussed in the "Why Computers Suck" post it may be possible to port LIME support to multiple different guest operating systems allowing execution of any program with any ABI with near indistinguishable performance compared to native execution. +</p> +<h3><span id="Quality_of_Service_.28QoS.29"></span><span class="mw-headline" id="Quality_of_Service_(QoS)">Quality of Service (QoS)</span></h3> +<p><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO-Mdev</a> functionality like that used in <a rel="nofollow" class="external text" href="">GPU Virtual Machine (GVM)</a> provides granular GPU resource allocation and load balancing functions similar to those seen in <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Cgroups">control groups (cgroups)</a> as they are commonly applied today to RAM and CPU resources. In the context LIME VFIO-Mdev could be applied for load balancing of individual processes running in a virtualized state to ensure individual processes making use of the GPU cannot deny service to others on the system. +</p> +<h2><span class="mw-headline" id="Development_Status">Development Status</span></h2> +<p>Development of this functionality is ongoing. Efforts to improve LIME are primarily focused on stabilization of shared filesystem functions. +</p> +<h3><span class="mw-headline" id="VirtIO-FS">VirtIO-FS</span></h3> +<p>VirtIO-FS provides shared filesystem functionality between host and guest using <a rel="nofollow" class="external text" href="https://github.com/libfuse/libfuse">FUSE</a> which is ideal for LIME, however in the context of Windows guests the C version of virtiofsd appears unstable (seen in <a rel="nofollow" class="external text" href="https://github.com/virtio-win/kvm-guest-drivers-windows">virtio-win</a> issue <a rel="nofollow" class="external text" href="https://github.com/virtio-win/kvm-guest-drivers-windows/issues/550">550 [closed]</a>, <a rel="nofollow" class="external text" href="https://github.com/virtio-win/kvm-guest-drivers-windows/issues/723">723 [closed]</a>, <a rel="nofollow" class="external text" href="https://github.com/virtio-win/kvm-guest-drivers-windows/issues/724">724 [open]</a>). Testing has been performed by members of the Open-IOV community which have shown initial signs of increased filesystem stability under continuous read/write loads using the Rust version of virtiofsd (<a rel="nofollow" class="external text" href="https://gitlab.com/virtio-fs/virtiofsd">virtiofsd-rs</a>). +</p><p>While many programs can be stored in the VirtIO-FS shared directory some programs such as <a rel="nofollow" class="external text" href="https://store.steampowered.com/">Steam</a> don't want to install programs into the VirtIO-FS drive (seen as a secondary drive in Windows - in often as disk D:/ if no additional media is attached). This game installation behaviour (which drive the user may place their programs in) may not be in common with other game stores such as the <a rel="nofollow" class="external text" href="https://store.epicgames.com/en-US/">Epic Games Store</a>, or <a rel="nofollow" class="external text" href="https://www.gog.com/good-old-games">Good Old Games (GOG)</a>. +</p> +<!-- +NewPP limit report +Cached time: 20260911202652 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.012 seconds +Real time usage: 0.017 seconds +Preprocessor visited node count: 45/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 34/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:89-0!canonical and timestamp 20260911202652 and revision id 786. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Looking_Glass_KVMFR.html b/wiki/open-iov.org/index.php/Looking_Glass_KVMFR.html new file mode 100644 index 0000000..329fc22 --- /dev/null +++ b/wiki/open-iov.org/index.php/Looking_Glass_KVMFR.html @@ -0,0 +1,222 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Looking Glass KVMFR - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"83b75a01a79aa09de5359dd0","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Looking_Glass_KVMFR","wgTitle":"Looking Glass KVMFR","wgCurRevisionId":855,"wgRevisionId":855,"wgArticleId":32,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"Looking_Glass_KVMFR","wgRelevantArticleId":32,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr", +"pageVariantFallbacks":"en"},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Mdev-GPU.html b/wiki/open-iov.org/index.php/Mdev-GPU.html new file mode 100644 index 0000000..de97b4e --- /dev/null +++ b/wiki/open-iov.org/index.php/Mdev-GPU.html @@ -0,0 +1,362 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Mdev-GPU - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"5ef7a992113490dfbfb2e42f","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Mdev-GPU","wgTitle":"Mdev-GPU","wgCurRevisionId":23740,"wgRevisionId":23740,"wgArticleId":85,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"Mdev-GPU","wgRelevantArticleId":85,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"}, +"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","mediawiki.toc","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="../load.php%3Flang=en&modules=ext.visualEditor.desktopArticleTarget.noscript|skins.vector.styles.legacy&only=styles&skin=vector.css"/> +<script async="" src="../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Mdev-GPU rootpage-Mdev-GPU skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Mdev-GPU</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Mdev-GPU.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Mdev-GPU.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>This page makes use of terms that are defined in the <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Glossary"><i>Open-IOV Glossary</i></a>. If you're curious what a given term means you can check there for a definition. +</p><p><br /> +</p><p>This page will be used to document the <b>Mdev-GPU API</b> as well as provide an overview of the internals of the Mdev-GPU package. +</p><p>Mdev-GPU's source code can be found <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU">here</a>. +</p><p> +Module docs can be found <a rel="nofollow" class="external text" href="">here</a>.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Mdev-GPU.html#Compilation"><span class="tocnumber">1</span> <span class="toctext">Compilation</span></a></li> +<li class="toclevel-1 tocsection-2"><a href="Mdev-GPU.html#Installation"><span class="tocnumber">2</span> <span class="toctext">Installation</span></a></li> +<li class="toclevel-1 tocsection-3"><a href="Mdev-GPU.html#Mdev-GPU_Configuration"><span class="tocnumber">3</span> <span class="toctext">Mdev-GPU Configuration</span></a> +<ul> +<li class="toclevel-2 tocsection-4"><a href="Mdev-GPU.html#Systemd"><span class="tocnumber">3.1</span> <span class="toctext">Systemd</span></a> +<ul> +<li class="toclevel-3 tocsection-5"><a href="Mdev-GPU.html#mdev-post.service"><span class="tocnumber">3.1.1</span> <span class="toctext">mdev-post.service</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-6"><a href="Mdev-GPU.html#Mdev-CLI"><span class="tocnumber">3.2</span> <span class="toctext">Mdev-CLI</span></a> +<ul> +<li class="toclevel-3 tocsection-7"><a href="Mdev-GPU.html#num"><span class="tocnumber">3.2.1</span> <span class="toctext">num</span></a></li> +<li class="toclevel-3 tocsection-8"><a href="Mdev-GPU.html#vDevId"><span class="tocnumber">3.2.2</span> <span class="toctext">vDevId</span></a></li> +<li class="toclevel-3 tocsection-9"><a href="Mdev-GPU.html#pDevId"><span class="tocnumber">3.2.3</span> <span class="toctext">pDevId</span></a></li> +<li class="toclevel-3 tocsection-10"><a href="Mdev-GPU.html#name"><span class="tocnumber">3.2.4</span> <span class="toctext">name</span></a></li> +<li class="toclevel-3 tocsection-11"><a href="Mdev-GPU.html#gpuClass"><span class="tocnumber">3.2.5</span> <span class="toctext">gpuClass</span></a></li> +<li class="toclevel-3 tocsection-12"><a href="Mdev-GPU.html#maxInstances"><span class="tocnumber">3.2.6</span> <span class="toctext">maxInstances</span></a></li> +<li class="toclevel-3 tocsection-13"><a href="Mdev-GPU.html#virtDisplay"><span class="tocnumber">3.2.7</span> <span class="toctext">virtDisplay</span></a> +<ul> +<li class="toclevel-4 tocsection-14"><a href="Mdev-GPU.html#numHeads"><span class="tocnumber">3.2.7.1</span> <span class="toctext">numHeads</span></a></li> +<li class="toclevel-4 tocsection-15"><a href="Mdev-GPU.html#maxResX"><span class="tocnumber">3.2.7.2</span> <span class="toctext">maxResX</span></a></li> +<li class="toclevel-4 tocsection-16"><a href="Mdev-GPU.html#maxResY"><span class="tocnumber">3.2.7.3</span> <span class="toctext">maxResY</span></a></li> +<li class="toclevel-4 tocsection-17"><a href="Mdev-GPU.html#frlConfig"><span class="tocnumber">3.2.7.4</span> <span class="toctext">frlConfig</span></a></li> +<li class="toclevel-4 tocsection-18"><a href="Mdev-GPU.html#frlEnable"><span class="tocnumber">3.2.7.5</span> <span class="toctext">frlEnable</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-19"><a href="Mdev-GPU.html#ecc"><span class="tocnumber">3.2.8</span> <span class="toctext">ecc</span></a></li> +<li class="toclevel-3 tocsection-20"><a href="Mdev-GPU.html#fbLen"><span class="tocnumber">3.2.9</span> <span class="toctext">fbLen</span></a></li> +<li class="toclevel-3 tocsection-21"><a href="Mdev-GPU.html#fbRes"><span class="tocnumber">3.2.10</span> <span class="toctext">fbRes</span></a></li> +<li class="toclevel-3 tocsection-22"><a href="Mdev-GPU.html#mapVideoSize"><span class="tocnumber">3.2.11</span> <span class="toctext">mapVideoSize</span></a></li> +<li class="toclevel-3 tocsection-23"><a href="Mdev-GPU.html#encCap"><span class="tocnumber">3.2.12</span> <span class="toctext">encCap</span></a></li> +<li class="toclevel-3 tocsection-24"><a href="Mdev-GPU.html#bar1Len"><span class="tocnumber">3.2.13</span> <span class="toctext">bar1Len</span></a></li> +</ul> +</li> +</ul> +</li> +</ul> +</div> + +<h3><span class="mw-headline" id="Compilation">Compilation</span></h3> +<p>Compiling Mdev-GPU from source is very simple however it can take a long time to complete (10 minutes for existing sources). +</p><p>If you'd like to compile Mdev-GPU yourself you can do so by cloning <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU">the repo</a> and running the following two commands from within the repository directory: +</p><p><code>curl -sSL https://get.haskellstack.org/ | sh</code> +</p><p><code>stack install</code> +</p><p>These commands will generate all binaries provided by Mdev-GPU under the path <code>~/.local/bin/</code>. +</p><p>If you would prefer not to wait for the program to compile you can find pre-compiled x86_64 binaries under the <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU/releases/tag/0.1.0.0">Releases section of the repository on GitHub</a>. +</p> +<h3><span class="mw-headline" id="Installation">Installation</span></h3> +<p>The binaries compiled on your local machine by Stack in the <code>~/.local/bin/</code> path or downloaded from <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU/releases">Releases on GitHub</a> should be copied to <code>/usr/bin/</code>. This can be accomplished both via install script (currently testing in ) or via management layer-agnostic package. +</p> +<h3><span class="mw-headline" id="Mdev-GPU_Configuration">Mdev-GPU Configuration</span></h3> +<p>The Mdev-GPU repository provides Systemd service and example configurations for Mdev-CLI in the <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU/tree/master/etc">/etc/ folder</a>. On installation the directories & files contained in the repository's /etc/ folder should be copied to the absolute path <code>/etc/</code> on the user's computer. +</p> +<h4><span class="mw-headline" id="Systemd">Systemd</span></h4> +<p>GVM/Mdev-GPU exposes several of it's functions as Systemd services. +</p><p>As of the 0.1.0.0 release the following Systemd services are available: +</p> +<ul><li><b>mdev-post.service</b></li></ul> +<h5><span class="mw-headline" id="mdev-post.service">mdev-post.service</span></h5> +<p>As the name would suggest <b><a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU/blob/master/etc/systemd/system/mdev-post.service">mdev-post.service</a></b> posts the GPU(s) in a state where they are ready to be virtualized. When the service is invoked the mdev-cli util registers Mdev callbacks and supported mediated device (Mdev) types with the Mediated Core according to the user's specified configuration at <b><code>/etc/gvm/mdev-gpu/generate-vgpu-types.yaml</code></b>. If you'd like to place your configuration file elsewhere and still have your configuration invoked on boot you can edit the systemd service <a rel="nofollow" class="external text" href="https://github.com//Mdev-GPU/blob/9993fd0781ddddfcca2cb9bee6455ea2c024cc23/etc/systemd/system/mdev-post.service#L10">ExecStart= line</a> to specify an alternative path. +</p> +<h4><span class="mw-headline" id="Mdev-CLI">Mdev-CLI</span></h4> +<p>Configuration for Mdev-GPU can be found in the path <b><code>/etc/gvm/mdev-gpu/</code></b>. This path will by default contain several vendor-specific folders which may include configuration examples for various devices/architectures as well as the file <code><b>generate-vgpu-types.yaml</b></code> which you can configure to specify your desired Virtual GPU (vGPU) / VFIO-Mdev topologies as they are presented in the sysfsdev mdev_bus path and as seen by tools such as <a rel="nofollow" class="external text" href="https://github.com/mdevctl/mdevctl">mdevctl</a>. Once you have configured the available types your liking you can refresh the supported types registered with the <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals#Mediated_Core">Mediated Core</a> by rebooting your machine or reloading the vendor driver kernel module then restarting <b>mdev-post.service</b> or by invoking <b>mdev-cli</b>. +</p><p><br /> +The available yaml properties which may be specified in <b><code>/etc/gvm/mdev-gpu/generate-vgpu-types.yaml</code></b> are shown below. Note that fields with the <sup>[required]</sup> tag must be specified in the yaml file whereas fields with the <sup>[optional]</sup> tag may be omitted from configuration if you would prefer to rely upon default parameters instead. +</p> +<h5><span class="mw-headline" id="num">num</span></h5> +<p><sup>[required]</sup> +</p><p>num refers to the Mediated Device (Mdev) type number. This value specifies the profile's numerical identifier in the sysfsdev mdev_bus path. +</p> +<h5><span class="mw-headline" id="vDevId">vDevId</span></h5> +<p><sup>[optional]</sup> +</p><p>The vGPU (Virtual GPU) PCI Device ID which should be presented to the guest. +</p> +<h5><span class="mw-headline" id="pDevId">pDevId</span></h5> +<p><sup>[optional]</sup> +</p><p>The pGPU (Physical GPU) PCI Device ID which should be presented to the host. +</p> +<h5><span class="mw-headline" id="name">name</span></h5> +<p><sup>[optional]</sup> +</p><p>The GPU name presented to the guest. +</p> +<h5><span class="mw-headline" id="gpuClass">gpuClass</span></h5> +<p><sup>[optional]</sup> +</p><p>The class of GPU to use. +</p><p>available strings: +</p><p>"Compute" +</p><p>"Graphics" +</p> +<h5><span class="mw-headline" id="maxInstances">maxInstances</span></h5> +<p><sup>[required]</sup> +</p><p>maxInstances refers to the maximum number of instances available of any given Mediated Device (Mdev) profile. This number can be configured arbitrarily however it should ideally not be set to a value which allows for fbLen/fbRes values that allow a number of Mdev devices to be created which would exceed your device's available VRAM. +</p> +<h5><span class="mw-headline" id="virtDisplay">virtDisplay</span></h5> +<p><sup>[optional]</sup> +</p><p>virtDisplay controls the topologies of virtual displays. virtDisplay exposes the following user configurable properties: +</p> +<h6><span class="mw-headline" id="numHeads">numHeads</span></h6> +<p><sup>[optional]</sup> +</p><p>Number of heads [virtual monitors] available for each Mediated Device (Mdev). +</p> +<h6><span class="mw-headline" id="maxResX">maxResX</span></h6> +<p><sup>[optional]</sup> +</p><p>Maximum width of the mediated display. +</p> +<h6><span class="mw-headline" id="maxResY">maxResY</span></h6> +<p><sup>[optional]</sup> +</p><p>Maximum height of the mediated display. +</p> +<h6><span class="mw-headline" id="frlConfig">frlConfig</span></h6> +<p><sup>[optional]</sup> +</p><p>Frame rate limiter for the mediated display. +</p> +<h6><span class="mw-headline" id="frlEnable">frlEnable</span></h6> +<p><sup>[optional]</sup> +</p><p>Do we enable frame rate limiting or not? +</p> +<h5><span class="mw-headline" id="ecc">ecc</span></h5> +<p><sup>[optional]</sup> +</p><p>ecc refers to if error correcting memory should be used. +</p> +<h5><span class="mw-headline" id="fbLen">fbLen</span></h5> +<p><sup>[required]</sup> +</p><p>fbLen is the framebuffer length (in megabytes). +</p> +<h5><span class="mw-headline" id="fbRes">fbRes</span></h5> +<p><sup>[required]</sup> +</p><p>fbRes is the framebuffer reserved by the hypervisor (in megabytes). In most circumstances this value should scale to around 1/7th the size of your chosen fbLen value. +</p> +<h5><span class="mw-headline" id="mapVideoSize">mapVideoSize</span></h5> +<p><sup>[optional]</sup> +</p><p>Mappable video size in MBs, 24 by default. +</p> +<h5><span class="mw-headline" id="encCap">encCap</span></h5> +<p><sup>[optional]</sup> +</p><p>Percentage we use the NvEnc hardware. +</p> +<h5><span class="mw-headline" id="bar1Len">bar1Len</span></h5> +<p><sup>[optional]</sup> +</p><p>bar1Len refers to the size of the Base Address Registers for BAR1 (MSI) as presented by the <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_I/O_Internals#VFIO_device_file_descriptor">VFIO File Descriptor</a>. +</p> +<!-- +NewPP limit report +Cached time: 20260911171856 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.023 seconds +Real time usage: 0.028 seconds +Preprocessor visited node count: 77/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 29/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:85-0!canonical and timestamp 20260911171856 and revision id 23740. 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Mediated_Device_Internals.html b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html new file mode 100644 index 0000000..fb28c2e --- /dev/null +++ b/wiki/open-iov.org/index.php/Mediated_Device_Internals.html @@ -0,0 +1,1014 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Virtual I/O Internals - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"56251ac5d852c262225539cd","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Virtual_I/O_Internals","wgTitle":"Virtual I/O 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id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Virtual I/O Internals</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"><span class="mw-redirectedfrom">(Redirected from <a href="../index.php%3Ftitle=Mediated_Device_Internals&redirect=no.html" class="mw-redirect" title="Mediated Device Internals">Mediated Device Internals</a>)</span></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Mediated_Device_Internals.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Mediated_Device_Internals.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>The following document details the internals of a <b>VFIO (Virtual Function I/O)</b> driven <b>Shared</b> <b>I/O Device.</b></p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<p>This article places emphasis on the <b>Virtual GPU (vGPU)</b> use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +</p> +<table class="wikitable"> +<caption>Comparison of Assistance Modes +</caption> +<tbody><tr> +<th>Mdev Mode +</th> +<th>SR-IOV Mode +</th> +<th>SIOV Mode +</th></tr> +<tr> +<td>No hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td></tr> +<tr> +<td>Host requires insight about guest workload. +</td> +<td>Host ignorance of guest workload. +</td> +<td>Host requires insight about guest workload. +</td></tr> +<tr> +<td>Error reporting. +</td> +<td>No guest driver error reporting. +</td> +<td>Error reporting. +</td></tr> +<tr> +<td>In depth dynamic monitoring. +</td> +<td>Basic dynamic monitoring. +</td> +<td>In depth dynamic monitoring. +</td></tr> +<tr> +<td>Software defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td></tr> +<tr> +<td>Requires deferred instructions to be supported by host software (support libraries). +</td> +<td>Guest is ignorant of host supported software such as support libraries. +</td> +<td> +</td></tr> +<tr> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td></tr> +<tr> +<td>Device reset. +</td> +<td>Device reset. +</td> +<td>Device reset. +</td></tr> +<tr> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td></tr> +<tr> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td></tr> +<tr> +<td>Single PCI requester ID. +</td> +<td>Multiple PCI requester IDs. +</td> +<td>Multiple PCI requester IDs. +</td></tr></tbody></table> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Mediated_Device_Internals.html#All_Modes"><span class="tocnumber">1</span> <span class="toctext">All Modes</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Mediated_Device_Internals.html#Knowledge_Resources_Used"><span class="tocnumber">1.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="Mediated_Device_Internals.html#Binding_VFIO_devices"><span class="tocnumber">1.2</span> <span class="toctext">Binding VFIO devices</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="Mediated_Device_Internals.html#Programming_the_IOMMU"><span class="tocnumber">1.3</span> <span class="toctext">Programming the IOMMU</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Mediated_Device_Internals.html#VFIO_Memory_Mapped_IO"><span class="tocnumber">1.4</span> <span class="toctext">VFIO Memory Mapped IO</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Mediated_Device_Internals.html#Getting_the_VFIO_Group_File_Descriptor"><span class="tocnumber">1.5</span> <span class="toctext">Getting the VFIO Group File Descriptor</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Mediated_Device_Internals.html#VFIO_device_file_descriptor"><span class="tocnumber">1.6</span> <span class="toctext">VFIO device file descriptor</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="Mediated_Device_Internals.html#VFIO_Interrupts"><span class="tocnumber">1.7</span> <span class="toctext">VFIO Interrupts</span></a> +<ul> +<li class="toclevel-3 tocsection-9"><a href="Mediated_Device_Internals.html#IRQs"><span class="tocnumber">1.7.1</span> <span class="toctext">IRQs</span></a> +<ul> +<li class="toclevel-4 tocsection-10"><a href="Mediated_Device_Internals.html#Get_Device_Info"><span class="tocnumber">1.7.1.1</span> <span class="toctext">Get Device Info</span></a></li> +<li class="toclevel-4 tocsection-11"><a href="Mediated_Device_Internals.html#Get_Region_Info"><span class="tocnumber">1.7.1.2</span> <span class="toctext">Get Region Info</span></a></li> +<li class="toclevel-4 tocsection-12"><a href="Mediated_Device_Internals.html#Get_IRQ_Info"><span class="tocnumber">1.7.1.3</span> <span class="toctext">Get IRQ Info</span></a></li> +<li class="toclevel-4 tocsection-13"><a href="Mediated_Device_Internals.html#Set_IRQs"><span class="tocnumber">1.7.1.4</span> <span class="toctext">Set IRQs</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-14"><a href="Mediated_Device_Internals.html#Device_Decomposure/Recomposure"><span class="tocnumber">1.8</span> <span class="toctext">Device Decomposure/Recomposure</span></a></li> +<li class="toclevel-2 tocsection-15"><a href="Mediated_Device_Internals.html#Memory_Management_Unit_(MMU)"><span class="tocnumber">1.9</span> <span class="toctext">Memory Management Unit (MMU)</span></a> +<ul> +<li class="toclevel-3 tocsection-16"><a href="Mediated_Device_Internals.html#MMIO_Isolation_(Platform_MMU)"><span class="tocnumber">1.9.1</span> <span class="toctext">MMIO Isolation (Platform MMU)</span></a></li> +<li class="toclevel-3 tocsection-17"><a href="Mediated_Device_Internals.html#VRAM_Isolation_(GPU_GMMU)"><span class="tocnumber">1.9.2</span> <span class="toctext">VRAM Isolation (GPU GMMU)</span></a></li> +<li class="toclevel-3 tocsection-18"><a href="Mediated_Device_Internals.html#Platform_MMIO_<->_GPU_Shadow_Pages"><span class="tocnumber">1.9.3</span> <span class="toctext">Platform MMIO <-> GPU Shadow Pages</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-19"><a href="Mediated_Device_Internals.html#VFIO_Quirks_(region_traps)"><span class="tocnumber">1.10</span> <span class="toctext">VFIO Quirks (region traps)</span></a></li> +<li class="toclevel-2 tocsection-20"><a href="Mediated_Device_Internals.html#Known_IOMMU_Issues"><span class="tocnumber">1.11</span> <span class="toctext">Known IOMMU Issues</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-21"><a href="Mediated_Device_Internals.html#Mdev_Mode"><span class="tocnumber">2</span> <span class="toctext">Mdev Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-22"><a href="Mediated_Device_Internals.html#Knowledge_Resources_Used_2"><span class="tocnumber">2.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-23"><a href="Mediated_Device_Internals.html#Mediated_Core"><span class="tocnumber">2.2</span> <span class="toctext">Mediated Core</span></a></li> +<li class="toclevel-2 tocsection-24"><a href="Mediated_Device_Internals.html#Device_Initialization"><span class="tocnumber">2.3</span> <span class="toctext">Device Initialization</span></a> +<ul> +<li class="toclevel-3 tocsection-25"><a href="Mediated_Device_Internals.html#Registering_VFIO_MDEV_as_a_driver"><span class="tocnumber">2.3.1</span> <span class="toctext">Registering VFIO MDEV as a driver</span></a></li> +<li class="toclevel-3 tocsection-26"><a href="Mediated_Device_Internals.html#Registering_PCIE_Device_with_the_Mediated_Core"><span class="tocnumber">2.3.2</span> <span class="toctext">Registering PCIE Device with the Mediated Core</span></a></li> +<li class="toclevel-3 tocsection-27"><a href="Mediated_Device_Internals.html#Registering_Mediated_Callbacks_(CBs)"><span class="tocnumber">2.3.3</span> <span class="toctext">Registering Mediated Callbacks (CBs)</span></a></li> +<li class="toclevel-3 tocsection-28"><a href="Mediated_Device_Internals.html#Creating_a_Mediated_Device_via_mdev-sysfsdev_API"><span class="tocnumber">2.3.4</span> <span class="toctext">Creating a Mediated Device via mdev-sysfsdev API</span></a></li> +<li class="toclevel-3 tocsection-29"><a href="Mediated_Device_Internals.html#QEMU_adds_VFIO_device_to_IOMMU_container-group"><span class="tocnumber">2.3.5</span> <span class="toctext">QEMU adds VFIO device to IOMMU container-group</span></a></li> +<li class="toclevel-3 tocsection-30"><a href="Mediated_Device_Internals.html#QEMU_passes_mdev_device_file_descriptor_to_VM"><span class="tocnumber">2.3.6</span> <span class="toctext">QEMU passes mdev device file descriptor to VM</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-31"><a href="Mediated_Device_Internals.html#Instruction_Execution"><span class="tocnumber">2.4</span> <span class="toctext">Instruction Execution</span></a> +<ul> +<li class="toclevel-3 tocsection-32"><a href="Mediated_Device_Internals.html#IRQ_remapping"><span class="tocnumber">2.4.1</span> <span class="toctext">IRQ remapping</span></a></li> +<li class="toclevel-3 tocsection-33"><a href="Mediated_Device_Internals.html#Interrupt_Injection"><span class="tocnumber">2.4.2</span> <span class="toctext">Interrupt Injection</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-34"><a href="Mediated_Device_Internals.html#Memory_Management"><span class="tocnumber">2.5</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-35"><a href="Mediated_Device_Internals.html#Region_Passthrough"><span class="tocnumber">2.5.1</span> <span class="toctext">Region Passthrough</span></a> +<ul> +<li class="toclevel-4 tocsection-36"><a href="Mediated_Device_Internals.html#Emulated_Regions"><span class="tocnumber">2.5.1.1</span> <span class="toctext">Emulated Regions</span></a></li> +<li class="toclevel-4 tocsection-37"><a href="Mediated_Device_Internals.html#Passthrough_Regions"><span class="tocnumber">2.5.1.2</span> <span class="toctext">Passthrough Regions</span></a></li> +<li class="toclevel-4 tocsection-38"><a href="Mediated_Device_Internals.html#Region_Access"><span class="tocnumber">2.5.1.3</span> <span class="toctext">Region Access</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-39"><a href="Mediated_Device_Internals.html#EPT_Page_Violations"><span class="tocnumber">2.5.2</span> <span class="toctext">EPT Page Violations</span></a></li> +<li class="toclevel-3 tocsection-40"><a href="Mediated_Device_Internals.html#Mediated_DMA_Translations"><span class="tocnumber">2.5.3</span> <span class="toctext">Mediated DMA Translations</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-41"><a href="Mediated_Device_Internals.html#Scheduling"><span class="tocnumber">2.6</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-42"><a href="Mediated_Device_Internals.html#Kernel_API"><span class="tocnumber">2.7</span> <span class="toctext">Kernel API</span></a></li> +<li class="toclevel-2 tocsection-43"><a href="Mediated_Device_Internals.html#Sample_Code"><span class="tocnumber">2.8</span> <span class="toctext">Sample Code</span></a> +<ul> +<li class="toclevel-3 tocsection-44"><a href="Mediated_Device_Internals.html#Compilation"><span class="tocnumber">2.8.1</span> <span class="toctext">Compilation</span></a></li> +<li class="toclevel-3 tocsection-45"><a href="Mediated_Device_Internals.html#Loading_Kernel_Modules"><span class="tocnumber">2.8.2</span> <span class="toctext">Loading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-46"><a href="Mediated_Device_Internals.html#Unloading_Kernel_Modules"><span class="tocnumber">2.8.3</span> <span class="toctext">Unloading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-47"><a href="Mediated_Device_Internals.html#Additional_Documentation"><span class="tocnumber">2.8.4</span> <span class="toctext">Additional Documentation</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-48"><a href="Mediated_Device_Internals.html#Mdev_Mode_Requirements"><span class="tocnumber">2.9</span> <span class="toctext">Mdev Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-49"><a href="Mediated_Device_Internals.html#SR-IOV_Mode"><span class="tocnumber">3</span> <span class="toctext">SR-IOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-50"><a href="Mediated_Device_Internals.html#Knowledge_Resources_Used_3"><span class="tocnumber">3.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-51"><a href="Mediated_Device_Internals.html#Instruction_Execution_2"><span class="tocnumber">3.2</span> <span class="toctext">Instruction Execution</span></a></li> +<li class="toclevel-2 tocsection-52"><a href="Mediated_Device_Internals.html#Memory_Management_2"><span class="tocnumber">3.3</span> <span class="toctext">Memory Management</span></a></li> +<li class="toclevel-2 tocsection-53"><a href="Mediated_Device_Internals.html#Scheduling_2"><span class="tocnumber">3.4</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-54"><a href="Mediated_Device_Internals.html#SR-IOV_Mode_Requirements"><span class="tocnumber">3.5</span> <span class="toctext">SR-IOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-55"><a href="Mediated_Device_Internals.html#SIOV_Mode"><span class="tocnumber">4</span> <span class="toctext">SIOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-56"><a href="Mediated_Device_Internals.html#Knowledge_Resources_Used_4"><span class="tocnumber">4.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-57"><a href="Mediated_Device_Internals.html#Memory_Management_3"><span class="tocnumber">4.2</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-58"><a href="Mediated_Device_Internals.html#IOMMU_Aware_Mediated_Device"><span class="tocnumber">4.2.1</span> <span class="toctext">IOMMU Aware Mediated Device</span></a></li> +<li class="toclevel-3 tocsection-59"><a href="Mediated_Device_Internals.html#Shared_Hardware_Workqueues"><span class="tocnumber">4.2.2</span> <span class="toctext">Shared Hardware Workqueues</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-60"><a href="Mediated_Device_Internals.html#SIOV_Mode_Requirements"><span class="tocnumber">4.3</span> <span class="toctext">SIOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-61"><a href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)"><span class="tocnumber">5</span> <span class="toctext">References (Talks & Reading Material)</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="All_Modes">All Modes</span></h2> +<p>This section will cover concepts which apply both to <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a>, <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> & <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SIOV_Mode">SIOV Mode</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Alex Williamson. +</p><p>See references 2, 14, & 22 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Binding_VFIO_devices">Binding VFIO devices</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Vfio-pci_driver_bindings.png.html" class="image"><img alt="" src="../images/thumb/9/9e/Vfio-pci_driver_bindings.png/300px-Vfio-pci_driver_bindings.png" decoding="async" width="300" height="218" class="thumbimage" srcset="../images/thumb/9/9e/Vfio-pci_driver_bindings.png/450px-Vfio-pci_driver_bindings.png 1.5x, ../images/thumb/9/9e/Vfio-pci_driver_bindings.png/600px-Vfio-pci_driver_bindings.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Vfio-pci_driver_bindings.png.html" class="internal" title="Enlarge"></a></div><b>Figure 1:</b> VFIO group nodes are unit of ownership that VFIO uses. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:IOCTL_set_VFIO_container.png.html" class="image"><img alt="" src="../images/thumb/3/33/IOCTL_set_VFIO_container.png/300px-IOCTL_set_VFIO_container.png" decoding="async" width="300" height="242" class="thumbimage" srcset="../images/thumb/3/33/IOCTL_set_VFIO_container.png/450px-IOCTL_set_VFIO_container.png 1.5x, ../images/thumb/3/33/IOCTL_set_VFIO_container.png/600px-IOCTL_set_VFIO_container.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:IOCTL_set_VFIO_container.png.html" class="internal" title="Enlarge"></a></div><b>Figure 2:</b> IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="image"><img alt="" src="../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/300px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png" decoding="async" width="300" height="214" class="thumbimage" srcset="../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/450px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 1.5x, ../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/600px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="internal" title="Enlarge"></a></div><b>Figure 3:</b> Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="image"><img alt="" src="../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/300px-Ioctl-VFIO_GROUP_GET_FD.png" decoding="async" width="300" height="204" class="thumbimage" srcset="../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/450px-Ioctl-VFIO_GROUP_GET_FD.png 1.5x, ../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/600px-Ioctl-VFIO_GROUP_GET_FD.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="internal" title="Enlarge"></a></div><b>Figure 4:</b> Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 1:</b> Binding devices to the vfio-pci driver results in VFIO group nodes. +</p><p>Opening the file "/dev/vfio/vfio" creates a VFIO Container. +</p><p><b>Figure 2:</b> The interrupt routine <b><code>IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER)</code></b> places the VFIO group inside the VFIO container. +</p> +<h3><span class="mw-headline" id="Programming_the_IOMMU">Programming the IOMMU</span></h3> +<p>When this has been done <b><code>IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU)</code></b> can then be used to set an IOMMU type for the container which places it in a user interactable state. +</p><p>Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +</p> +<h3><span class="mw-headline" id="VFIO_Memory_Mapped_IO">VFIO Memory Mapped IO</span></h3> +<p><b>Figure 3:</b> Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using <b><code>IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP)</code></b> for map/pin and <b><code>IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP)</code></b> for unmap/unpin. +</p> +<h3><span class="mw-headline" id="Getting_the_VFIO_Group_File_Descriptor">Getting the VFIO Group File Descriptor</span></h3> +<p><b>Figure 4:</b> Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +</p> +<h3><span class="mw-headline" id="VFIO_device_file_descriptor">VFIO device file descriptor</span></h3> +<p>VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +</p><p>In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +</p> +<table class="wikitable"> +<caption>BAR regions in a VGA PCI device. +</caption> +<tbody><tr> +<th>00:00.0 VGA compatible controller +</th></tr> +<tr> +<td>Region 0 Bar0 (Config Space) starts at offset 0 +</td></tr> +<tr> +<td>Region 1 Bar1 (MSI - Message Signaled Interrupts) +</td></tr> +<tr> +<td>Region 2 Bar2 (MSIX) +</td></tr> +<tr> +<td>Region 3 Bar3 +</td></tr> +<tr> +<td>Region 4 Bar4 +</td></tr> +<tr> +<td>Region 5 Bar5 (IO port space) +</td></tr> +<tr> +<td>Expansion ROM +</td></tr></tbody></table> +<p>Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +</p> +<table class="wikitable"> +<caption>VFIO representation of PCI BAR regions offsets. +</caption> +<tbody><tr> +<th colspan="5"><- File Offset -> +</th></tr> +<tr> +<th>0 -> A +</th> +<th>A -> (A+B) +</th> +<th>(A+B) -> (A+B+C) +</th> +<th>(A+B+C) -> (A+B+C+D) +</th> +<th>... +</th></tr> +<tr> +<td>Region 0 (size A) +</td> +<td>Region 1 (size B) +</td> +<td>Region 2 (size C) +</td> +<td>Region 3 (size D) +</td> +<td>... +</td></tr></tbody></table> +<h3><span class="mw-headline" id="VFIO_Interrupts">VFIO Interrupts</span></h3> +<p>Guests communicate with the host via VFIO Interrupt Requests (<a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt_request_(PC_architecture)">IRQs</a>). These are sent via an irqfd (IRQ <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">File Descriptor</a>). Similarly, the host receives these interrupts via <a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> (Event File Descriptor). The resulting data can be returned via a <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callback</a>. +</p> +<h4><span class="mw-headline" id="IRQs">IRQs</span></h4> +<p>Device properties discovered via interrupt (IOCTL). +</p> +<h5><span class="mw-headline" id="Get_Device_Info">Get Device Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_device_info +</td></tr> +<tr> +<td rowspan="7"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="3"> +</td> +<td>VFIO_DEVICE_FLAGS_PCI +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_PLATFORM +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_RESET +</td></tr> +<tr> +<td>num_irqs +</td> +<td> +</td></tr> +<tr> +<td>num_regions +</td> +<td> +</td></tr></tbody></table> +<p>The IRQ <b><code>VFIO_DEVICE_GET_INFO</code></b> can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L194">here (vfio.h)</a></b>. +</p><p><b>Sample mdev code</b> to service this request can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L470">here</a></b>, and <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L522">here</a></b>. +</p> +<h5><span class="mw-headline" id="Get_Region_Info">Get Region Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_REGION_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_region_info +</td></tr> +<tr> +<td rowspan="10"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>cap_offset +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_REGION_INFO_FLAG_CAPS +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_MMAP +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_READ +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_WRITE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>offset +</td> +<td> +</td></tr> +<tr> +<td>size +</td> +<td> +</td></tr></tbody></table> +<p>Once the interrupt user knows the number of regions within a VFIO device they can use IRQ <b><code>VFIO_DEVICE_GET_REGION_INFO</code></b> to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +</p><p>The upstream API can be read <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L240"><b>here (vfio.h)</b></a>. +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L425"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L545"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Get_IRQ_Info">Get IRQ Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_IRQ_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_info +</td></tr> +<tr> +<td rowspan="8"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_IRQ_INFO_AUTOMASKED +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_MASKABLE +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_NORESIZE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_GET_IRQ_INFO</b></code> is used to retrieve information about a device IRQ. +</p><p><b><code>VFIO_IRQ_INFO_AUTOMASKED</code></b> is used to mask interrupts when they occur to protect the host. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L480">here (vfio.h)</a></b> +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L463"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L570"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Set_IRQs">Set IRQs</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_SET_IRQS +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_set +</td></tr> +<tr> +<td rowspan="12"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>data[] +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="6"> +</td> +<td>VFIO_IRQ_SET_ACTION_MASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_TRIGGER +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_UNMASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_BOOL +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_NONE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>start +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_SET_IRQS</b></code> is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L524">here (vfio.h)</a></b>. +</p> +<h3><span id="Device_Decomposure.2FRecomposure"></span><span class="mw-headline" id="Device_Decomposure/Recomposure">Device Decomposure/Recomposure</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="image"><img alt="Figure 5: Device Decomposure and Recomposure via VFIO." src="../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/300px-Device_Decomposure_and_Recomposure_via_VFIO.png" decoding="async" width="300" height="147" class="thumbimage" srcset="../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/450px-Device_Decomposure_and_Recomposure_via_VFIO.png 1.5x, ../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/600px-Device_Decomposure_and_Recomposure_via_VFIO.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="internal" title="Enlarge"></a></div><b>Figure 5:</b> Device Decomposure and Recomposure via VFIO. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 5:</b> Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +</p> +<h3><span id="Memory_Management_Unit_.28MMU.29"></span><span class="mw-headline" id="Memory_Management_Unit_(MMU)">Memory Management Unit (MMU)</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 275px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_6-_MMU_-_GMMU_IOVA_translation-isolation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 6:</b> MMU - GMMU IOVA translation/isolation.</div></div></div> +<p><b>Figure 6:</b> This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +</p> +<h4><span id="MMIO_Isolation_.28Platform_MMU.29"></span><span class="mw-headline" id="MMIO_Isolation_(Platform_MMU)">MMIO Isolation (Platform MMU)</span></h4> +<p>The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Random-access_memory">Random Access Memory (RAM)</a>. MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +</p> +<h4><span id="VRAM_Isolation_.28GPU_GMMU.29"></span><span class="mw-headline" id="VRAM_Isolation_(GPU_GMMU)">VRAM Isolation (GPU GMMU)</span></h4> +<p>The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard <a href="https://en.wikipedia.org/wiki/Video_random_access_memory" class="extiw" title="wikipedia:Video random access memory">Video Random Access Memory (VRAM)</a>. Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +</p> +<h4><span id="Platform_MMIO_.3C-.3E_GPU_Shadow_Pages"></span><span class="mw-headline" id="Platform_MMIO_<->_GPU_Shadow_Pages">Platform MMIO <-> GPU Shadow Pages</span></h4> +<p>In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="image"><img alt="Figure 7: A depiction of region overlays within a VFIO file descriptor." src="../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/300px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png" decoding="async" width="300" height="268" class="thumbimage" srcset="../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/450px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 1.5x, ../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/600px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 7:</b> A depiction of region overlays within a VFIO file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span id="VFIO_Quirks_.28region_traps.29"></span><span class="mw-headline" id="VFIO_Quirks_(region_traps)">VFIO Quirks (region traps)</span></h3> +<p><b>Figure 7:</b> Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="image"><img alt="Peer-to-Peer DMA Isolation under IOMMU" src="../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/300px-Screen_Shot_2022-05-06_at_10.46.59_AM.png" decoding="async" width="300" height="224" class="thumbimage" srcset="../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/450px-Screen_Shot_2022-05-06_at_10.46.59_AM.png 1.5x, ../images/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="internal" title="Enlarge"></a></div><b>Figure 8:</b> Peer-to-Peer DMA Isolation under IOMMU. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span class="mw-headline" id="Known_IOMMU_Issues">Known IOMMU Issues</span></h3> +<p><b>DMA Aliasing</b> +</p> +<ul><li>Not all devices generate unique IDs.</li> +<li>Not all devices generate IDs they should.<br /></li></ul> +<p><b>DMA Isolation</b> +</p> +<ul><li><b>Figure 8:</b> Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.</li></ul> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="image"><img alt="Figure 0: Approches to GPU Virtualization." src="../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/300px-Figure_0-_Approches_to_GPU_Virtualization..png" decoding="async" width="300" height="153" class="thumbimage" srcset="../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/450px-Figure_0-_Approches_to_GPU_Virtualization..png 1.5x, ../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/600px-Figure_0-_Approches_to_GPU_Virtualization..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="internal" title="Enlarge"></a></div><b>Figure 0:</b> Approaches to GPU Virtualization. See slides from: <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)">[61]</a></div></div></div> +<h2><span class="mw-headline" id="Mdev_Mode">Mdev Mode</span></h2> +<p><b>Mdev Mode (VFIO Mediated Device)</b> is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_2">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +</p><p>See references 1, 7, 8, 17, 18, 19, 70 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Mediated_Core">Mediated Core</span></h3> +<p>The mediated device framework made 3 major changes to the VFIO driver. +</p> +<ul><li><b>1: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_core.c">Mediated core module (new)</a></b> <br /> -Mediated bus driver, create mediated device. <br /> -Physical device interface for vendor callbacks. <br /> -Generic Mediated device management user interface (sysfs).</li> +<li><b>2: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_driver.c">Mediated device module (new)</a></b> <br /> -Manage created mediated device, fully compatible with VFIO user API (UAPI).</li> +<li><b>3: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/vfio_iommu_type1.c">VFIO IOMMU driver (enhancement)</a></b> <br /> -VFIO IOMMU API Type1 compatible, easy to extend to non-Type1.</li></ul> +<p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg03922.html"><b>lists.gnu.org Qemu-devel</b> mailing list archive</a>. +</p> +<h3><span class="mw-headline" id="Device_Initialization">Device Initialization</span></h3> +<p>This section will deal with how an Mdev driver is initialized. +</p><p><b>Sample mdev code</b> for device initialization can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L229">here</a></b>. +</p> +<h4><span class="mw-headline" id="Registering_VFIO_MDEV_as_a_driver">Registering VFIO MDEV as a driver</span></h4> +<p>VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +</p> +<h4><span class="mw-headline" id="Registering_PCIE_Device_with_the_Mediated_Core">Registering PCIE Device with the Mediated Core</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Mdev-gpu.png.html" class="image"><img alt="Registering the mediated device." src="../images/thumb/7/75/Mdev-gpu.png/300px-Mdev-gpu.png" decoding="async" width="300" height="208" class="thumbimage" srcset="../images/thumb/7/75/Mdev-gpu.png/450px-Mdev-gpu.png 1.5x, ../images/thumb/7/75/Mdev-gpu.png/600px-Mdev-gpu.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Mdev-gpu.png.html" class="internal" title="Enlarge"></a></div><b>Figure 9:</b> Registering the mediated device. This step may be accomplished via the vendor driver or via <a rel="nofollow" class="external text" href="">GVM/Mdev-GPU</a> for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.</div></div></div> +<p><b>Figure 9:</b> The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span id="Registering_Mediated_Callbacks_.28CBs.29"></span><span class="mw-headline" id="Registering_Mediated_Callbacks_(CBs)">Registering Mediated Callbacks (CBs)</span></h4> +<p><b>Figure 9:</b> The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span class="mw-headline" id="Creating_a_Mediated_Device_via_mdev-sysfsdev_API">Creating a Mediated Device via mdev-sysfsdev API</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="image"><img alt="" src="../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/300px-Echoing_a_UUID_into_the_sysfsdev_API.png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/450px-Echoing_a_UUID_into_the_sysfsdev_API.png 1.5x, ../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/600px-Echoing_a_UUID_into_the_sysfsdev_API.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="internal" title="Enlarge"></a></div><b>Figure 10:</b> Echoing a UUID into the mdev-sysfsdev API. This functionality is included in <a rel="nofollow" class="external text" href="https://github.com/mdevctl/mdevctl">mdevctl</a> and in <a rel="nofollow" class="external text" href=""></a>. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 10:</b> The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="image"><img alt="Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor." src="../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/300px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png" decoding="async" width="300" height="231" class="thumbimage" srcset="../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/450px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 1.5x, ../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/600px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 11:</b> QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<h4><span class="mw-headline" id="QEMU_adds_VFIO_device_to_IOMMU_container-group">QEMU adds VFIO device to IOMMU container-group</span></h4> +<p><b>Figure 11:</b> When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +</p> +<h4><span class="mw-headline" id="QEMU_passes_mdev_device_file_descriptor_to_VM">QEMU passes mdev device file descriptor to VM</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="image"><img alt="Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine." src="../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/300px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png" decoding="async" width="300" height="234" class="thumbimage" srcset="../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/450px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 1.5x, ../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/600px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="internal" title="Enlarge"></a></div><b>Figure 12:</b> QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 12:</b> Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +</p> +<h3><span class="mw-headline" id="Instruction_Execution">Instruction Execution</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioeventfd-and-irqfd.png.html" class="image"><img alt="" src="../images/thumb/a/aa/Ioeventfd-and-irqfd.png/300px-Ioeventfd-and-irqfd.png" decoding="async" width="300" height="215" class="thumbimage" srcset="../images/thumb/a/aa/Ioeventfd-and-irqfd.png/450px-Ioeventfd-and-irqfd.png 1.5x, ../images/thumb/a/aa/Ioeventfd-and-irqfd.png/600px-Ioeventfd-and-irqfd.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioeventfd-and-irqfd.png.html" class="internal" title="Enlarge"></a></div><b>Figure 13:</b> A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From <a rel="nofollow" class="external text" href="http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">blog.allenx</a></div></div></div> +<p><b>Figure 13:</b> Mdev Mode moves instruction information across a virtual function (VF) device using <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Remote_procedure_call">Remote Procedure Calls</a> generally by way of <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt">software interrupt</a> (<a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">Interrupt Request File Descriptor (irqfd)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">IO Event File Descriptor (ioeventfd)</a>. +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +</p> +<h4><span class="mw-headline" id="IRQ_remapping">IRQ remapping</span></h4> +<p>Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +</p> +<h4><span class="mw-headline" id="Interrupt_Injection">Interrupt Injection</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p> +<h3><span class="mw-headline" id="Memory_Management">Memory Management</span></h3> +<p>Mdev memory management is handled by vendor driver software. +</p> +<h4><span class="mw-headline" id="Region_Passthrough">Region Passthrough</span></h4> +<p>Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +</p> +<h5><span class="mw-headline" id="Emulated_Regions">Emulated Regions</span></h5> +<p>Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L112">in this sample code</a>. +</p> +<h5><span class="mw-headline" id="Passthrough_Regions">Passthrough Regions</span></h5> +<p>Passthrough memory regions use direct communication requiring no VM-exit (fast). +</p> +<h5><span class="mw-headline" id="Region_Access">Region Access</span></h5> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="image"><img alt="Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs" src="../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/300px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png" decoding="async" width="300" height="236" class="thumbimage" srcset="../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/450px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 1.5x, ../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/600px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="internal" title="Enlarge"></a></div><b>Figure 14:</b> QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 14:</b> QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 238px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="./File:Guest_driver_accessing_Mdev_MMIO_space_backed_by_mdev_file_descriptor_triggers_EPT_violation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 15:</b> Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 15:</b> The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="image"><img alt="Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver." src="../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/300px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/450px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 1.5x, ../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/600px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="internal" title="Enlarge"></a></div><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="image"><img alt="Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor." src="../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/300px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/450px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 1.5x, ../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/600px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 17:</b> QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 17:</b> QEMU convert request from KVM to R/W access to Mdev file descriptor. +</p> +<h4><span class="mw-headline" id="EPT_Page_Violations">EPT Page Violations</span></h4> +<p>Guest <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Memory-mapped_I/O">Memory Mapped IO (MMIO)</a> trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">Mdev File Descriptor (FD)</a>. Reads and writes are then handled by the host GPU device driver via mediated <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callbacks (CBs)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO-mdev</a>. +</p> +<h4><span class="mw-headline" id="Mediated_DMA_Translations">Mediated DMA Translations</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p><p>Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +</p><p><b>Figure 18:</b> Memory regions get added by QEMU. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Memory_Regions_Added_by_QEMU.png.html" class="image"><img alt="Memory Regions Added by QEMU" src="../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/300px-Memory_Regions_Added_by_QEMU.png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/450px-Memory_Regions_Added_by_QEMU.png 1.5x, ../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/600px-Memory_Regions_Added_by_QEMU.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Memory_Regions_Added_by_QEMU.png.html" class="internal" title="Enlarge"></a></div><b>Figure 18:</b> Memory Regions Added by QEMU. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 19:</b> QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="image"><img alt="QEMU calls VFIO DMA MAP via Memory listener" src="../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/300px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/450px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 1.5x, ../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/600px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="internal" title="Enlarge"></a></div><b>Figure 19:</b> QEMU calls VFIO DMA MAP via Memory listener. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="image"><img alt="Type 1 IOMMU Tracks VA-GFN" src="../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/300px-Type_1_IOMMU_Tracks_VA-GFN.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/450px-Type_1_IOMMU_Tracks_VA-GFN.png 1.5x, ../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/600px-Type_1_IOMMU_Tracks_VA-GFN.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="internal" title="Enlarge"></a></div><b>Figure 20:</b> Type 1 IOMMU Tracks <VA, GFN>. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 20:</b> Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +</p> +<h3><span class="mw-headline" id="Scheduling">Scheduling</span></h3> +<p>Scheduling is handled by the host mdev driver. +</p> +<h3><span class="mw-headline" id="Kernel_API">Kernel API</span></h3> +<p>Kernel documentation used for implementing a VFIO Mediated Device may be found at <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/driver-api/vfio-mediated-device.html">kernel.org</a>. +</p> +<h3><span class="mw-headline" id="Sample_Code">Sample Code</span></h3> +<p>Sample code for various mdev implementations may be found below: +</p><p><b>Mediated Virtual PCI Display Host Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy.c">mdpy.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy-fb.c">mdpy-fb.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mbochs.c">mbochs.c</a>.</li></ol> +<p><b>Serial PCI Port-based Mediated Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mtty.c">mtty.c</a>.</li></ol> +<h6><span class="mw-headline" id="Compilation">Compilation</span></h6> +<p>To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +</p><p><code>make</code> +</p><p>When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +</p> +<h6><span class="mw-headline" id="Loading_Kernel_Modules">Loading Kernel Modules</span></h6> +<p>Now that you have compiled the kernel modules you may load them via the insmod command. +</p><p>For example to load the <b>mtty.ko</b> module run the following command from within the directory where you built the modules: +</p><p><code>insmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Unloading_Kernel_Modules">Unloading Kernel Modules</span></h6> +<p>To unload any of the kernel modules you may make use of the rmmod command. +</p><p>For example to unload the <b>mtty.ko</b> module run the following command: +</p><p><code>rmmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Additional_Documentation">Additional Documentation</span></h6> +<p>An additional guide explaining how to make use of the mtty.c sample code may be found at <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294#n308">line 308</a> of the kernel.org VFIO Mediated Device documentation. +</p> +<h3><span class="mw-headline" id="Mdev_Mode_Requirements">Mdev Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Software HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SR-IOV_Mode">SR-IOV Mode</span></h2> +<p><b>SR-IOV Mode (Single Root I/O Virtualization)</b> involves hardware assisted virtualization on I/O peripherals. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_3">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +</p><p>See reference 6 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Instruction_Execution_2">Instruction Execution</span></h3> +<p>SR-IOV communicates instructions from a virtual function (VF) directly to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/PCI_configuration_space">PCI BAR</a>. +</p> +<h3><span class="mw-headline" id="Memory_Management_2">Memory Management</span></h3> +<p>Guests are presenting with passthrough memory regions by the device firmware. +</p> +<h3><span class="mw-headline" id="Scheduling_2">Scheduling</span></h3> +<p>Scheduling may be handled by the host mdev driver and/or the device firmware. +</p> +<h3><span class="mw-headline" id="SR-IOV_Mode_Requirements">SR-IOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SR-IOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SIOV_Mode">SIOV Mode</span></h2> +<p><b>SIOV (Scalable I/O Virtualization)</b> involves the combination of concepts form both <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> and <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a> as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +</p><p><b>Revision 1.0 of the SIOV specification</b> can be read on the <a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Open Compute Project website</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_4">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +</p><p>See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Memory_Management_3">Memory Management</span></h3> +<p>Enhancements to <a rel="nofollow" class="external text" href="https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/002/intel-virtualization-technology-for-directed-i-o/">Intel VT-d</a> introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (<a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Memory_Management">mdev memory management</a>). This change is referred to as an IOMMU Aware Mediated Device. +</p> +<h4><span class="mw-headline" id="IOMMU_Aware_Mediated_Device">IOMMU Aware Mediated Device</span></h4> +<p>SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +</p><p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">mailing list archive on <b>lwn.net</b> under <b>(vfio/mdev: IOMMU aware mediated device)</b></a>. +</p> +<h4><span class="mw-headline" id="Shared_Hardware_Workqueues">Shared Hardware Workqueues</span></h4> +<p>SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +</p><p><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">According to <b>kernel.org</b></a>: <i>"In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function."</i> +</p> +<h3><span class="mw-headline" id="SIOV_Mode_Requirements">SIOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SIOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=Xs0TJU_sIPc">[2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede</a> - <a rel="nofollow" class="external text" href="https://www.linux-kvm.org/images/5/59/02x03-Neo_Jia_and_Kirti_Wankhede-vGPU_on_KVM-A_VFIO_based_Framework.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=WFkdTFTOTpA">[2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson</a> - <a rel="nofollow" class="external text" href="http://events17.linuxfoundation.org/sites/events/files/slides/An%20Introduction%20to%20PCI%20Device%20Assignment%20with%20VFIO%20-%20Williamson%20-%202016-08-30_0.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://events19.linuxfoundation.cn/wp-content/uploads/2017/11/Intel%C2%AE-Scalable-I_O-Virtualization_Kevin-Tian.pdf">[2017] Scalable I/O Virtualization by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=G6D-jaCs6sc">[2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu</a> - <a rel="nofollow" class="external text" href="https://static.sched.com/hosted_files/kvmforum2019/5e/Bring%20a%20scalable%20IOV%20capable%20device%20into%20Linux%20-%20KVM%202019.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Scalable I/O Virtualization Revision 1.0</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=_tB3EbFDcRQ">[2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue</a> - <a rel="nofollow" class="external text" href="https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Live-Migration-Support-for-GPU-with-SRIOV-Challenges-and-Solution-Zheng-Xiao-Alibaba-Cloud-Jerry-Jiang-Ken-Xue-AMD.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=UODxW1opfn0">[2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=DKYvQ3FdFeo">[2016] Qemu Graphics Update 2016 by Gerd Hoffmann</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a></li> +<li><a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/eventfd.c">root/virt/kvm/eventfd.c</a></li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">KVM: irqfd</a>)</li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">KVM: add ioeventfd support</a>)</li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220120223711/http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">KVM irqfd & ioeventfd</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio.rst">VFIO - Virtual Function I/O</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/vfio.c">root/virt/kvm/vfio.c</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO Mediated Devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">IOMMU Aware Mediated Device</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=95KSKrZM8oQ">Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=cHMLBcHplhk">[2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=KWRKx_uxUDI">[2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/auxiliary_bus.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294">Auxiliary Bus</a></li> +<li><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">Shared Virtual Addressing</a></li> +<li><a rel="nofollow" class="external text" href="https://vfio.blogspot.com/">vfio.blogspot.com</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/xengt.pdf">XenGT by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130721094438/http://labs.vmware.com/academic/publications/gpu-virtualization">VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman</a></li> +<li><a rel="nofollow" class="external text" href="https://pcisig.com/specifications/iov">PCI SIG I/O Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120108034526/http://sysweb.cs.toronto.edu/vmgl">VMGL by the University of Toronto Computer Science Department</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120518125815/http://www.nvidia.com/object/vgx-hypervisor.html">Kepler VGX Hypervisor</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090218010221/http://software.intel.com/en-us/articles/intel-virtualization-technology-for-directed-io-vt-d-enhancing-intel-platforms-for-efficient-virtualization-of-io-devices">Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/2001/0712/a/dma-interface.php3">DMA-Mapping.txt (Dynamic DMA Mapping)</a></li> +<li><a rel="nofollow" class="external text" href="https://events.static.linuxfound.org/slides/2011/linuxcon-japan/lcj2011_guangrong.pdf">KVM MMU Virtualization by Xiao Guangrong</a></li> +<li><a rel="nofollow" class="external text" href="https://wiki.osdev.org/PCI">OSDEV: PCI</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1">Down to the TLP: How PCI express devices talk (Part I)</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2">Down to the TLP: How PCI express devices talk (Part II)</a></li> +<li><a rel="nofollow" class="external text" href="https://projectacrn.github.io/latest/tutorials/sriov_virtualization.html">Intel ACRN: Enabling SR-IOV Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://docs.kernel.org/admin-guide/abi-testing.html#abi-file-testing-sysfs-bus-pci">Kernel.org sysfs-bus-pci</a></li> +<li><a rel="nofollow" class="external text" href="https://linux-kernel-labs.github.io/refs/heads/master/labs/memory_mapping.html">Linux Kernel Labs: Memory Mapping</a></li> +<li><a rel="nofollow" class="external text" href="https://rayanfam.com/topics/inside-windows-page-frame-number-part1/">Inside Windows Page Frame Number (PFN) - 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+</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Merged_Drivers rootpage-Merged_Drivers skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Merged Drivers</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Merged_Drivers.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Merged_Drivers.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>The following page will provide specifications and details on the current state of host DRM + VFIO-Mdev drivers in support of various vendors. +</p><p>In the context of this page the term <b>"Merged Driver"</b> refers to drivers which <i>allow simultaneous acceleration of the host using a device's PF (Physical Function) and acceleration of guests using one or more VFs (Virtual Functions) created using the same device</i>. +</p><p> +Merged functionality is currently supported for drivers which both make use of VFIO-Mdev and SR-IOV functionality depending on the vendor and driver implementation.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Merged_Drivers.html#Intel_i915"><span class="tocnumber">1</span> <span class="toctext">Intel i915</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Merged_Drivers.html#Known_Issues"><span class="tocnumber">1.1</span> <span class="toctext">Known Issues</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="Merged_Drivers.html#Resolved_Issues"><span class="tocnumber">1.2</span> <span class="toctext">Resolved Issues</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-4"><a href="Merged_Drivers.html#Nvidia"><span class="tocnumber">2</span> <span class="toctext">Nvidia</span></a> +<ul> +<li class="toclevel-2 tocsection-5"><a href="Merged_Drivers.html#Known_Issues_2"><span class="tocnumber">2.1</span> <span class="toctext">Known Issues</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Merged_Drivers.html#Resolved_Issues_2"><span class="tocnumber">2.2</span> <span class="toctext">Resolved Issues</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Merged_Drivers.html#Module_Configuration"><span class="tocnumber">2.3</span> <span class="toctext">Module Configuration</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-8"><a href="Merged_Drivers.html#AMDGPU"><span class="tocnumber">3</span> <span class="toctext">AMDGPU</span></a> +<ul> +<li class="toclevel-2 tocsection-9"><a href="Merged_Drivers.html#Known_Issues_3"><span class="tocnumber">3.1</span> <span class="toctext">Known Issues</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Intel_i915">Intel i915</span></h2> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Intel_GVT-g_Capabilities.png.html" class="image"><img alt="" src="../images/thumb/0/0b/Intel_GVT-g_Capabilities.png/300px-Intel_GVT-g_Capabilities.png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/0/0b/Intel_GVT-g_Capabilities.png/450px-Intel_GVT-g_Capabilities.png 1.5x, ../images/thumb/0/0b/Intel_GVT-g_Capabilities.png/600px-Intel_GVT-g_Capabilities.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Intel_GVT-g_Capabilities.png.html" class="internal" title="Enlarge"></a></div>Intel's slides mention the ability to accelerate up to '8 VMs plus DOM0'. Source: <a rel="nofollow" class="external free" href="https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf">https://01.org/sites/default/files/documentation/an_introduction_to_intel_gvt-g_for_external.pdf</a></div></div></div> +<p>Intel currently supports host DRM and VFIO-Mdev/SR-IOV functionality in it's <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/i915">current i915 driver sources (VFIO-Mdev/GVT-g)</a> and <a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/commit/41ef979f0894326c202473807a56b599a2f3d04e">upstreaming i915 driver sources (VFIO-Mdev/SR-IOV)</a>. +</p> +<h3><span class="mw-headline" id="Known_Issues">Known Issues</span></h3> +<ol><li>SR-IOV functionality is undocumented in the <a rel="nofollow" class="external text" href="https://01.org/linuxgraphics/gfx-docs/drm/gpu/i915.html">i915 driver API documentation</a>. <br /> <i><b>Confirmed affected versions:</b> *</i><div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html" class="image"><img alt="" src="../images/thumb/3/3d/Intel_i915_Host_DRM_+_VFIO-Mdev..png/300px-Intel_i915_Host_DRM_+_VFIO-Mdev..png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/3/3d/Intel_i915_Host_DRM_+_VFIO-Mdev..png/450px-Intel_i915_Host_DRM_+_VFIO-Mdev..png 1.5x, ../images/thumb/3/3d/Intel_i915_Host_DRM_+_VFIO-Mdev..png/600px-Intel_i915_Host_DRM_+_VFIO-Mdev..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Intel_i915_Host_DRM_+_VFIO-Mdev..png.html" class="internal" title="Enlarge"></a></div>A diagram depicting i915's shared host + VFIO-Mdev driver model.</div></div></div></li></ol> +<h3><span class="mw-headline" id="Resolved_Issues">Resolved Issues</span></h3> +<ol><li>Multiplexing functionality requires use modified KVM and Xen hypervisors (<a rel="nofollow" class="external text" href="https://01.org/sites/default/files/documentation/01x08b-kvmgt-a.pdf">KVMGT</a>/<a rel="nofollow" class="external text" href="https://wiki.xenproject.org/wiki/XenGT">XenGT</a>). <i><b><br />Confirmed affected versions:</b> <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/i915">current i915 driver sources (GVT-g)</a><b><br />Fixed in:</b> <a rel="nofollow" class="external text" href="https://github.com/intel/linux-intel-lts/commit/41ef979f0894326c202473807a56b599a2f3d04e">upstreaming i915 driver sources (SR-IOV)</a></i></li></ol> +<h2><span class="mw-headline" id="Nvidia">Nvidia</span></h2> +<h3><span class="mw-headline" id="Known_Issues_2">Known Issues</span></h3> +<ol><li>Power management on laptops running mediated graphics functionality may causes graphical errors when not plugged in to AC power. <br /><i><b>Confirmed affected versions:</b> 460.32.01, 460.73.04</i> <br /><i><b>Possible mitigation:</b></i> <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/20220425092615.10133-1-abhsahu@nvidia.com/">lore.kernel.org: <i>"vfio/pci: Change the PF power state to D0 before enabling VFs"</i></a></li> +<li>VFIO-vmalloc errors may occur as a result of page collisions between host & guest on GPUs with smaller VRAM frame buffer sizes. <br /><i><b>Confirmed affected versions:</b> 460.32.01, 460.73.04</i></li> +<li>Mdev service daemons may crash or load incorrectly requiring a service restart or reboot during host runtime.<br /><i><b>Confirmed affected versions:</b> 460.32.01, 460.73.04, 510.xx.xx</i></li> +<li>Guest drivers fail to initialize correctly when VFIO-Mdev devices are mixed with some VFIO passthrough'd USB hubs.<br /><i><b>Confirmed affected versions:</b> 460.73.01</i></li></ol> +<h3><span class="mw-headline" id="Resolved_Issues_2">Resolved Issues</span></h3> +<ol><li>Upon executing <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Virtual_IO_Internals#QEMU_adds_VFIO_device_to_IOMMU_container-group">QEMU mdev device initialization</a> for a second Mdev an IOMMU group binding error occurs in QEMU preventing the device from being brought up.<br /><i><b>Confirmed affected versions:</b> 460.32.01, 460.73.04<br /><b>Fixed in:</b> 510.xx.xx</i></li></ol> +<h3><span class="mw-headline" id="Module_Configuration">Module Configuration</span></h3> +<p>Depending on your use-case the use of some additional parameters when booting the system may be helpful. +</p><p>Here is a list of some parameters which may be used when loading the module via GRUB or Systemd-boot. +</p> +<table class="wikitable"> +<caption>Module Parameters +</caption> +<tbody><tr> +<th>Parameter +</th> +<th>Description +</th> +<th>Side-Effects +</th></tr> +<tr> +<td>cudahost=1 +</td> +<td>Allows use of CUDA on the host system. +</td> +<td>Windows guests may fail. +</td></tr> +<tr> +<td>nvidia.vgpukvm=0 +</td> +<td>Disables GPU virtualization on the host. +</td> +<td> +</td></tr></tbody></table> +<h2><span class="mw-headline" id="AMDGPU">AMDGPU</span></h2> +<p>At this time AMDGPU does not currently support VFIO-Mdev functionality. It may be possible to incorporate <a rel="nofollow" class="external text" href="https://open-iov.org/index.php/Mediated_Device_Internals#Mdev_Mode">Mdev Mode mediated device support</a> similar to those functions in nvidia.ko and i915.ko in the <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/amd/amdgpu">Linux kernel's AMDGPU driver sources</a> to produce a driver suitable for merged host+guest DRM for use with AMD GPU devices. +</p> +<h3><span class="mw-headline" id="Known_Issues_3">Known Issues</span></h3> +<ol><li>Host DRM does not work alongside guest VFIO-Mdev. <br /><i><b>Confirmed affected versions:</b> *</i></li> +<li>The amdgpu kernel module doesn't contain hooks for guest signalling via <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">irqfd</a> & <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">ioeventfd</a> used for VFIO-mdev callbacks. <br /><i><b>Confirmed affected versions:</b> *</i> <br /></li></ol> +<!-- +NewPP limit report +Cached time: 20260911155251 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.013 seconds +Real time usage: 0.014 seconds +Preprocessor visited node count: 42/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:30-0!canonical and timestamp 20260911155251 and revision id 23737. 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id="firstHeading" class="firstHeading" >OpenRM</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="OpenRM.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="OpenRM.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>OpenRM refers to the open sourcing of the NVIDIA kernel module for Linux, specifically the RM Core or the internal resource manager. +</p><p> +Through the open sourced code (<a rel="nofollow" class="external text" href="https://github.com/NVIDIA/open-gpu-kernel-modules">located here</a>) we have been able to deduce 7 top level APIs that are being exposed to the Linux developers.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="OpenRM.html#Interaction_With_OpenRM"><span class="tocnumber">1</span> <span class="toctext">Interaction With OpenRM</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="OpenRM.html#Alloc_(Client)"><span class="tocnumber">1.1</span> <span class="toctext">Alloc (Client)</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="OpenRM.html#Alloc_Memory_64"><span class="tocnumber">1.2</span> <span class="toctext">Alloc Memory 64</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="OpenRM.html#Control"><span class="tocnumber">1.3</span> <span class="toctext">Control</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="OpenRM.html#Dup_Object"><span class="tocnumber">1.4</span> <span class="toctext">Dup Object</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="OpenRM.html#Free"><span class="tocnumber">1.5</span> <span class="toctext">Free</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="OpenRM.html#Vid_Heap_Control"><span class="tocnumber">1.6</span> <span class="toctext">Vid Heap Control</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="OpenRM.html#Map_Memory"><span class="tocnumber">1.7</span> <span class="toctext">Map Memory</span></a></li> +<li class="toclevel-2 tocsection-9"><a href="OpenRM.html#Unmap_Memory"><span class="tocnumber">1.8</span> <span class="toctext">Unmap Memory</span></a></li> +<li class="toclevel-2 tocsection-10"><a href="OpenRM.html#Alloc_Context_DMA_2"><span class="tocnumber">1.9</span> <span class="toctext">Alloc Context DMA 2</span></a></li> +<li class="toclevel-2 tocsection-11"><a href="OpenRM.html#Map_Memory_DMA"><span class="tocnumber">1.10</span> <span class="toctext">Map Memory DMA</span></a></li> +<li class="toclevel-2 tocsection-12"><a href="OpenRM.html#Un-map_Memory_DMA"><span class="tocnumber">1.11</span> <span class="toctext">Un-map Memory DMA</span></a></li> +<li class="toclevel-2 tocsection-13"><a href="OpenRM.html#Bind_Context_DMA"><span class="tocnumber">1.12</span> <span class="toctext">Bind Context DMA</span></a></li> +<li class="toclevel-2 tocsection-14"><a href="OpenRM.html#Share"><span class="tocnumber">1.13</span> <span class="toctext">Share</span></a></li> +<li class="toclevel-2 tocsection-15"><a href="OpenRM.html#Add_VBlank_Callback"><span class="tocnumber">1.14</span> <span class="toctext">Add VBlank Callback</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-16"><a href="OpenRM.html#Engines"><span class="tocnumber">2</span> <span class="toctext">Engines</span></a> +<ul> +<li class="toclevel-2 tocsection-17"><a href="OpenRM.html#Table_of_Engines"><span class="tocnumber">2.1</span> <span class="toctext">Table of Engines</span></a></li> +</ul> +</li> +</ul> +</div> + +<h2><span class="mw-headline" id="Interaction_With_OpenRM">Interaction With OpenRM</span></h2> +<p>All of OpenRM is a high scale object oriented abstraction layer for the GPU, all resources are internally classes which have control definitions (methods) on how you can use them. These classes can also represent physical resources or engines. +</p> +<h3><span id="Alloc_.28Client.29"></span><span class="mw-headline" id="Alloc_(Client)">Alloc (Client)</span></h3> +<p>This is analogous to calling an object constructor in a higher level programming language, such as C#. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).</li> +<li>hObjectParent - Parent of the resource we are allocating.</li> +<li>hObjectNew - New object to allocate.</li> +<li>hClass - Class of the object we are dealing with.</li> +<li>pAllocParams - Pointer to values passed into the constructor call.</li> +<li>status - Status of the constructor call (did it succeed or fail)</li></ol> +<h3><span class="mw-headline" id="Alloc_Memory_64">Alloc Memory 64</span></h3> +<p>This creates a CPU's mapping to a resource. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hRoot - RM Client Id (given by the kernel module for an individual process that is interacting with the kernel module).</li> +<li>hObjectParent - Parent of the resource we create the CPU mapping to.</li> +<li>hObjectNew - Mapping object resource id.</li> +<li>hClass - Class of the mapped object.</li> +<li>flags - Flags to use on the mapped object.</li> +<li>pMemory - pointer for the memory to map.</li> +<li>pLimit - Edge of memory map.</li> +<li>status - Status of the constructor call.</li></ol> +<p>NOTE: Seems to be deprecated. +</p> +<h3><span class="mw-headline" id="Control">Control</span></h3> +<p>This is a control command which is analogous to calling a method on a class. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - RM Client Id.</li> +<li>hObject - Object id.</li> +<li>cmd - Method to call.</li> +<li>params - Parameters into this method.</li> +<li>paramsSize - Size of the params.</li> +<li>status - Status of the control call.</li></ol> +<p>NOTE: The control will overwrite the object we pass in over the params pointer. +</p> +<h3><span class="mw-headline" id="Dup_Object">Dup Object</span></h3> +<p>Duplicates the object, or clones the object, which is a deep copy. This procedure can be used across processes in order to produce shared memory. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - RM Client Id.</li> +<li>hParent - Parent of the object.</li> +<li>hObject - Object destination for duplicating.</li> +<li>hClientSrc - Client source id.</li> +<li>hObjectSrc - Object source.</li> +<li>flags - Flags to use.</li> +<li>status - Status of the duplication.</li></ol> +<h3><span class="mw-headline" id="Free">Free</span></h3> +<p>Frees an object from the object tree. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hRoot - Client Id.</li> +<li>hObjectParent - Parent of the object.</li> +<li>hObjectOld - Object to call the destructor on.</li> +<li>status - Status of the free.</li></ol> +<h3><span class="mw-headline" id="Vid_Heap_Control">Vid Heap Control</span></h3> +<p>TODO: Figure out what this does. +</p><p>NOTE: Seems to be deprecated. +</p> +<h3><span class="mw-headline" id="Map_Memory">Map Memory</span></h3> +<p>This seems to be the same as alloc memory but seems to be used more often. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hDevice - Device id.</li> +<li>hMemory - Memory resource.</li> +<li>offset - Offset of the memory.</li> +<li>length - Length of the memory.</li> +<li>pLinearAddress - Pointer for returned address.</li> +<li>status - Status of the map memory.</li> +<li>flags - Flags to use.</li></ol> +<h3><span class="mw-headline" id="Unmap_Memory">Unmap Memory</span></h3> +<p>This unmaps the CPU memory mapping from the resource. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hDevice - Device Id.</li> +<li>hMemory - Memory Id.</li> +<li>pLinearAddress - pointer to virtual address.</li> +<li>status - Status of the unmap command.</li> +<li>flags - Flags to use.</li></ol> +<h3><span class="mw-headline" id="Alloc_Context_DMA_2">Alloc Context DMA 2</span></h3> +<p>Allocates a context for DMA. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hObjectParent - Object parent.</li> +<li>hSubDevice - Sub device to allocate on.</li> +<li>hObjectNew - Context id.</li> +<li>hClass - Type of class.</li> +<li>flags - Flags to use.</li> +<li>selector - UNKNOWN.</li> +<li>hMemory - Handle for Memory resource to DMA map.</li> +<li>offset - Offset for the DMA mapping.</li> +<li>limit - Limit of the DMA map.</li> +<li>status - Status of the allocation.</li></ol> +<p>NOTE: Seems to be deprecated. +</p> +<h3><span class="mw-headline" id="Map_Memory_DMA">Map Memory DMA</span></h3> +<p>Map a region of memory for DMA access. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hDevice - Device Id.</li> +<li>hDma - DMA Id.</li> +<li>hMemory - Memory Id.</li> +<li>offset - Offset of the region.</li> +<li>limit - Limit of the region.</li> +<li>flags - flags to use.</li> +<li>dmaOffset - Offset of the mapping.</li> +<li>status - Status of the map Memory DMA.</li></ol> +<h3><span class="mw-headline" id="Un-map_Memory_DMA">Un-map Memory DMA</span></h3> +<p>Unmaps a region of memory for DMA access. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hDevice - Device Id.</li> +<li>hDma - DMA handle.</li> +<li>hMemory - Memory handle.</li> +<li>flags - Flags to use.</li> +<li>dmaOffset - DMA Offset to unmap.</li> +<li>status - Status of the unmap Memory DMA.</li></ol> +<h3><span class="mw-headline" id="Bind_Context_DMA">Bind Context DMA</span></h3> +<p>Binds a context for DMA interaction to a channel. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hChannel - Channel Id.</li> +<li>hCtxDma - Context for DMA Id.</li> +<li>status - Status of the bind context DMA.</li></ol> +<p>NOTE: Seems to be deprecated. +</p> +<h3><span class="mw-headline" id="Share">Share</span></h3> +<p>Sharing of a resource between multiple clients. +</p><p>TODO: Understand this sharing more. +</p><p>The data for this call requires the following components: +</p> +<ol><li>hClient - Client Id.</li> +<li>hObject - Resource Id.</li> +<li>sharePolicy - Share policy.</li> +<li>status - Status of sharing.</li></ol> +<h3><span class="mw-headline" id="Add_VBlank_Callback">Add VBlank Callback</span></h3> +<p>TODO: Figure out what this does. +</p><p>NOTE: Seems to be deprecated. +</p> +<h2><span class="mw-headline" id="Engines">Engines</span></h2> +<p>There are engines which internally act as classes inside the OpenRM driver. +</p><p>These classes have a few key components that make them unique. +</p> +<h3><span class="mw-headline" id="Table_of_Engines">Table of Engines</span></h3> +<table class="wikitable sortable mw-collapsible"> +<caption>Engines +</caption> +<tbody><tr> +<th>Engine +</th> +<th>Description +</th></tr> +<tr> +<td>Invalid +</td> +<td>Does not exist. +</td></tr> +<tr> +<td>Software +</td> +<td>Abstraction layer for software processes inside the OS Software. +</td></tr> +<tr> +<td>GPU +</td> +<td>Interaction layer with the GPU. +</td></tr> +<tr> +<td>Falcon +</td> +<td>Interaction with the Falcon on the GPU. +</td></tr> +<tr> +<td>Master Control +</td> +<td>Unknown. +</td></tr> +<tr> +<td>Kernel Master Control +</td> +<td>Interaction with the PMC.<a rel="nofollow" class="external autonumber" href="https://github.com/NVIDIA/open-gpu-kernel-modules/blob/d8f3bcff924776518f1e63286537c3cf365289ac/src/nvidia/generated/g_kernel_mc_nvoc.h">[1]</a> +</td></tr> +<tr> +<td>Private Ring +</td> +<td>Interaction with a private messaging ring. +</td></tr> +<tr> +<td>Software Interrupt +</td> +<td>Interaction with software interrupts. +</td></tr> +<tr> +<td>Memory System +</td> +<td>Interaction with the memory system. +</td></tr> +<tr> +<td>Kernel Memory System +</td> +<td>Interaction with the kernel memory system. +</td></tr> +<tr> +<td>Memory Manager +</td> +<td>Interaction with the memory management system. +</td></tr> +<tr> +<td>FBFlcn +</td> +<td>Interaction with the FBFlcn subsystem. +</td></tr> +<tr> +<td>TMR +</td> +<td>Interaction with the TMR on specific chips. +</td></tr> +<tr> +<td>DMA +</td> +<td>Interaction with a GPU's DMA access. +</td></tr> +<tr> +<td>Kernel FIFO +</td> +<td>First in First out queue in the GPU driver. +</td></tr> +<tr> +<td>FIFO +</td> +<td>Interaction with a generic FIFO. +</td></tr> +<tr> +<td>OS +</td> +<td>Interaction with the OS. +</td></tr> +<tr> +<td>BUS +</td> +<td>PCI Bus interaction +</td></tr> +<tr> +<td>Kernel BUS +</td> +<td>Internal module BUS. +</td></tr> +<tr> +<td>INFOROM +</td> +<td>Interaction with the INFOROM Region on the GPU. +</td></tr> +<tr> +<td>PERF +</td> +<td>Unknown. +</td></tr> +<tr> +<td>Kernel PERF +</td> +<td>Unknown. +</td></tr> +<tr> +<td>BIF +</td> +<td>Unknown. +</td></tr> +<tr> +<td>Kernel BIF +</td> +<td>Unknown. +</td></tr> +<tr> +<td>SF +</td> +<td>Unknown. +</td></tr> +<tr> +<td>GPIO +</td> +<td>Interaction with GPIO. +</td></tr> +<tr> +<td>CLK +</td> +<td>Clock manager system. +</td></tr> +<tr> +<td>Kernel Display +</td> +<td>Kernel Display system. +</td></tr> +<tr> +<td>DISP +</td> +<td>Display system. +</td></tr> +<tr> +<td>DPU +</td> +<td>Data Processing Unit. +</td></tr> +<tr> +<td> +</td> +<td> +</td></tr> +<tr> +<td> +</td> +<td> +</td></tr></tbody></table> +<!-- +NewPP limit report +Cached time: 20260911155536 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.019 seconds +Real time usage: 0.020 seconds +Preprocessor visited node count: 51/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:40-0!canonical and timestamp 20260911155536 and revision id 23739. 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rootpage-Special_Contributions_Arthur skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + <div id="mw-indicator-mw-helplink" class="mw-indicator"><a href="https://www.mediawiki.org/wiki/Special:MyLanguage/Help:User_contributions" target="_blank" class="mw-helplink">Help</a></div> + </div> + <h1 id="firstHeading" class="firstHeading" >User contributions for Arthur</h1> + <div id="bodyContent" class="vector-body"> + + <div id="contentSub"><div class="mw-contributions-user-tools">For <a href="../../index.php%3Ftitle=User:Arthur&action=edit&redlink=1.html" class="new" title="User:Arthur (page does not exist)">Arthur</a> <span class="mw-changeslist-links"><span><a href="../../index.php%3Ftitle=User_talk:Arthur&action=edit&redlink=1.html" class="new" title="User talk:Arthur (page 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class='oo-ui-inputWidget-input' /><span aria-disabled='false' class='oo-ui-checkboxInputWidget-checkIcon oo-ui-widget oo-ui-widget-enabled oo-ui-iconElement-icon oo-ui-icon-check oo-ui-iconElement oo-ui-labelElement-invisible oo-ui-iconWidget oo-ui-image-invert'></span></span></span><span class='oo-ui-fieldLayout-header'><label for='ooui-php-9' class='oo-ui-labelElement-label'>Only show edits that are latest revisions</label></span></div></div><div id='ooui-php-18' class='mw-htmlform-field-HTMLCheckField oo-ui-layout oo-ui-labelElement oo-ui-fieldLayout oo-ui-fieldLayout-align-inline' data-ooui='{"_":"mw.htmlform.FieldLayout","fieldWidget":{"tag":"mw-show-new-only"},"align":"inline","helpInline":true,"$overlay":true,"label":{"html":"Only show edits that are page creations"},"classes":["mw-htmlform-field-HTMLCheckField",""]}'><div class='oo-ui-fieldLayout-body'><span class='oo-ui-fieldLayout-field'><span id='mw-show-new-only' aria-disabled='false' class='oo-ui-widget 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data-ooui='{"_":"mw.htmlform.FieldLayout","fieldWidget":{"tag":"mw-show-new-only"},"align":"inline","helpInline":true,"$overlay":true,"label":{"html":"Hide minor edits"},"classes":["mw-htmlform-field-HTMLCheckField","mw-hide-minor-edits"]}'><div class='oo-ui-fieldLayout-body'><span class='oo-ui-fieldLayout-field'><span id='mw-show-new-only' aria-disabled='false' class='mw-hide-minor-edits oo-ui-widget oo-ui-widget-enabled oo-ui-inputWidget oo-ui-checkboxInputWidget' data-ooui='{"_":"OO.ui.CheckboxInputWidget","name":"hideMinor","value":"1","inputId":"ooui-php-11","required":false,"classes":["mw-hide-minor-edits"]}'><input type='checkbox' tabindex='0' aria-disabled='false' name='hideMinor' value='1' id='ooui-php-11' class='oo-ui-inputWidget-input' /><span aria-disabled='false' class='oo-ui-checkboxInputWidget-checkIcon oo-ui-widget oo-ui-widget-enabled oo-ui-iconElement-icon oo-ui-icon-check oo-ui-iconElement oo-ui-labelElement-invisible oo-ui-iconWidget oo-ui-image-invert'></span></span></span><span class='oo-ui-fieldLayout-header'><label for='ooui-php-11' class='oo-ui-labelElement-label'>Hide minor edits</label></span></div></div></div></div></div></fieldset></div><div class='oo-ui-layout oo-ui-panelLayout oo-ui-panelLayout-padded oo-ui-panelLayout-framed'><fieldset class='oo-ui-layout oo-ui-labelElement oo-ui-fieldsetLayout'><legend class='oo-ui-fieldsetLayout-header'><span class='oo-ui-iconElement-icon oo-ui-iconElement-noIcon'></span><span class='oo-ui-labelElement-label'>⧼contribs-date⧽</span></legend><div class='oo-ui-fieldsetLayout-group'><div aria-disabled='false' class='oo-ui-widget oo-ui-widget-enabled'><div id="mw-htmlform-contribs-date"><div data-mw-modules='mediawiki.widgets.DateInputWidget' id='ooui-php-22' class='mw-htmlform-field-HTMLDateTimeField mw-htmlform-datetime-field mw-htmlform-autoinfuse oo-ui-layout oo-ui-labelElement oo-ui-fieldLayout oo-ui-fieldLayout-align-top' data-ooui='{"_":"mw.htmlform.FieldLayout","fieldWidget":{"tag":"mw-date-start"},"align":"top","helpInline":true,"$overlay":true,"label":{"html":"From date:"},"classes":["mw-htmlform-field-HTMLDateTimeField"," mw-htmlform-datetime-field","mw-htmlform-autoinfuse"]}'><div class='oo-ui-fieldLayout-body'><span class='oo-ui-fieldLayout-header'><label for='ooui-php-20' class='oo-ui-labelElement-label'>From date:</label></span><div class='oo-ui-fieldLayout-field'><div id='mw-date-start' aria-disabled='false' class='oo-ui-widget oo-ui-widget-enabled oo-ui-inputWidget oo-ui-textInputWidget oo-ui-textInputWidget-type-text oo-ui-textInputWidget-php mw-widget-dateInputWidget' data-ooui='{"_":"mw.widgets.DateInputWidget","longDisplayFormat":false,"precision":"day","$overlay":true,"placeholder":"YYYY-MM-DD","name":"start","inputId":"ooui-php-20","required":false}'><input type='date' tabindex='0' aria-disabled='false' name='start' value='' placeholder='YYYY-MM-DD' id='ooui-php-20' class='oo-ui-inputWidget-input' /><span class='oo-ui-iconElement-icon oo-ui-iconElement-noIcon'></span><span class='oo-ui-indicatorElement-indicator oo-ui-indicatorElement-noIndicator'></span></div></div></div></div><div data-mw-modules='mediawiki.widgets.DateInputWidget' id='ooui-php-23' class='mw-htmlform-field-HTMLDateTimeField mw-htmlform-datetime-field mw-htmlform-autoinfuse oo-ui-layout oo-ui-labelElement oo-ui-fieldLayout oo-ui-fieldLayout-align-top' data-ooui='{"_":"mw.htmlform.FieldLayout","fieldWidget":{"tag":"mw-date-end"},"align":"top","helpInline":true,"$overlay":true,"label":{"html":"To date:"},"classes":["mw-htmlform-field-HTMLDateTimeField"," mw-htmlform-datetime-field","mw-htmlform-autoinfuse"]}'><div class='oo-ui-fieldLayout-body'><span class='oo-ui-fieldLayout-header'><label for='ooui-php-21' class='oo-ui-labelElement-label'>To date:</label></span><div class='oo-ui-fieldLayout-field'><div id='mw-date-end' aria-disabled='false' class='oo-ui-widget oo-ui-widget-enabled oo-ui-inputWidget oo-ui-textInputWidget oo-ui-textInputWidget-type-text oo-ui-textInputWidget-php mw-widget-dateInputWidget' data-ooui='{"_":"mw.widgets.DateInputWidget","longDisplayFormat":false,"precision":"day","$overlay":true,"placeholder":"YYYY-MM-DD","name":"end","inputId":"ooui-php-21","required":false}'><input type='date' tabindex='0' aria-disabled='false' name='end' value='' placeholder='YYYY-MM-DD' id='ooui-php-21' class='oo-ui-inputWidget-input' /><span class='oo-ui-iconElement-icon oo-ui-iconElement-noIcon'></span><span class='oo-ui-indicatorElement-indicator oo-ui-indicatorElement-noIndicator'></span></div></div></div></div></div></div></div></fieldset></div> +<input id="mw-input-limit" name="limit" type="hidden" value="50"/> +<input id="mw-input-title" name="title" type="hidden" value="Special:Contributions"/> +<div class="mw-htmlform-submit-buttons"> +<span aria-disabled='false' id='ooui-php-24' class='mw-htmlform-submit oo-ui-widget oo-ui-widget-enabled oo-ui-inputWidget oo-ui-buttonElement oo-ui-buttonElement-framed oo-ui-labelElement oo-ui-flaggedElement-primary oo-ui-flaggedElement-progressive oo-ui-buttonInputWidget' data-ooui='{"_":"OO.ui.ButtonInputWidget","type":"submit","value":"Search","label":"Search","flags":["primary","progressive"],"classes":["mw-htmlform-submit"]}'><button type='submit' tabindex='0' aria-disabled='false' value='Search' class='oo-ui-inputWidget-input oo-ui-buttonElement-button'><span class='oo-ui-iconElement-icon oo-ui-iconElement-noIcon oo-ui-image-invert'></span><span class='oo-ui-labelElement-label'>Search</span><span class='oo-ui-indicatorElement-indicator oo-ui-indicatorElement-noIndicator oo-ui-image-invert'></span></button></span></div> +</div></div></fieldset></form></div><p class="mw-pager-navigation-bar">(newest | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&dir=prev&target=Arthur" class="mw-lastlink" title="Special:Contributions/Arthur">oldest</a>) View (newer 50 | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=20230302003218&target=Arthur" class="mw-nextlink" title="Special:Contributions/Arthur" rel="next">older 50</a>) (<a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=&limit=20&target=Arthur" class="mw-numlink" title="Special:Contributions/Arthur">20</a> | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=&limit=50&target=Arthur" class="mw-numlink" title="Special:Contributions/Arthur">50</a> | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=&limit=100&target=Arthur" class="mw-numlink" title="Special:Contributions/Arthur">100</a> | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=&limit=250&target=Arthur" class="mw-numlink" title="Special:Contributions/Arthur">250</a> | <a href="https://open-iov.org/index.php?title=Special:Contributions/Arthur&offset=&limit=500&target=Arthur" class="mw-numlink" title="Special:Contributions/Arthur">500</a>)</p><ul class="mw-contributions-list"> +<li data-mw-revid="23794" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=Articles&oldid=23794.html" class="mw-changeslist-date" title="Articles">16:27, 19 April 2024</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23794" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,196 bytes after change">−11</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23793" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Articles&oldid=23793" class="mw-changeslist-date" title="Articles">16:16, 19 April 2024</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23793" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,207 bytes after change">−68</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23792" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&oldid=23792.html" class="mw-changeslist-date" title="Virtual I/O Internals">17:54, 19 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23792" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="45,293 bytes after change">+96</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)" title="Virtual I/O Internals">→References (Talks & Reading Material)</a></span></span></span> +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23791" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=GPU_Driver_Internals&oldid=23791.html" class="mw-changeslist-date" title="GPU Driver Internals">17:53, 19 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23791" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="22,686 bytes after change">+96</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)" title="GPU Driver Internals">→References (Talks & Reading Material)</a></span></span></span> +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23790" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23790" class="mw-changeslist-date" title="Virtual I/O Internals">17:52, 19 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23790" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="45,197 bytes after change">+63</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23789" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23789" class="mw-changeslist-date" title="GPU Driver Internals">17:51, 19 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23789" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="22,590 bytes after change">+88</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span 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title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="22,502 bytes after change">−6</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#QEMU_Host-Side_Modules" title="GPU Driver Internals">→QEMU Host-Side Modules</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23787" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23787" class="mw-changeslist-date" title="GPU Driver Internals">20:54, 16 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23787" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <strong dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="22,508 bytes after change">+3,413</strong> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23786" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23786.html" class="mw-changeslist-date" title="GPU Software Bill Of Materials (SBOM)">14:58, 13 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23786" class="mw-changeslist-diff" title="GPU Software Bill Of Materials (SBOM)">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html" class="mw-changeslist-history" title="GPU Software Bill Of Materials (SBOM)">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-null mw-diff-bytes" title="10,238 bytes after change">0</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + <span class="comment comment--without-parentheses">Updated Nvidia VGX vGPU version to 15.2 in GPU SBOM.</span> +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23785" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23785" class="mw-changeslist-date" title="Virtual I/O Internals">17:02, 12 June 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23785" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="45,134 bytes after change">+144</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O 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href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23783" class="mw-changeslist-date" title="Virtual I/O Internals">21:20, 22 May 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23783" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="44,990 bytes after change">+101</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a 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class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="44,648 bytes after change">+82</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)" title="Virtual I/O Internals">→References (Talks & Reading Material)</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker 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+<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#Translation_Tables" title="GPU Driver Internals">→Translation Tables</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23776" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23776" class="mw-changeslist-date" title="GPU Driver Internals">23:27, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23776" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="18,767 bytes after change">+131</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#References_(Talks_&_Reading_Material)" title="GPU Driver Internals">→References (Talks & Reading Material)</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" 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class="mw-changeslist-date" title="GPU Software Bill Of Materials (SBOM)">17:37, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23774" class="mw-changeslist-diff" title="GPU Software Bill Of Materials (SBOM)">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html" class="mw-changeslist-history" title="GPU Software Bill Of Materials (SBOM)">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="10,238 bytes after change">+18</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" 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class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23772" class="mw-changeslist-diff" title="GPU Software Bill Of Materials (SBOM)">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html" class="mw-changeslist-history" title="GPU Software Bill Of Materials (SBOM)">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="9,308 bytes after change">+70</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a 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after change">+135</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23770" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23770" class="mw-changeslist-date" title="GPU Software Bill Of Materials (SBOM)">17:12, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23770" class="mw-changeslist-diff" title="GPU Software Bill Of Materials (SBOM)">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html" class="mw-changeslist-history" title="GPU Software Bill Of Materials (SBOM)">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="9,103 bytes after change">+324</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23769" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23769" class="mw-changeslist-date" title="GPU Driver Internals">17:09, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23769" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="18,581 bytes after change">+62</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23768" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23768" class="mw-changeslist-date" title="GPU Driver Internals">17:08, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23768" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="18,519 bytes after change">+194</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#RM_Core" title="GPU Driver Internals">→RM Core</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23767" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23767" class="mw-changeslist-date" title="GPU Driver Internals">17:05, 5 April 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23767" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="18,325 bytes after change">+351</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../GPU_Driver_Internals.html#nvidia-vgpu-mgr" title="GPU Driver Internals">→nvidia-vgpu-mgr</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23766" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Articles&oldid=23766" class="mw-changeslist-date" title="Articles">19:01, 30 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23766" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,272 bytes after change">−53</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Articles.html#Projects" title="Articles">→Projects</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23765" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=Main_Page&oldid=23765.html" class="mw-changeslist-date" title="Main Page">18:25, 30 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Main_Page&diff=prev&oldid=23765" class="mw-changeslist-diff" title="Main Page">diff</a></span> <span><a href="../../index.php%3Ftitle=Main_Page&action=history.html" class="mw-changeslist-history" title="Main Page">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="1,190 bytes after change">+8</span> <span class="mw-changeslist-separator"></span> +<a href="../../images/archive/c/c3/20221214193624!I915_Scheduling_Events_and_Requests.png.html" class="mw-contributions-title" title="Main Page">Main Page</a> + +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23764" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23764" class="mw-changeslist-date" title="Virtual I/O Internals">19:50, 28 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23764" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="44,566 bytes after change">+77</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)" title="Virtual I/O Internals">→References (Talks & Reading Material)</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23763" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=Glossary&oldid=23763.html" class="mw-changeslist-date" title="Glossary">19:24, 27 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Glossary&diff=prev&oldid=23763" class="mw-changeslist-diff" title="Glossary">diff</a></span> <span><a href="../../index.php%3Ftitle=Glossary&action=history.html" class="mw-changeslist-history" title="Glossary">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="6,694 bytes after change">+248</span> <span class="mw-changeslist-separator"></span> +<a href="../Glossary.html" class="mw-contributions-title" title="Glossary">Glossary</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Glossary.html#Virtual_GPU_(vGPU)" title="Glossary">→Virtual GPU (vGPU)</a></span></span></span> +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23762" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&oldid=23762" class="mw-changeslist-date" title="Virtual I/O Internals">19:08, 27 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Virtual_I/O_Internals&diff=prev&oldid=23762" class="mw-changeslist-diff" title="Virtual I/O Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=Virtual_I%252FO_Internals&action=history.html" class="mw-changeslist-history" title="Virtual I/O Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="44,489 bytes after change">+1</span> <span class="mw-changeslist-separator"></span> +<a href="../Virtual_I/O_Internals.html" class="mw-contributions-title" title="Virtual I/O Internals">Virtual I/O Internals</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Virtual_I/O_Internals.html#Instruction_Execution" title="Virtual I/O Internals">→Instruction Execution</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23761" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&oldid=23761" class="mw-changeslist-date" title="GPU Software Bill Of Materials (SBOM)">04:57, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Software_Bill_Of_Materials_(SBOM)&diff=prev&oldid=23761" class="mw-changeslist-diff" title="GPU Software Bill Of Materials (SBOM)">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Software_Bill_Of_Materials_(SBOM)&action=history.html" class="mw-changeslist-history" title="GPU Software Bill Of Materials (SBOM)">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="8,779 bytes after change">+168</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" class="mw-contributions-title" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> + + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23760" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Articles&oldid=23760" class="mw-changeslist-date" title="Articles">04:45, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23760" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,325 bytes after change">−95</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Articles.html#Integration_Documents" title="Articles">→GVM Integration Documents</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23759" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Articles&oldid=23759" class="mw-changeslist-date" title="Articles">04:42, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23759" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,420 bytes after change">−2</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Articles.html#Gpuvm_Integration_Documents" title="Articles">→Gpuvm Integration Documents</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23758" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=Articles&oldid=23758" class="mw-changeslist-date" title="Articles">04:42, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Articles&diff=prev&oldid=23758" class="mw-changeslist-diff" title="Articles">diff</a></span> <span><a href="../../index.php%3Ftitle=Articles&action=history.html" class="mw-changeslist-history" title="Articles">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="5,422 bytes after change">−77</span> <span class="mw-changeslist-separator"></span> +<a href="../Articles.html" class="mw-contributions-title" title="Articles">Articles</a> + <span class="comment comment--without-parentheses"><span dir="auto"><span class="autocomment"><a href="../Articles.html#Integration_Documents" title="Articles">→GVM Integration Documents</a></span></span></span> + +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23757" class="mw-contributions-current mw-tag-visualeditor"><a href="../../index.php%3Ftitle=Intel&oldid=23757.html" class="mw-changeslist-date" title="Intel">04:42, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Intel&diff=prev&oldid=23757" class="mw-changeslist-diff" title="Intel">diff</a></span> <span><a href="../../index.php%3Ftitle=Intel&action=history.html" class="mw-changeslist-history" title="Intel">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-neg mw-diff-bytes" title="508 bytes after change">−51</span> <span class="mw-changeslist-separator"></span> +<a href="../Intel.html" class="mw-contributions-title" title="Intel">Intel</a> + +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-visualeditor"><a href="https://open-iov.org/index.php?title=Open-IOV:VisualEditor&action=edit&redlink=1" class="new" title="Open-IOV:VisualEditor (page does not exist)">Visual edit</a></span></span> +</li> +<li data-mw-revid="23756" class="mw-contributions-current mw-tag-mw-new-redirect"><a href="../../index.php%3Ftitle=Intel_SR-IOV_APIs&oldid=23756.html" class="mw-redirect mw-changeslist-date" title="Intel SR-IOV APIs">04:26, 23 March 2023</a> +<span class="mw-changeslist-links"><span>diff</span> <span><a href="../../index.php%3Ftitle=Intel_SR-IOV_APIs&action=history.html" class="mw-redirect mw-changeslist-history" title="Intel SR-IOV APIs">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="19 bytes after change">+19</span> <span class="mw-changeslist-separator"></span> <abbr class="newpage" title="This edit created a new page">N</abbr> +<a href="../../index.php%3Ftitle=Intel_SR-IOV_APIs&redirect=no.html" class="mw-redirect mw-contributions-title" title="Intel SR-IOV APIs">Intel SR-IOV APIs</a> + <span class="comment comment--without-parentheses">Arthur moved page <a href="../Intel_SR-IOV_APIs.html" class="mw-redirect" title="Intel SR-IOV APIs">Intel SR-IOV APIs</a> to <a href="../Intel.html" title="Intel">Intel</a></span> +<span class="mw-uctop">current</span> +<span class="mw-tag-markers"><a href="https://open-iov.org/index.php/Special:Tags" title="Special:Tags">Tag</a>: <span class="mw-tag-marker mw-tag-marker-mw-new-redirect">New redirect</span></span> +</li> +<li data-mw-revid="23755"><a href="https://open-iov.org/index.php?title=Intel&oldid=23755" class="mw-changeslist-date" title="Intel">04:26, 23 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=Intel&diff=prev&oldid=23755" class="mw-changeslist-diff" title="Intel">diff</a></span> <span><a href="../../index.php%3Ftitle=Intel&action=history.html" class="mw-changeslist-history" title="Intel">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-null mw-diff-bytes" title="559 bytes after change">0</span> <span class="mw-changeslist-separator"></span> <abbr class="minoredit" title="This is a minor edit">m</abbr> +<a href="../Intel.html" class="mw-contributions-title" title="Intel">Intel</a> + <span class="comment comment--without-parentheses">Arthur moved page <a href="../Intel_SR-IOV_APIs.html" class="mw-redirect" title="Intel SR-IOV APIs">Intel SR-IOV APIs</a> to <a href="../Intel.html" title="Intel">Intel</a></span> + + +</li> +<li data-mw-revid="23754" class="mw-tag-visualeditor"><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&oldid=23754" class="mw-changeslist-date" title="GPU Driver Internals">23:02, 22 March 2023</a> +<span class="mw-changeslist-links"><span><a href="https://open-iov.org/index.php?title=GPU_Driver_Internals&diff=prev&oldid=23754" class="mw-changeslist-diff" title="GPU Driver Internals">diff</a></span> <span><a href="../../index.php%3Ftitle=GPU_Driver_Internals&action=history.html" class="mw-changeslist-history" title="GPU Driver Internals">hist</a></span></span> <span class="mw-changeslist-separator"></span> <span dir="ltr" class="mw-plusminus-pos mw-diff-bytes" title="17,974 bytes after change">+201</span> <span class="mw-changeslist-separator"></span> +<a href="../GPU_Driver_Internals.html" class="mw-contributions-title" title="GPU Driver Internals">GPU Driver Internals</a> + <span class="comment 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=500" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../Glossary.html" title="Glossary">Glossary</a> (file link) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Glossary" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=20" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=50" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=100" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=250" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png&limit=500" title="Special:WhatLinksHere/File:Application Binary Interface (ABI).png">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="./File:Application_Binary_Interface_(ABI).png.html">https://open-iov.org/index.php/Special:WhatLinksHere/File:Application_Binary_Interface_(ABI).png</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> 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title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=500" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../GPU_Driver_Internals.html" title="GPU Driver Internals">GPU Driver Internals</a> (file link) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=GPU+Driver+Internals" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=20" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=50" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=100" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=250" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png&limit=500" title="Special:WhatLinksHere/File:I915 Scheduling Events and Requests.png">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="./File:I915_Scheduling_Events_and_Requests.png.html">https://open-iov.org/index.php/Special:WhatLinksHere/File:I915_Scheduling_Events_and_Requests.png</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" 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name="title"/><fieldset> +<legend>What links here</legend> +<label for="mw-whatlinkshere-target" class="mw-searchInput">Page:</label> <input name="target" size="40" value="File:IVSHMEM.png" id="mw-whatlinkshere-target" class="mw-searchInput" /> <label for="namespace">Namespace:</label> <select class="namespaceselector" id="namespace" name="namespace"> +<option value="" selected="">all</option> +<option value="0">(Main)</option> +<option value="1">Talk</option> +<option value="2">User</option> +<option value="3">User talk</option> +<option value="4">Open-IOV</option> +<option value="5">Open-IOV talk</option> +<option value="6">File</option> +<option value="7">File talk</option> +<option value="8">MediaWiki</option> +<option value="9">MediaWiki talk</option> +<option value="10">Template</option> +<option value="11">Template talk</option> +<option value="12">Help</option> +<option value="13">Help talk</option> +<option value="14">Category</option> +<option value="15">Category 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:IVSHMEM.png&limit=500" title="Special:WhatLinksHere/File:IVSHMEM.png">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../Glossary.html" title="Glossary">Glossary</a> (file link) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Glossary" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:IVSHMEM.png&limit=20" title="Special:WhatLinksHere/File:IVSHMEM.png">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:IVSHMEM.png&limit=50" title="Special:WhatLinksHere/File:IVSHMEM.png">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:IVSHMEM.png&limit=100" title="Special:WhatLinksHere/File:IVSHMEM.png">100</a> | <a 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name="title"/><fieldset> +<legend>What links here</legend> +<label for="mw-whatlinkshere-target" class="mw-searchInput">Page:</label> <input name="target" size="40" value="File:SR-IOV.png" id="mw-whatlinkshere-target" class="mw-searchInput" /> <label for="namespace">Namespace:</label> <select class="namespaceselector" id="namespace" name="namespace"> +<option value="" selected="">all</option> +<option value="0">(Main)</option> +<option value="1">Talk</option> +<option value="2">User</option> +<option value="3">User talk</option> +<option value="4">Open-IOV</option> +<option value="5">Open-IOV talk</option> +<option value="6">File</option> +<option value="7">File talk</option> +<option value="8">MediaWiki</option> +<option value="9">MediaWiki talk</option> +<option value="10">Template</option> +<option value="11">Template talk</option> +<option value="12">Help</option> +<option value="13">Help talk</option> +<option value="14">Category</option> +<option value="15">Category talk</option> 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=500" title="Special:WhatLinksHere/File:SR-IOV.png">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../Glossary.html" title="Glossary">Glossary</a> (file link) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Glossary" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=20" title="Special:WhatLinksHere/File:SR-IOV.png">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=50" title="Special:WhatLinksHere/File:SR-IOV.png">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=100" title="Special:WhatLinksHere/File:SR-IOV.png">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=250" title="Special:WhatLinksHere/File:SR-IOV.png">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:SR-IOV.png&limit=500" title="Special:WhatLinksHere/File:SR-IOV.png">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="./File:SR-IOV.png.html">https://open-iov.org/index.php/Special:WhatLinksHere/File:SR-IOV.png</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Telescope_LG-Proxy.png&limit=50" title="Special:WhatLinksHere/File:Telescope LG-Proxy.png">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Telescope_LG-Proxy.png&limit=100" title="Special:WhatLinksHere/File:Telescope LG-Proxy.png">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Telescope_LG-Proxy.png&limit=250" title="Special:WhatLinksHere/File:Telescope LG-Proxy.png">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Telescope_LG-Proxy.png&limit=500" title="Special:WhatLinksHere/File:Telescope LG-Proxy.png">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../Looking_Glass_KVMFR.html" title="Looking Glass KVMFR">Looking Glass KVMFR</a> (file link) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Looking+Glass+KVMFR" title="Special:WhatLinksHere">← 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/File:Vfio-pci_driver_bindings.png&limit=500" title="Special:WhatLinksHere/File:Vfio-pci driver bindings.png">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="./File:Vfio-pci_driver_bindings.png.html">https://open-iov.org/index.php/Special:WhatLinksHere/File:Vfio-pci_driver_bindings.png</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" class="mw-list-item"><a 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Internals">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../Articles.html" title="Articles">Articles</a> <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Articles" title="Special:WhatLinksHere">← links</a>)</span></li> +<li><a href="../Introduction.html" title="Introduction">Introduction</a> <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Introduction" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/GPU_Driver_Internals&limit=20" title="Special:WhatLinksHere/GPU Driver Internals">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/GPU_Driver_Internals&limit=50" title="Special:WhatLinksHere/GPU Driver Internals">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/GPU_Driver_Internals&limit=100" title="Special:WhatLinksHere/GPU Driver Internals">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/GPU_Driver_Internals&limit=250" title="Special:WhatLinksHere/GPU Driver Internals">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/GPU_Driver_Internals&limit=500" title="Special:WhatLinksHere/GPU Driver Internals">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="GPU_Driver_Internals.html">https://open-iov.org/index.php/Special:WhatLinksHere/GPU_Driver_Internals</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Special:WhatLinksHere/Glossary.html b/wiki/open-iov.org/index.php/Special:WhatLinksHere/Glossary.html new file mode 100644 index 0000000..8c6a961 --- /dev/null +++ b/wiki/open-iov.org/index.php/Special:WhatLinksHere/Glossary.html @@ -0,0 +1,218 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Pages that link to "Glossary" - Open-IOV</title> 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Special:WhatLinksHere/Intel.html b/wiki/open-iov.org/index.php/Special:WhatLinksHere/Intel.html new file mode 100644 index 0000000..0aa4d85 --- /dev/null +++ b/wiki/open-iov.org/index.php/Special:WhatLinksHere/Intel.html @@ -0,0 +1,217 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Pages that link to "Intel" - Open-IOV</title> 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=20" title="Special:WhatLinksHere/Intel">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=50" title="Special:WhatLinksHere/Intel">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=100" title="Special:WhatLinksHere/Intel">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=250" title="Special:WhatLinksHere/Intel">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=500" title="Special:WhatLinksHere/Intel">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../../index.php%3Ftitle=Intel_SR-IOV_APIs&redirect=no.html" class="mw-redirect" title="Intel SR-IOV APIs">Intel SR-IOV APIs</a> (redirect page) <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Intel+SR-IOV+APIs" title="Special:WhatLinksHere">← links</a>)</span> +<ul><li><a href="../Articles.html" title="Articles">Articles</a> <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Articles" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul></li></ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=20" title="Special:WhatLinksHere/Intel">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=50" title="Special:WhatLinksHere/Intel">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=100" title="Special:WhatLinksHere/Intel">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=250" title="Special:WhatLinksHere/Intel">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Intel&limit=500" title="Special:WhatLinksHere/Intel">500</a>) +<div class="printfooter">Retrieved from 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href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=Articles" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Merged_Drivers&limit=20" title="Special:WhatLinksHere/Merged Drivers">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Merged_Drivers&limit=50" title="Special:WhatLinksHere/Merged Drivers">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Merged_Drivers&limit=100" title="Special:WhatLinksHere/Merged Drivers">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Merged_Drivers&limit=250" title="Special:WhatLinksHere/Merged Drivers">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/Merged_Drivers&limit=500" title="Special:WhatLinksHere/Merged Drivers">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Special:WhatLinksHere/OpenRM.html b/wiki/open-iov.org/index.php/Special:WhatLinksHere/OpenRM.html new file mode 100644 index 0000000..87d2172 --- /dev/null +++ b/wiki/open-iov.org/index.php/Special:WhatLinksHere/OpenRM.html @@ -0,0 +1,216 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Pages that link to "OpenRM" - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!0,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"ea106e5cf4ec11eb0981989f","wgCSPNonce":!1,"wgCanonicalNamespace":"Special","wgCanonicalSpecialPageName":"Whatlinkshere","wgNamespaceNumber":-1,"wgPageName":"Special:WhatLinksHere/OpenRM","wgTitle":"WhatLinksHere/OpenRM","wgCurRevisionId":0,"wgRevisionId":0,"wgArticleId":0,"wgIsArticle":!1,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"OpenRM","wgRelevantArticleId":40,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"}, +"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","mediawiki.helplink":"ready","mediawiki.special.changeslist":"ready","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["mediawiki.special.recentchanges","site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); +});});</script> +<link rel="stylesheet" href="https://open-iov.org/load.php?lang=en&modules=ext.visualEditor.desktopArticleTarget.noscript%7Cmediawiki.helplink%7Cmediawiki.special.changeslist%7Cskins.vector.styles.legacy&only=styles&skin=vector"/> +<script async="" src="../../load.php%3Flang=en&modules=startup&only=scripts&raw=1&skin=vector"></script> +<meta name="generator" content="MediaWiki 1.37.1"/> +<meta name="robots" content="noindex,nofollow"/> +<meta name="format-detection" content="telephone=no"/> +<link rel="shortcut icon" href="../../favicon.ico.html"/> +<link rel="search" type="application/opensearchdescription+xml" href="../../opensearch_desc.php" title="Open-IOV (en)"/> +<link rel="EditURI" type="application/rsd+xml" href="../../api.php%3Faction=rsd"/> +<link rel="alternate" type="application/atom+xml" title="Open-IOV Atom feed" href="../../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns--1 ns-special mw-special-Whatlinkshere page-Special_WhatLinksHere_OpenRM rootpage-Special_WhatLinksHere_OpenRM skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + <div id="mw-indicator-mw-helplink" class="mw-indicator"><a href="https://www.mediawiki.org/wiki/Special:MyLanguage/Help:What_links_here" target="_blank" class="mw-helplink">Help</a></div> + </div> + <h1 id="firstHeading" class="firstHeading" >Pages that link to "OpenRM"</h1> + <div id="bodyContent" class="vector-body"> + + <div id="contentSub">← <a href="../OpenRM.html" title="OpenRM">OpenRM</a></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="OpenRM.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="OpenRM.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content"><form action="https://open-iov.org/index.php"><input type="hidden" value="Special:WhatLinksHere" name="title"/><fieldset> +<legend>What links here</legend> +<label for="mw-whatlinkshere-target" class="mw-searchInput">Page:</label> <input name="target" size="40" value="OpenRM" id="mw-whatlinkshere-target" class="mw-searchInput" /> <label for="namespace">Namespace:</label> <select class="namespaceselector" id="namespace" name="namespace"> +<option value="" selected="">all</option> +<option value="0">(Main)</option> +<option value="1">Talk</option> +<option value="2">User</option> +<option value="3">User talk</option> +<option value="4">Open-IOV</option> +<option value="5">Open-IOV talk</option> +<option value="6">File</option> +<option value="7">File talk</option> +<option value="8">MediaWiki</option> +<option value="9">MediaWiki talk</option> +<option value="10">Template</option> +<option value="11">Template talk</option> +<option value="12">Help</option> +<option value="13">Help talk</option> +<option value="14">Category</option> +<option value="15">Category talk</option> +</select> <span class="mw-input-with-label mw-input-hidden"><input name="invert" type="checkbox" value="1" id="nsinvert" title="Check this box to hide links from pages within the selected namespace." /> <label for="nsinvert" title="Check this box to hide links from pages within the selected namespace.">Invert selection</label></span> <input type="submit" value="Go"/></fieldset></form> +<fieldset> +<legend>Filters</legend> +<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&hidetrans=1" title="Special:WhatLinksHere/OpenRM">Hide</a> transclusions | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&hidelinks=1" title="Special:WhatLinksHere/OpenRM">Hide</a> links | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&hideredirs=1" title="Special:WhatLinksHere/OpenRM">Hide</a> redirects +</fieldset> +<p>The following pages link to <strong><a href="../OpenRM.html" title="OpenRM">OpenRM</a></strong>: +</p><p>Displayed 1 item. +</p>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=20" title="Special:WhatLinksHere/OpenRM">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=50" title="Special:WhatLinksHere/OpenRM">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=100" title="Special:WhatLinksHere/OpenRM">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=250" title="Special:WhatLinksHere/OpenRM">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=500" title="Special:WhatLinksHere/OpenRM">500</a>)<ul id="mw-whatlinkshere-list"><li><a href="../GPU_Software_Bill_Of_Materials_(SBOM).html" title="GPU Software Bill Of Materials (SBOM)">GPU Software Bill Of Materials (SBOM)</a> <span class="mw-whatlinkshere-tools">(<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere&target=GPU+Software+Bill+Of+Materials+%28SBOM%29" title="Special:WhatLinksHere">← links</a>)</span></li> +</ul>View (previous 50 | next 50) (<a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=20" title="Special:WhatLinksHere/OpenRM">20</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=50" title="Special:WhatLinksHere/OpenRM">50</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=100" title="Special:WhatLinksHere/OpenRM">100</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=250" title="Special:WhatLinksHere/OpenRM">250</a> | <a href="https://open-iov.org/index.php?title=Special:WhatLinksHere/OpenRM&limit=500" title="Special:WhatLinksHere/OpenRM">500</a>) +<div class="printfooter">Retrieved from "<a dir="ltr" href="OpenRM.html">https://open-iov.org/index.php/Special:WhatLinksHere/OpenRM</a>"</div></div> + <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> + </div> +</div> + +<div id="mw-navigation"> + <h2>Navigation menu</h2> + <div id="mw-head"> + <nav id="p-personal" class="mw-portlet mw-portlet-personal vector-user-menu-legacy vector-menu" aria-labelledby="p-personal-label" role="navigation" + > + <h3 id="p-personal-label" class="vector-menu-heading"> <span>Personal tools</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="pt-login" class="mw-list-item"><a href="https://open-iov.org/index.php?title=Special:UserLogin&returnto=Special%3AWhatLinksHere%2FOpenRM" title="You are encouraged to log in; however, it is not mandatory [o]" accesskey="o">Log in</a></li></ul> + + </div> +</nav> + + <div id="left-navigation"> + <nav id="p-namespaces" class="mw-portlet mw-portlet-namespaces vector-menu vector-menu-tabs" aria-labelledby="p-namespaces-label" role="navigation" + > + <h3 id="p-namespaces-label" class="vector-menu-heading"> <span>Namespaces</span> + </h3> + <div class="vector-menu-content"> + + <ul class="vector-menu-content-list"><li id="ca-nstab-main" class="selected mw-list-item"><a href="../OpenRM.html" title="View the content page [c]" accesskey="c">Page</a></li><li id="ca-talk" class="new mw-list-item"><a href="https://open-iov.org/index.php?title=Talk:OpenRM&action=edit&redlink=1" rel="discussion" title="Discussion about the content page (page does not exist) [t]" accesskey="t">Discussion</a></li></ul> + + </div> +</nav> + + <nav id="p-variants" class="mw-portlet mw-portlet-variants emptyPortlet vector-menu-dropdown-noicon vector-menu vector-menu-dropdown" aria-labelledby="p-variants-label" role="navigation" + > + <input type="checkbox" + id="p-variants-checkbox" + role="button" + aria-haspopup="true" + data-event-name="ui.dropdown-p-variants" + class=" vector-menu-checkbox" aria-labelledby="p-variants-label" /> + <h3 id="p-variants-label" class="vector-menu-heading"> <span>Variants</span> + <span class="vector-menu-checkbox-expanded">expanded</span> + <span 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/VGPU_Unlock.html b/wiki/open-iov.org/index.php/VGPU_Unlock.html new file mode 100644 index 0000000..7d4ca73 --- /dev/null +++ b/wiki/open-iov.org/index.php/VGPU_Unlock.html @@ -0,0 +1,215 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>VGPU Unlock - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"0157d7b72872e7dc54e40473","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"VGPU_Unlock","wgTitle":"VGPU Unlock","wgCurRevisionId":145,"wgRevisionId":145,"wgArticleId":38,"wgIsArticle":!0,"wgIsRedirect":!1,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":[],"wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"VGPU_Unlock","wgRelevantArticleId":38,"wgIsProbablyEditable":!1,"wgRelevantPageIsProbablyEditable":!1,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgVisualEditor":{"pageLanguageCode":"en","pageLanguageDir":"ltr","pageVariantFallbacks":"en" +},"wgEditSubmitButtonLabelPublish":!1};RLSTATE={"site.styles":"ready","noscript":"ready","user.styles":"ready","user":"ready","user.options":"loading","skins.vector.styles.legacy":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready"};RLPAGEMODULES=["site","mediawiki.page.ready","skins.vector.legacy.js","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader"];</script> +<script>(RLQ=window.RLQ||[]).push(function(){mw.loader.implement("user.options@1hzgi",function($,jQuery,require,module){/*@nomin*/mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Virtual_I/O_Internals.html b/wiki/open-iov.org/index.php/Virtual_I/O_Internals.html new file mode 100644 index 0000000..d94714c --- /dev/null +++ b/wiki/open-iov.org/index.php/Virtual_I/O_Internals.html @@ -0,0 +1,1013 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Virtual I/O Internals - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"52fb822c5e4ab4015d1f9ece","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Virtual_I/O_Internals","wgTitle":"Virtual I/O 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href="../../index.php%3Ftitle=Special:RecentChanges&feed=atom"/> +</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Virtual_I_O_Internals rootpage-Virtual_I_O_Internals skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Virtual I/O Internals</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="O_Internals.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="O_Internals.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>The following document details the internals of a <b>VFIO (Virtual Function I/O)</b> driven <b>Shared</b> <b>I/O Device.</b></p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<p>This article places emphasis on the <b>Virtual GPU (vGPU)</b> use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +</p> +<table class="wikitable"> +<caption>Comparison of Assistance Modes +</caption> +<tbody><tr> +<th>Mdev Mode +</th> +<th>SR-IOV Mode +</th> +<th>SIOV Mode +</th></tr> +<tr> +<td>No hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td></tr> +<tr> +<td>Host requires insight about guest workload. +</td> +<td>Host ignorance of guest workload. +</td> +<td>Host requires insight about guest workload. +</td></tr> +<tr> +<td>Error reporting. +</td> +<td>No guest driver error reporting. +</td> +<td>Error reporting. +</td></tr> +<tr> +<td>In depth dynamic monitoring. +</td> +<td>Basic dynamic monitoring. +</td> +<td>In depth dynamic monitoring. +</td></tr> +<tr> +<td>Software defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td></tr> +<tr> +<td>Requires deferred instructions to be supported by host software (support libraries). +</td> +<td>Guest is ignorant of host supported software such as support libraries. +</td> +<td> +</td></tr> +<tr> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td></tr> +<tr> +<td>Device reset. +</td> +<td>Device reset. +</td> +<td>Device reset. +</td></tr> +<tr> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td></tr> +<tr> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td></tr> +<tr> +<td>Single PCI requester ID. +</td> +<td>Multiple PCI requester IDs. +</td> +<td>Multiple PCI requester IDs. +</td></tr></tbody></table> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="O_Internals.html#All_Modes"><span class="tocnumber">1</span> <span class="toctext">All Modes</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="O_Internals.html#Knowledge_Resources_Used"><span class="tocnumber">1.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="O_Internals.html#Binding_VFIO_devices"><span class="tocnumber">1.2</span> <span class="toctext">Binding VFIO devices</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="O_Internals.html#Programming_the_IOMMU"><span class="tocnumber">1.3</span> <span class="toctext">Programming the IOMMU</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="O_Internals.html#VFIO_Memory_Mapped_IO"><span class="tocnumber">1.4</span> <span class="toctext">VFIO Memory Mapped IO</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="O_Internals.html#Getting_the_VFIO_Group_File_Descriptor"><span class="tocnumber">1.5</span> <span class="toctext">Getting the VFIO Group File Descriptor</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="O_Internals.html#VFIO_device_file_descriptor"><span class="tocnumber">1.6</span> <span class="toctext">VFIO device file descriptor</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="O_Internals.html#VFIO_Interrupts"><span class="tocnumber">1.7</span> <span class="toctext">VFIO Interrupts</span></a> +<ul> +<li class="toclevel-3 tocsection-9"><a href="O_Internals.html#IRQs"><span class="tocnumber">1.7.1</span> <span class="toctext">IRQs</span></a> +<ul> +<li class="toclevel-4 tocsection-10"><a href="O_Internals.html#Get_Device_Info"><span class="tocnumber">1.7.1.1</span> <span class="toctext">Get Device Info</span></a></li> +<li class="toclevel-4 tocsection-11"><a href="O_Internals.html#Get_Region_Info"><span class="tocnumber">1.7.1.2</span> <span class="toctext">Get Region Info</span></a></li> +<li class="toclevel-4 tocsection-12"><a href="O_Internals.html#Get_IRQ_Info"><span class="tocnumber">1.7.1.3</span> <span class="toctext">Get IRQ Info</span></a></li> +<li class="toclevel-4 tocsection-13"><a href="O_Internals.html#Set_IRQs"><span class="tocnumber">1.7.1.4</span> <span class="toctext">Set IRQs</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-14"><a href="O_Internals.html#Device_Decomposure/Recomposure"><span class="tocnumber">1.8</span> <span class="toctext">Device Decomposure/Recomposure</span></a></li> +<li class="toclevel-2 tocsection-15"><a href="O_Internals.html#Memory_Management_Unit_(MMU)"><span class="tocnumber">1.9</span> <span class="toctext">Memory Management Unit (MMU)</span></a> +<ul> +<li class="toclevel-3 tocsection-16"><a href="O_Internals.html#MMIO_Isolation_(Platform_MMU)"><span class="tocnumber">1.9.1</span> <span class="toctext">MMIO Isolation (Platform MMU)</span></a></li> +<li class="toclevel-3 tocsection-17"><a href="O_Internals.html#VRAM_Isolation_(GPU_GMMU)"><span class="tocnumber">1.9.2</span> <span class="toctext">VRAM Isolation (GPU GMMU)</span></a></li> +<li class="toclevel-3 tocsection-18"><a href="O_Internals.html#Platform_MMIO_<->_GPU_Shadow_Pages"><span class="tocnumber">1.9.3</span> <span class="toctext">Platform MMIO <-> GPU Shadow Pages</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-19"><a href="O_Internals.html#VFIO_Quirks_(region_traps)"><span class="tocnumber">1.10</span> <span class="toctext">VFIO Quirks (region traps)</span></a></li> +<li class="toclevel-2 tocsection-20"><a href="O_Internals.html#Known_IOMMU_Issues"><span class="tocnumber">1.11</span> <span class="toctext">Known IOMMU Issues</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-21"><a href="O_Internals.html#Mdev_Mode"><span class="tocnumber">2</span> <span class="toctext">Mdev Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-22"><a href="O_Internals.html#Knowledge_Resources_Used_2"><span class="tocnumber">2.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-23"><a href="O_Internals.html#Mediated_Core"><span class="tocnumber">2.2</span> <span class="toctext">Mediated Core</span></a></li> +<li class="toclevel-2 tocsection-24"><a href="O_Internals.html#Device_Initialization"><span class="tocnumber">2.3</span> <span class="toctext">Device Initialization</span></a> +<ul> +<li class="toclevel-3 tocsection-25"><a href="O_Internals.html#Registering_VFIO_MDEV_as_a_driver"><span class="tocnumber">2.3.1</span> <span class="toctext">Registering VFIO MDEV as a driver</span></a></li> +<li class="toclevel-3 tocsection-26"><a href="O_Internals.html#Registering_PCIE_Device_with_the_Mediated_Core"><span class="tocnumber">2.3.2</span> <span class="toctext">Registering PCIE Device with the Mediated Core</span></a></li> +<li class="toclevel-3 tocsection-27"><a href="O_Internals.html#Registering_Mediated_Callbacks_(CBs)"><span class="tocnumber">2.3.3</span> <span class="toctext">Registering Mediated Callbacks (CBs)</span></a></li> +<li class="toclevel-3 tocsection-28"><a href="O_Internals.html#Creating_a_Mediated_Device_via_mdev-sysfsdev_API"><span class="tocnumber">2.3.4</span> <span class="toctext">Creating a Mediated Device via mdev-sysfsdev API</span></a></li> +<li class="toclevel-3 tocsection-29"><a href="O_Internals.html#QEMU_adds_VFIO_device_to_IOMMU_container-group"><span class="tocnumber">2.3.5</span> <span class="toctext">QEMU adds VFIO device to IOMMU container-group</span></a></li> +<li class="toclevel-3 tocsection-30"><a href="O_Internals.html#QEMU_passes_mdev_device_file_descriptor_to_VM"><span class="tocnumber">2.3.6</span> <span class="toctext">QEMU passes mdev device file descriptor to VM</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-31"><a href="O_Internals.html#Instruction_Execution"><span class="tocnumber">2.4</span> <span class="toctext">Instruction Execution</span></a> +<ul> +<li class="toclevel-3 tocsection-32"><a href="O_Internals.html#IRQ_remapping"><span class="tocnumber">2.4.1</span> <span class="toctext">IRQ remapping</span></a></li> +<li class="toclevel-3 tocsection-33"><a href="O_Internals.html#Interrupt_Injection"><span class="tocnumber">2.4.2</span> <span class="toctext">Interrupt Injection</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-34"><a href="O_Internals.html#Memory_Management"><span class="tocnumber">2.5</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-35"><a href="O_Internals.html#Region_Passthrough"><span class="tocnumber">2.5.1</span> <span class="toctext">Region Passthrough</span></a> +<ul> +<li class="toclevel-4 tocsection-36"><a href="O_Internals.html#Emulated_Regions"><span class="tocnumber">2.5.1.1</span> <span class="toctext">Emulated Regions</span></a></li> +<li class="toclevel-4 tocsection-37"><a href="O_Internals.html#Passthrough_Regions"><span class="tocnumber">2.5.1.2</span> <span class="toctext">Passthrough Regions</span></a></li> +<li class="toclevel-4 tocsection-38"><a href="O_Internals.html#Region_Access"><span class="tocnumber">2.5.1.3</span> <span class="toctext">Region Access</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-39"><a href="O_Internals.html#EPT_Page_Violations"><span class="tocnumber">2.5.2</span> <span class="toctext">EPT Page Violations</span></a></li> +<li class="toclevel-3 tocsection-40"><a href="O_Internals.html#Mediated_DMA_Translations"><span class="tocnumber">2.5.3</span> <span class="toctext">Mediated DMA Translations</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-41"><a href="O_Internals.html#Scheduling"><span class="tocnumber">2.6</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-42"><a href="O_Internals.html#Kernel_API"><span class="tocnumber">2.7</span> <span class="toctext">Kernel API</span></a></li> +<li class="toclevel-2 tocsection-43"><a href="O_Internals.html#Sample_Code"><span class="tocnumber">2.8</span> <span class="toctext">Sample Code</span></a> +<ul> +<li class="toclevel-3 tocsection-44"><a href="O_Internals.html#Compilation"><span class="tocnumber">2.8.1</span> <span class="toctext">Compilation</span></a></li> +<li class="toclevel-3 tocsection-45"><a href="O_Internals.html#Loading_Kernel_Modules"><span class="tocnumber">2.8.2</span> <span class="toctext">Loading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-46"><a href="O_Internals.html#Unloading_Kernel_Modules"><span class="tocnumber">2.8.3</span> <span class="toctext">Unloading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-47"><a href="O_Internals.html#Additional_Documentation"><span class="tocnumber">2.8.4</span> <span class="toctext">Additional Documentation</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-48"><a href="O_Internals.html#Mdev_Mode_Requirements"><span class="tocnumber">2.9</span> <span class="toctext">Mdev Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-49"><a href="O_Internals.html#SR-IOV_Mode"><span class="tocnumber">3</span> <span class="toctext">SR-IOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-50"><a href="O_Internals.html#Knowledge_Resources_Used_3"><span class="tocnumber">3.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-51"><a href="O_Internals.html#Instruction_Execution_2"><span class="tocnumber">3.2</span> <span class="toctext">Instruction Execution</span></a></li> +<li class="toclevel-2 tocsection-52"><a href="O_Internals.html#Memory_Management_2"><span class="tocnumber">3.3</span> <span class="toctext">Memory Management</span></a></li> +<li class="toclevel-2 tocsection-53"><a href="O_Internals.html#Scheduling_2"><span class="tocnumber">3.4</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-54"><a href="O_Internals.html#SR-IOV_Mode_Requirements"><span class="tocnumber">3.5</span> <span class="toctext">SR-IOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-55"><a href="O_Internals.html#SIOV_Mode"><span class="tocnumber">4</span> <span class="toctext">SIOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-56"><a href="O_Internals.html#Knowledge_Resources_Used_4"><span class="tocnumber">4.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-57"><a href="O_Internals.html#Memory_Management_3"><span class="tocnumber">4.2</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-58"><a href="O_Internals.html#IOMMU_Aware_Mediated_Device"><span class="tocnumber">4.2.1</span> <span class="toctext">IOMMU Aware Mediated Device</span></a></li> +<li class="toclevel-3 tocsection-59"><a href="O_Internals.html#Shared_Hardware_Workqueues"><span class="tocnumber">4.2.2</span> <span class="toctext">Shared Hardware Workqueues</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-60"><a href="O_Internals.html#SIOV_Mode_Requirements"><span class="tocnumber">4.3</span> <span class="toctext">SIOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-61"><a href="O_Internals.html#References_(Talks_&_Reading_Material)"><span class="tocnumber">5</span> <span class="toctext">References (Talks & Reading Material)</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="All_Modes">All Modes</span></h2> +<p>This section will cover concepts which apply both to <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a>, <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> & <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#SIOV_Mode">SIOV Mode</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Alex Williamson. +</p><p>See references 2, 14, & 22 in the <a rel="nofollow" class="external text" href="../Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Binding_VFIO_devices">Binding VFIO devices</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Vfio-pci_driver_bindings.png.html" class="image"><img alt="" src="../../images/thumb/9/9e/Vfio-pci_driver_bindings.png/300px-Vfio-pci_driver_bindings.png" decoding="async" width="300" height="218" class="thumbimage" srcset="../../images/thumb/9/9e/Vfio-pci_driver_bindings.png/450px-Vfio-pci_driver_bindings.png 1.5x, ../../images/thumb/9/9e/Vfio-pci_driver_bindings.png/600px-Vfio-pci_driver_bindings.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Vfio-pci_driver_bindings.png.html" class="internal" title="Enlarge"></a></div><b>Figure 1:</b> VFIO group nodes are unit of ownership that VFIO uses. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:IOCTL_set_VFIO_container.png.html" class="image"><img alt="" src="../../images/thumb/3/33/IOCTL_set_VFIO_container.png/300px-IOCTL_set_VFIO_container.png" decoding="async" width="300" height="242" class="thumbimage" srcset="../../images/thumb/3/33/IOCTL_set_VFIO_container.png/450px-IOCTL_set_VFIO_container.png 1.5x, ../../images/thumb/3/33/IOCTL_set_VFIO_container.png/600px-IOCTL_set_VFIO_container.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:IOCTL_set_VFIO_container.png.html" class="internal" title="Enlarge"></a></div><b>Figure 2:</b> IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="image"><img alt="" src="../../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/300px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png" decoding="async" width="300" height="214" class="thumbimage" srcset="../../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/450px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 1.5x, ../../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/600px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="internal" title="Enlarge"></a></div><b>Figure 3:</b> Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="image"><img alt="" src="../../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/300px-Ioctl-VFIO_GROUP_GET_FD.png" decoding="async" width="300" height="204" class="thumbimage" srcset="../../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/450px-Ioctl-VFIO_GROUP_GET_FD.png 1.5x, ../../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/600px-Ioctl-VFIO_GROUP_GET_FD.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="internal" title="Enlarge"></a></div><b>Figure 4:</b> Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 1:</b> Binding devices to the vfio-pci driver results in VFIO group nodes. +</p><p>Opening the file "/dev/vfio/vfio" creates a VFIO Container. +</p><p><b>Figure 2:</b> The interrupt routine <b><code>IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER)</code></b> places the VFIO group inside the VFIO container. +</p> +<h3><span class="mw-headline" id="Programming_the_IOMMU">Programming the IOMMU</span></h3> +<p>When this has been done <b><code>IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU)</code></b> can then be used to set an IOMMU type for the container which places it in a user interactable state. +</p><p>Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +</p> +<h3><span class="mw-headline" id="VFIO_Memory_Mapped_IO">VFIO Memory Mapped IO</span></h3> +<p><b>Figure 3:</b> Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using <b><code>IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP)</code></b> for map/pin and <b><code>IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP)</code></b> for unmap/unpin. +</p> +<h3><span class="mw-headline" id="Getting_the_VFIO_Group_File_Descriptor">Getting the VFIO Group File Descriptor</span></h3> +<p><b>Figure 4:</b> Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +</p> +<h3><span class="mw-headline" id="VFIO_device_file_descriptor">VFIO device file descriptor</span></h3> +<p>VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +</p><p>In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +</p> +<table class="wikitable"> +<caption>BAR regions in a VGA PCI device. +</caption> +<tbody><tr> +<th>00:00.0 VGA compatible controller +</th></tr> +<tr> +<td>Region 0 Bar0 (Config Space) starts at offset 0 +</td></tr> +<tr> +<td>Region 1 Bar1 (MSI - Message Signaled Interrupts) +</td></tr> +<tr> +<td>Region 2 Bar2 (MSIX) +</td></tr> +<tr> +<td>Region 3 Bar3 +</td></tr> +<tr> +<td>Region 4 Bar4 +</td></tr> +<tr> +<td>Region 5 Bar5 (IO port space) +</td></tr> +<tr> +<td>Expansion ROM +</td></tr></tbody></table> +<p>Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +</p> +<table class="wikitable"> +<caption>VFIO representation of PCI BAR regions offsets. +</caption> +<tbody><tr> +<th colspan="5"><- File Offset -> +</th></tr> +<tr> +<th>0 -> A +</th> +<th>A -> (A+B) +</th> +<th>(A+B) -> (A+B+C) +</th> +<th>(A+B+C) -> (A+B+C+D) +</th> +<th>... +</th></tr> +<tr> +<td>Region 0 (size A) +</td> +<td>Region 1 (size B) +</td> +<td>Region 2 (size C) +</td> +<td>Region 3 (size D) +</td> +<td>... +</td></tr></tbody></table> +<h3><span class="mw-headline" id="VFIO_Interrupts">VFIO Interrupts</span></h3> +<p>Guests communicate with the host via VFIO Interrupt Requests (<a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt_request_(PC_architecture)">IRQs</a>). These are sent via an irqfd (IRQ <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">File Descriptor</a>). Similarly, the host receives these interrupts via <a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> (Event File Descriptor). The resulting data can be returned via a <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callback</a>. +</p> +<h4><span class="mw-headline" id="IRQs">IRQs</span></h4> +<p>Device properties discovered via interrupt (IOCTL). +</p> +<h5><span class="mw-headline" id="Get_Device_Info">Get Device Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_device_info +</td></tr> +<tr> +<td rowspan="7"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="3"> +</td> +<td>VFIO_DEVICE_FLAGS_PCI +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_PLATFORM +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_RESET +</td></tr> +<tr> +<td>num_irqs +</td> +<td> +</td></tr> +<tr> +<td>num_regions +</td> +<td> +</td></tr></tbody></table> +<p>The IRQ <b><code>VFIO_DEVICE_GET_INFO</code></b> can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L194">here (vfio.h)</a></b>. +</p><p><b>Sample mdev code</b> to service this request can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L470">here</a></b>, and <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L522">here</a></b>. +</p> +<h5><span class="mw-headline" id="Get_Region_Info">Get Region Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_REGION_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_region_info +</td></tr> +<tr> +<td rowspan="10"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>cap_offset +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_REGION_INFO_FLAG_CAPS +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_MMAP +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_READ +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_WRITE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>offset +</td> +<td> +</td></tr> +<tr> +<td>size +</td> +<td> +</td></tr></tbody></table> +<p>Once the interrupt user knows the number of regions within a VFIO device they can use IRQ <b><code>VFIO_DEVICE_GET_REGION_INFO</code></b> to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +</p><p>The upstream API can be read <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L240"><b>here (vfio.h)</b></a>. +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L425"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L545"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Get_IRQ_Info">Get IRQ Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_IRQ_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_info +</td></tr> +<tr> +<td rowspan="8"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_IRQ_INFO_AUTOMASKED +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_MASKABLE +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_NORESIZE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_GET_IRQ_INFO</b></code> is used to retrieve information about a device IRQ. +</p><p><b><code>VFIO_IRQ_INFO_AUTOMASKED</code></b> is used to mask interrupts when they occur to protect the host. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L480">here (vfio.h)</a></b> +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L463"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L570"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Set_IRQs">Set IRQs</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_SET_IRQS +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_set +</td></tr> +<tr> +<td rowspan="12"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>data[] +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="6"> +</td> +<td>VFIO_IRQ_SET_ACTION_MASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_TRIGGER +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_UNMASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_BOOL +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_NONE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>start +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_SET_IRQS</b></code> is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L524">here (vfio.h)</a></b>. +</p> +<h3><span id="Device_Decomposure.2FRecomposure"></span><span class="mw-headline" id="Device_Decomposure/Recomposure">Device Decomposure/Recomposure</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="image"><img alt="Figure 5: Device Decomposure and Recomposure via VFIO." src="../../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/300px-Device_Decomposure_and_Recomposure_via_VFIO.png" decoding="async" width="300" height="147" class="thumbimage" srcset="../../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/450px-Device_Decomposure_and_Recomposure_via_VFIO.png 1.5x, ../../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/600px-Device_Decomposure_and_Recomposure_via_VFIO.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="internal" title="Enlarge"></a></div><b>Figure 5:</b> Device Decomposure and Recomposure via VFIO. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 5:</b> Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +</p> +<h3><span id="Memory_Management_Unit_.28MMU.29"></span><span class="mw-headline" id="Memory_Management_Unit_(MMU)">Memory Management Unit (MMU)</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 275px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="../File:Figure_6-_MMU_-_GMMU_IOVA_translation-isolation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 6:</b> MMU - GMMU IOVA translation/isolation.</div></div></div> +<p><b>Figure 6:</b> This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +</p> +<h4><span id="MMIO_Isolation_.28Platform_MMU.29"></span><span class="mw-headline" id="MMIO_Isolation_(Platform_MMU)">MMIO Isolation (Platform MMU)</span></h4> +<p>The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Random-access_memory">Random Access Memory (RAM)</a>. MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +</p> +<h4><span id="VRAM_Isolation_.28GPU_GMMU.29"></span><span class="mw-headline" id="VRAM_Isolation_(GPU_GMMU)">VRAM Isolation (GPU GMMU)</span></h4> +<p>The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard <a href="https://en.wikipedia.org/wiki/Video_random_access_memory" class="extiw" title="wikipedia:Video random access memory">Video Random Access Memory (VRAM)</a>. Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +</p> +<h4><span id="Platform_MMIO_.3C-.3E_GPU_Shadow_Pages"></span><span class="mw-headline" id="Platform_MMIO_<->_GPU_Shadow_Pages">Platform MMIO <-> GPU Shadow Pages</span></h4> +<p>In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="image"><img alt="Figure 7: A depiction of region overlays within a VFIO file descriptor." src="../../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/300px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png" decoding="async" width="300" height="268" class="thumbimage" srcset="../../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/450px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 1.5x, ../../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/600px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 7:</b> A depiction of region overlays within a VFIO file descriptor. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span id="VFIO_Quirks_.28region_traps.29"></span><span class="mw-headline" id="VFIO_Quirks_(region_traps)">VFIO Quirks (region traps)</span></h3> +<p><b>Figure 7:</b> Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="image"><img alt="Peer-to-Peer DMA Isolation under IOMMU" src="../../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/300px-Screen_Shot_2022-05-06_at_10.46.59_AM.png" decoding="async" width="300" height="224" class="thumbimage" srcset="../../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/450px-Screen_Shot_2022-05-06_at_10.46.59_AM.png 1.5x, ../../images/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="internal" title="Enlarge"></a></div><b>Figure 8:</b> Peer-to-Peer DMA Isolation under IOMMU. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span class="mw-headline" id="Known_IOMMU_Issues">Known IOMMU Issues</span></h3> +<p><b>DMA Aliasing</b> +</p> +<ul><li>Not all devices generate unique IDs.</li> +<li>Not all devices generate IDs they should.<br /></li></ul> +<p><b>DMA Isolation</b> +</p> +<ul><li><b>Figure 8:</b> Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.</li></ul> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="image"><img alt="Figure 0: Approches to GPU Virtualization." src="../../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/300px-Figure_0-_Approches_to_GPU_Virtualization..png" decoding="async" width="300" height="153" class="thumbimage" srcset="../../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/450px-Figure_0-_Approches_to_GPU_Virtualization..png 1.5x, ../../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/600px-Figure_0-_Approches_to_GPU_Virtualization..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="internal" title="Enlarge"></a></div><b>Figure 0:</b> Approaches to GPU Virtualization. See slides from: <a rel="nofollow" class="external text" href="O_Internals.html#References_(Talks_&_Reading_Material)">[61]</a></div></div></div> +<h2><span class="mw-headline" id="Mdev_Mode">Mdev Mode</span></h2> +<p><b>Mdev Mode (VFIO Mediated Device)</b> is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_2">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +</p><p>See references 1, 7, 8, 17, 18, 19, 70 in the <a rel="nofollow" class="external text" href="../Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Mediated_Core">Mediated Core</span></h3> +<p>The mediated device framework made 3 major changes to the VFIO driver. +</p> +<ul><li><b>1: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_core.c">Mediated core module (new)</a></b> <br /> -Mediated bus driver, create mediated device. <br /> -Physical device interface for vendor callbacks. <br /> -Generic Mediated device management user interface (sysfs).</li> +<li><b>2: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_driver.c">Mediated device module (new)</a></b> <br /> -Manage created mediated device, fully compatible with VFIO user API (UAPI).</li> +<li><b>3: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/vfio_iommu_type1.c">VFIO IOMMU driver (enhancement)</a></b> <br /> -VFIO IOMMU API Type1 compatible, easy to extend to non-Type1.</li></ul> +<p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg03922.html"><b>lists.gnu.org Qemu-devel</b> mailing list archive</a>. +</p> +<h3><span class="mw-headline" id="Device_Initialization">Device Initialization</span></h3> +<p>This section will deal with how an Mdev driver is initialized. +</p><p><b>Sample mdev code</b> for device initialization can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L229">here</a></b>. +</p> +<h4><span class="mw-headline" id="Registering_VFIO_MDEV_as_a_driver">Registering VFIO MDEV as a driver</span></h4> +<p>VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +</p> +<h4><span class="mw-headline" id="Registering_PCIE_Device_with_the_Mediated_Core">Registering PCIE Device with the Mediated Core</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Mdev-gpu.png.html" class="image"><img alt="Registering the mediated device." src="../../images/thumb/7/75/Mdev-gpu.png/300px-Mdev-gpu.png" decoding="async" width="300" height="208" class="thumbimage" srcset="../../images/thumb/7/75/Mdev-gpu.png/450px-Mdev-gpu.png 1.5x, ../../images/thumb/7/75/Mdev-gpu.png/600px-Mdev-gpu.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Mdev-gpu.png.html" class="internal" title="Enlarge"></a></div><b>Figure 9:</b> Registering the mediated device. This step may be accomplished via the vendor driver or via <a rel="nofollow" class="external text" href="">GVM/Mdev-GPU</a> for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.</div></div></div> +<p><b>Figure 9:</b> The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span id="Registering_Mediated_Callbacks_.28CBs.29"></span><span class="mw-headline" id="Registering_Mediated_Callbacks_(CBs)">Registering Mediated Callbacks (CBs)</span></h4> +<p><b>Figure 9:</b> The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span class="mw-headline" id="Creating_a_Mediated_Device_via_mdev-sysfsdev_API">Creating a Mediated Device via mdev-sysfsdev API</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="image"><img alt="" src="../../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/300px-Echoing_a_UUID_into_the_sysfsdev_API.png" decoding="async" width="300" height="235" class="thumbimage" srcset="../../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/450px-Echoing_a_UUID_into_the_sysfsdev_API.png 1.5x, ../../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/600px-Echoing_a_UUID_into_the_sysfsdev_API.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="internal" title="Enlarge"></a></div><b>Figure 10:</b> Echoing a UUID into the mdev-sysfsdev API. This functionality is included in <a rel="nofollow" class="external text" href="https://github.com/mdevctl/mdevctl">mdevctl</a> and in <a rel="nofollow" class="external text" href=""></a>. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 10:</b> The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="image"><img alt="Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor." src="../../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/300px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png" decoding="async" width="300" height="231" class="thumbimage" srcset="../../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/450px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 1.5x, ../../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/600px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 11:</b> QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<h4><span class="mw-headline" id="QEMU_adds_VFIO_device_to_IOMMU_container-group">QEMU adds VFIO device to IOMMU container-group</span></h4> +<p><b>Figure 11:</b> When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +</p> +<h4><span class="mw-headline" id="QEMU_passes_mdev_device_file_descriptor_to_VM">QEMU passes mdev device file descriptor to VM</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="image"><img alt="Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine." src="../../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/300px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png" decoding="async" width="300" height="234" class="thumbimage" srcset="../../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/450px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 1.5x, ../../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/600px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="internal" title="Enlarge"></a></div><b>Figure 12:</b> QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 12:</b> Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +</p> +<h3><span class="mw-headline" id="Instruction_Execution">Instruction Execution</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Ioeventfd-and-irqfd.png.html" class="image"><img alt="" src="../../images/thumb/a/aa/Ioeventfd-and-irqfd.png/300px-Ioeventfd-and-irqfd.png" decoding="async" width="300" height="215" class="thumbimage" srcset="../../images/thumb/a/aa/Ioeventfd-and-irqfd.png/450px-Ioeventfd-and-irqfd.png 1.5x, ../../images/thumb/a/aa/Ioeventfd-and-irqfd.png/600px-Ioeventfd-and-irqfd.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Ioeventfd-and-irqfd.png.html" class="internal" title="Enlarge"></a></div><b>Figure 13:</b> A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From <a rel="nofollow" class="external text" href="http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">blog.allenx</a></div></div></div> +<p><b>Figure 13:</b> Mdev Mode moves instruction information across a virtual function (VF) device using <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Remote_procedure_call">Remote Procedure Calls</a> generally by way of <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt">software interrupt</a> (<a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">Interrupt Request File Descriptor (irqfd)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">IO Event File Descriptor (ioeventfd)</a>. +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +</p> +<h4><span class="mw-headline" id="IRQ_remapping">IRQ remapping</span></h4> +<p>Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +</p> +<h4><span class="mw-headline" id="Interrupt_Injection">Interrupt Injection</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p> +<h3><span class="mw-headline" id="Memory_Management">Memory Management</span></h3> +<p>Mdev memory management is handled by vendor driver software. +</p> +<h4><span class="mw-headline" id="Region_Passthrough">Region Passthrough</span></h4> +<p>Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +</p> +<h5><span class="mw-headline" id="Emulated_Regions">Emulated Regions</span></h5> +<p>Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L112">in this sample code</a>. +</p> +<h5><span class="mw-headline" id="Passthrough_Regions">Passthrough Regions</span></h5> +<p>Passthrough memory regions use direct communication requiring no VM-exit (fast). +</p> +<h5><span class="mw-headline" id="Region_Access">Region Access</span></h5> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="image"><img alt="Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs" src="../../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/300px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png" decoding="async" width="300" height="236" class="thumbimage" srcset="../../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/450px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 1.5x, ../../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/600px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="internal" title="Enlarge"></a></div><b>Figure 14:</b> QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 14:</b> QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 238px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="../File:Guest_driver_accessing_Mdev_MMIO_space_backed_by_mdev_file_descriptor_triggers_EPT_violation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 15:</b> Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 15:</b> The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="image"><img alt="Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver." src="../../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/300px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/450px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 1.5x, ../../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/600px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="internal" title="Enlarge"></a></div><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="image"><img alt="Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor." src="../../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/300px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/450px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 1.5x, ../../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/600px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 17:</b> QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 17:</b> QEMU convert request from KVM to R/W access to Mdev file descriptor. +</p> +<h4><span class="mw-headline" id="EPT_Page_Violations">EPT Page Violations</span></h4> +<p>Guest <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Memory-mapped_I/O">Memory Mapped IO (MMIO)</a> trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">Mdev File Descriptor (FD)</a>. Reads and writes are then handled by the host GPU device driver via mediated <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callbacks (CBs)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO-mdev</a>. +</p> +<h4><span class="mw-headline" id="Mediated_DMA_Translations">Mediated DMA Translations</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p><p>Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +</p><p><b>Figure 18:</b> Memory regions get added by QEMU. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Memory_Regions_Added_by_QEMU.png.html" class="image"><img alt="Memory Regions Added by QEMU" src="../../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/300px-Memory_Regions_Added_by_QEMU.png" decoding="async" width="300" height="225" class="thumbimage" srcset="../../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/450px-Memory_Regions_Added_by_QEMU.png 1.5x, ../../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/600px-Memory_Regions_Added_by_QEMU.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Memory_Regions_Added_by_QEMU.png.html" class="internal" title="Enlarge"></a></div><b>Figure 18:</b> Memory Regions Added by QEMU. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 19:</b> QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="image"><img alt="QEMU calls VFIO DMA MAP via Memory listener" src="../../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/300px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/450px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 1.5x, ../../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/600px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="internal" title="Enlarge"></a></div><b>Figure 19:</b> QEMU calls VFIO DMA MAP via Memory listener. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="../File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="image"><img alt="Type 1 IOMMU Tracks VA-GFN" src="../../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/300px-Type_1_IOMMU_Tracks_VA-GFN.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/450px-Type_1_IOMMU_Tracks_VA-GFN.png 1.5x, ../../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/600px-Type_1_IOMMU_Tracks_VA-GFN.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="../File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="internal" title="Enlarge"></a></div><b>Figure 20:</b> Type 1 IOMMU Tracks <VA, GFN>. See slides from: <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 20:</b> Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +</p> +<h3><span class="mw-headline" id="Scheduling">Scheduling</span></h3> +<p>Scheduling is handled by the host mdev driver. +</p> +<h3><span class="mw-headline" id="Kernel_API">Kernel API</span></h3> +<p>Kernel documentation used for implementing a VFIO Mediated Device may be found at <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/driver-api/vfio-mediated-device.html">kernel.org</a>. +</p> +<h3><span class="mw-headline" id="Sample_Code">Sample Code</span></h3> +<p>Sample code for various mdev implementations may be found below: +</p><p><b>Mediated Virtual PCI Display Host Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy.c">mdpy.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy-fb.c">mdpy-fb.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mbochs.c">mbochs.c</a>.</li></ol> +<p><b>Serial PCI Port-based Mediated Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mtty.c">mtty.c</a>.</li></ol> +<h6><span class="mw-headline" id="Compilation">Compilation</span></h6> +<p>To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +</p><p><code>make</code> +</p><p>When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +</p> +<h6><span class="mw-headline" id="Loading_Kernel_Modules">Loading Kernel Modules</span></h6> +<p>Now that you have compiled the kernel modules you may load them via the insmod command. +</p><p>For example to load the <b>mtty.ko</b> module run the following command from within the directory where you built the modules: +</p><p><code>insmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Unloading_Kernel_Modules">Unloading Kernel Modules</span></h6> +<p>To unload any of the kernel modules you may make use of the rmmod command. +</p><p>For example to unload the <b>mtty.ko</b> module run the following command: +</p><p><code>rmmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Additional_Documentation">Additional Documentation</span></h6> +<p>An additional guide explaining how to make use of the mtty.c sample code may be found at <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294#n308">line 308</a> of the kernel.org VFIO Mediated Device documentation. +</p> +<h3><span class="mw-headline" id="Mdev_Mode_Requirements">Mdev Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Software HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SR-IOV_Mode">SR-IOV Mode</span></h2> +<p><b>SR-IOV Mode (Single Root I/O Virtualization)</b> involves hardware assisted virtualization on I/O peripherals. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_3">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +</p><p>See reference 6 in the <a rel="nofollow" class="external text" href="../Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Instruction_Execution_2">Instruction Execution</span></h3> +<p>SR-IOV communicates instructions from a virtual function (VF) directly to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/PCI_configuration_space">PCI BAR</a>. +</p> +<h3><span class="mw-headline" id="Memory_Management_2">Memory Management</span></h3> +<p>Guests are presenting with passthrough memory regions by the device firmware. +</p> +<h3><span class="mw-headline" id="Scheduling_2">Scheduling</span></h3> +<p>Scheduling may be handled by the host mdev driver and/or the device firmware. +</p> +<h3><span class="mw-headline" id="SR-IOV_Mode_Requirements">SR-IOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SR-IOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SIOV_Mode">SIOV Mode</span></h2> +<p><b>SIOV (Scalable I/O Virtualization)</b> involves the combination of concepts form both <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> and <a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a> as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +</p><p><b>Revision 1.0 of the SIOV specification</b> can be read on the <a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Open Compute Project website</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_4">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +</p><p>See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the <a rel="nofollow" class="external text" href="../Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Memory_Management_3">Memory Management</span></h3> +<p>Enhancements to <a rel="nofollow" class="external text" href="https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/002/intel-virtualization-technology-for-directed-i-o/">Intel VT-d</a> introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (<a rel="nofollow" class="external text" href="../Mediated_Device_Internals.html#Memory_Management">mdev memory management</a>). This change is referred to as an IOMMU Aware Mediated Device. +</p> +<h4><span class="mw-headline" id="IOMMU_Aware_Mediated_Device">IOMMU Aware Mediated Device</span></h4> +<p>SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +</p><p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">mailing list archive on <b>lwn.net</b> under <b>(vfio/mdev: IOMMU aware mediated device)</b></a>. +</p> +<h4><span class="mw-headline" id="Shared_Hardware_Workqueues">Shared Hardware Workqueues</span></h4> +<p>SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +</p><p><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">According to <b>kernel.org</b></a>: <i>"In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function."</i> +</p> +<h3><span class="mw-headline" id="SIOV_Mode_Requirements">SIOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SIOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=Xs0TJU_sIPc">[2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede</a> - <a rel="nofollow" class="external text" href="https://www.linux-kvm.org/images/5/59/02x03-Neo_Jia_and_Kirti_Wankhede-vGPU_on_KVM-A_VFIO_based_Framework.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=WFkdTFTOTpA">[2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson</a> - <a rel="nofollow" class="external text" href="http://events17.linuxfoundation.org/sites/events/files/slides/An%20Introduction%20to%20PCI%20Device%20Assignment%20with%20VFIO%20-%20Williamson%20-%202016-08-30_0.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://events19.linuxfoundation.cn/wp-content/uploads/2017/11/Intel%C2%AE-Scalable-I_O-Virtualization_Kevin-Tian.pdf">[2017] Scalable I/O Virtualization by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=G6D-jaCs6sc">[2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu</a> - <a rel="nofollow" class="external text" href="https://static.sched.com/hosted_files/kvmforum2019/5e/Bring%20a%20scalable%20IOV%20capable%20device%20into%20Linux%20-%20KVM%202019.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Scalable I/O Virtualization Revision 1.0</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=_tB3EbFDcRQ">[2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue</a> - <a rel="nofollow" class="external text" href="https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Live-Migration-Support-for-GPU-with-SRIOV-Challenges-and-Solution-Zheng-Xiao-Alibaba-Cloud-Jerry-Jiang-Ken-Xue-AMD.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=UODxW1opfn0">[2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=DKYvQ3FdFeo">[2016] Qemu Graphics Update 2016 by Gerd Hoffmann</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a></li> +<li><a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/eventfd.c">root/virt/kvm/eventfd.c</a></li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">KVM: irqfd</a>)</li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">KVM: add ioeventfd support</a>)</li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220120223711/http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">KVM irqfd & ioeventfd</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio.rst">VFIO - Virtual Function I/O</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/vfio.c">root/virt/kvm/vfio.c</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO Mediated Devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">IOMMU Aware Mediated Device</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=95KSKrZM8oQ">Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=cHMLBcHplhk">[2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=KWRKx_uxUDI">[2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/auxiliary_bus.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294">Auxiliary Bus</a></li> +<li><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">Shared Virtual Addressing</a></li> +<li><a rel="nofollow" class="external text" href="https://vfio.blogspot.com/">vfio.blogspot.com</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/xengt.pdf">XenGT by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130721094438/http://labs.vmware.com/academic/publications/gpu-virtualization">VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman</a></li> +<li><a rel="nofollow" class="external text" href="https://pcisig.com/specifications/iov">PCI SIG I/O Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120108034526/http://sysweb.cs.toronto.edu/vmgl">VMGL by the University of Toronto Computer Science Department</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120518125815/http://www.nvidia.com/object/vgx-hypervisor.html">Kepler VGX Hypervisor</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090218010221/http://software.intel.com/en-us/articles/intel-virtualization-technology-for-directed-io-vt-d-enhancing-intel-platforms-for-efficient-virtualization-of-io-devices">Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/2001/0712/a/dma-interface.php3">DMA-Mapping.txt (Dynamic DMA Mapping)</a></li> +<li><a rel="nofollow" class="external text" href="https://events.static.linuxfound.org/slides/2011/linuxcon-japan/lcj2011_guangrong.pdf">KVM MMU Virtualization by Xiao Guangrong</a></li> +<li><a rel="nofollow" class="external text" href="https://wiki.osdev.org/PCI">OSDEV: PCI</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1">Down to the TLP: How PCI express devices talk (Part I)</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2">Down to the TLP: How PCI express devices talk (Part II)</a></li> +<li><a rel="nofollow" class="external text" href="https://projectacrn.github.io/latest/tutorials/sriov_virtualization.html">Intel ACRN: Enabling SR-IOV Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://docs.kernel.org/admin-guide/abi-testing.html#abi-file-testing-sysfs-bus-pci">Kernel.org sysfs-bus-pci</a></li> +<li><a rel="nofollow" class="external text" href="https://linux-kernel-labs.github.io/refs/heads/master/labs/memory_mapping.html">Linux Kernel Labs: Memory Mapping</a></li> +<li><a rel="nofollow" class="external text" href="https://rayanfam.com/topics/inside-windows-page-frame-number-part1/">Inside Windows Page Frame Number (PFN) - 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\ No newline at end of file diff --git a/wiki/open-iov.org/index.php/Virtual_IO_Internals.html b/wiki/open-iov.org/index.php/Virtual_IO_Internals.html new file mode 100644 index 0000000..9975a3e --- /dev/null +++ b/wiki/open-iov.org/index.php/Virtual_IO_Internals.html @@ -0,0 +1,1014 @@ +<!DOCTYPE html> +<html class="client-nojs" lang="en" dir="ltr"> +<head> +<meta charset="UTF-8"/> +<title>Virtual I/O Internals - Open-IOV</title> +<script>document.documentElement.className="client-js";RLCONF={"wgBreakFrames":!1,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy","wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"277bc3d96654d846f7908b2b","wgCSPNonce":!1,"wgCanonicalNamespace":"","wgCanonicalSpecialPageName":!1,"wgNamespaceNumber":0,"wgPageName":"Virtual_I/O_Internals","wgTitle":"Virtual I/O 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id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Virtual I/O Internals</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"><span class="mw-redirectedfrom">(Redirected from <a href="../index.php%3Ftitle=Virtual_IO_Internals&redirect=no.html" class="mw-redirect" title="Virtual IO Internals">Virtual IO Internals</a>)</span></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Virtual_IO_Internals.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Virtual_IO_Internals.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>The following document details the internals of a <b>VFIO (Virtual Function I/O)</b> driven <b>Shared</b> <b>I/O Device.</b></p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<p>This article places emphasis on the <b>Virtual GPU (vGPU)</b> use case however these concepts apply generically to virtualization of I/O devices (TPUs, NICs, storage peripherals, ect..). +</p> +<table class="wikitable"> +<caption>Comparison of Assistance Modes +</caption> +<tbody><tr> +<th>Mdev Mode +</th> +<th>SR-IOV Mode +</th> +<th>SIOV Mode +</th></tr> +<tr> +<td>No hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td> +<td>Hardware assistance needed. +</td></tr> +<tr> +<td>Host requires insight about guest workload. +</td> +<td>Host ignorance of guest workload. +</td> +<td>Host requires insight about guest workload. +</td></tr> +<tr> +<td>Error reporting. +</td> +<td>No guest driver error reporting. +</td> +<td>Error reporting. +</td></tr> +<tr> +<td>In depth dynamic monitoring. +</td> +<td>Basic dynamic monitoring. +</td> +<td>In depth dynamic monitoring. +</td></tr> +<tr> +<td>Software defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td> +<td>Firmware defined MMU guest separation. +</td></tr> +<tr> +<td>Requires deferred instructions to be supported by host software (support libraries). +</td> +<td>Guest is ignorant of host supported software such as support libraries. +</td> +<td> +</td></tr> +<tr> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td> +<td>Routing interrupts. +</td></tr> +<tr> +<td>Device reset. +</td> +<td>Device reset. +</td> +<td>Device reset. +</td></tr> +<tr> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td> +<td>Enable/Disable device. +</td></tr> +<tr> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td> +<td>Support for multiple scheduling techniques. +</td></tr> +<tr> +<td>Single PCI requester ID. +</td> +<td>Multiple PCI requester IDs. +</td> +<td>Multiple PCI requester IDs. +</td></tr></tbody></table> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Virtual_IO_Internals.html#All_Modes"><span class="tocnumber">1</span> <span class="toctext">All Modes</span></a> +<ul> +<li class="toclevel-2 tocsection-2"><a href="Virtual_IO_Internals.html#Knowledge_Resources_Used"><span class="tocnumber">1.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-3"><a href="Virtual_IO_Internals.html#Binding_VFIO_devices"><span class="tocnumber">1.2</span> <span class="toctext">Binding VFIO devices</span></a></li> +<li class="toclevel-2 tocsection-4"><a href="Virtual_IO_Internals.html#Programming_the_IOMMU"><span class="tocnumber">1.3</span> <span class="toctext">Programming the IOMMU</span></a></li> +<li class="toclevel-2 tocsection-5"><a href="Virtual_IO_Internals.html#VFIO_Memory_Mapped_IO"><span class="tocnumber">1.4</span> <span class="toctext">VFIO Memory Mapped IO</span></a></li> +<li class="toclevel-2 tocsection-6"><a href="Virtual_IO_Internals.html#Getting_the_VFIO_Group_File_Descriptor"><span class="tocnumber">1.5</span> <span class="toctext">Getting the VFIO Group File Descriptor</span></a></li> +<li class="toclevel-2 tocsection-7"><a href="Virtual_IO_Internals.html#VFIO_device_file_descriptor"><span class="tocnumber">1.6</span> <span class="toctext">VFIO device file descriptor</span></a></li> +<li class="toclevel-2 tocsection-8"><a href="Virtual_IO_Internals.html#VFIO_Interrupts"><span class="tocnumber">1.7</span> <span class="toctext">VFIO Interrupts</span></a> +<ul> +<li class="toclevel-3 tocsection-9"><a href="Virtual_IO_Internals.html#IRQs"><span class="tocnumber">1.7.1</span> <span class="toctext">IRQs</span></a> +<ul> +<li class="toclevel-4 tocsection-10"><a href="Virtual_IO_Internals.html#Get_Device_Info"><span class="tocnumber">1.7.1.1</span> <span class="toctext">Get Device Info</span></a></li> +<li class="toclevel-4 tocsection-11"><a href="Virtual_IO_Internals.html#Get_Region_Info"><span class="tocnumber">1.7.1.2</span> <span class="toctext">Get Region Info</span></a></li> +<li class="toclevel-4 tocsection-12"><a href="Virtual_IO_Internals.html#Get_IRQ_Info"><span class="tocnumber">1.7.1.3</span> <span class="toctext">Get IRQ Info</span></a></li> +<li class="toclevel-4 tocsection-13"><a href="Virtual_IO_Internals.html#Set_IRQs"><span class="tocnumber">1.7.1.4</span> <span class="toctext">Set IRQs</span></a></li> +</ul> +</li> +</ul> +</li> +<li class="toclevel-2 tocsection-14"><a href="Virtual_IO_Internals.html#Device_Decomposure/Recomposure"><span class="tocnumber">1.8</span> <span class="toctext">Device Decomposure/Recomposure</span></a></li> +<li class="toclevel-2 tocsection-15"><a href="Virtual_IO_Internals.html#Memory_Management_Unit_(MMU)"><span class="tocnumber">1.9</span> <span class="toctext">Memory Management Unit (MMU)</span></a> +<ul> +<li class="toclevel-3 tocsection-16"><a href="Virtual_IO_Internals.html#MMIO_Isolation_(Platform_MMU)"><span class="tocnumber">1.9.1</span> <span class="toctext">MMIO Isolation (Platform MMU)</span></a></li> +<li class="toclevel-3 tocsection-17"><a href="Virtual_IO_Internals.html#VRAM_Isolation_(GPU_GMMU)"><span class="tocnumber">1.9.2</span> <span class="toctext">VRAM Isolation (GPU GMMU)</span></a></li> +<li class="toclevel-3 tocsection-18"><a href="Virtual_IO_Internals.html#Platform_MMIO_<->_GPU_Shadow_Pages"><span class="tocnumber">1.9.3</span> <span class="toctext">Platform MMIO <-> GPU Shadow Pages</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-19"><a href="Virtual_IO_Internals.html#VFIO_Quirks_(region_traps)"><span class="tocnumber">1.10</span> <span class="toctext">VFIO Quirks (region traps)</span></a></li> +<li class="toclevel-2 tocsection-20"><a href="Virtual_IO_Internals.html#Known_IOMMU_Issues"><span class="tocnumber">1.11</span> <span class="toctext">Known IOMMU Issues</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-21"><a href="Virtual_IO_Internals.html#Mdev_Mode"><span class="tocnumber">2</span> <span class="toctext">Mdev Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-22"><a href="Virtual_IO_Internals.html#Knowledge_Resources_Used_2"><span class="tocnumber">2.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-23"><a href="Virtual_IO_Internals.html#Mediated_Core"><span class="tocnumber">2.2</span> <span class="toctext">Mediated Core</span></a></li> +<li class="toclevel-2 tocsection-24"><a href="Virtual_IO_Internals.html#Device_Initialization"><span class="tocnumber">2.3</span> <span class="toctext">Device Initialization</span></a> +<ul> +<li class="toclevel-3 tocsection-25"><a href="Virtual_IO_Internals.html#Registering_VFIO_MDEV_as_a_driver"><span class="tocnumber">2.3.1</span> <span class="toctext">Registering VFIO MDEV as a driver</span></a></li> +<li class="toclevel-3 tocsection-26"><a href="Virtual_IO_Internals.html#Registering_PCIE_Device_with_the_Mediated_Core"><span class="tocnumber">2.3.2</span> <span class="toctext">Registering PCIE Device with the Mediated Core</span></a></li> +<li class="toclevel-3 tocsection-27"><a href="Virtual_IO_Internals.html#Registering_Mediated_Callbacks_(CBs)"><span class="tocnumber">2.3.3</span> <span class="toctext">Registering Mediated Callbacks (CBs)</span></a></li> +<li class="toclevel-3 tocsection-28"><a href="Virtual_IO_Internals.html#Creating_a_Mediated_Device_via_mdev-sysfsdev_API"><span class="tocnumber">2.3.4</span> <span class="toctext">Creating a Mediated Device via mdev-sysfsdev API</span></a></li> +<li class="toclevel-3 tocsection-29"><a href="Virtual_IO_Internals.html#QEMU_adds_VFIO_device_to_IOMMU_container-group"><span class="tocnumber">2.3.5</span> <span class="toctext">QEMU adds VFIO device to IOMMU container-group</span></a></li> +<li class="toclevel-3 tocsection-30"><a href="Virtual_IO_Internals.html#QEMU_passes_mdev_device_file_descriptor_to_VM"><span class="tocnumber">2.3.6</span> <span class="toctext">QEMU passes mdev device file descriptor to VM</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-31"><a href="Virtual_IO_Internals.html#Instruction_Execution"><span class="tocnumber">2.4</span> <span class="toctext">Instruction Execution</span></a> +<ul> +<li class="toclevel-3 tocsection-32"><a href="Virtual_IO_Internals.html#IRQ_remapping"><span class="tocnumber">2.4.1</span> <span class="toctext">IRQ remapping</span></a></li> +<li class="toclevel-3 tocsection-33"><a href="Virtual_IO_Internals.html#Interrupt_Injection"><span class="tocnumber">2.4.2</span> <span class="toctext">Interrupt Injection</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-34"><a href="Virtual_IO_Internals.html#Memory_Management"><span class="tocnumber">2.5</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-35"><a href="Virtual_IO_Internals.html#Region_Passthrough"><span class="tocnumber">2.5.1</span> <span class="toctext">Region Passthrough</span></a> +<ul> +<li class="toclevel-4 tocsection-36"><a href="Virtual_IO_Internals.html#Emulated_Regions"><span class="tocnumber">2.5.1.1</span> <span class="toctext">Emulated Regions</span></a></li> +<li class="toclevel-4 tocsection-37"><a href="Virtual_IO_Internals.html#Passthrough_Regions"><span class="tocnumber">2.5.1.2</span> <span class="toctext">Passthrough Regions</span></a></li> +<li class="toclevel-4 tocsection-38"><a href="Virtual_IO_Internals.html#Region_Access"><span class="tocnumber">2.5.1.3</span> <span class="toctext">Region Access</span></a></li> +</ul> +</li> +<li class="toclevel-3 tocsection-39"><a href="Virtual_IO_Internals.html#EPT_Page_Violations"><span class="tocnumber">2.5.2</span> <span class="toctext">EPT Page Violations</span></a></li> +<li class="toclevel-3 tocsection-40"><a href="Virtual_IO_Internals.html#Mediated_DMA_Translations"><span class="tocnumber">2.5.3</span> <span class="toctext">Mediated DMA Translations</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-41"><a href="Virtual_IO_Internals.html#Scheduling"><span class="tocnumber">2.6</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-42"><a href="Virtual_IO_Internals.html#Kernel_API"><span class="tocnumber">2.7</span> <span class="toctext">Kernel API</span></a></li> +<li class="toclevel-2 tocsection-43"><a href="Virtual_IO_Internals.html#Sample_Code"><span class="tocnumber">2.8</span> <span class="toctext">Sample Code</span></a> +<ul> +<li class="toclevel-3 tocsection-44"><a href="Virtual_IO_Internals.html#Compilation"><span class="tocnumber">2.8.1</span> <span class="toctext">Compilation</span></a></li> +<li class="toclevel-3 tocsection-45"><a href="Virtual_IO_Internals.html#Loading_Kernel_Modules"><span class="tocnumber">2.8.2</span> <span class="toctext">Loading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-46"><a href="Virtual_IO_Internals.html#Unloading_Kernel_Modules"><span class="tocnumber">2.8.3</span> <span class="toctext">Unloading Kernel Modules</span></a></li> +<li class="toclevel-3 tocsection-47"><a href="Virtual_IO_Internals.html#Additional_Documentation"><span class="tocnumber">2.8.4</span> <span class="toctext">Additional Documentation</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-48"><a href="Virtual_IO_Internals.html#Mdev_Mode_Requirements"><span class="tocnumber">2.9</span> <span class="toctext">Mdev Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-49"><a href="Virtual_IO_Internals.html#SR-IOV_Mode"><span class="tocnumber">3</span> <span class="toctext">SR-IOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-50"><a href="Virtual_IO_Internals.html#Knowledge_Resources_Used_3"><span class="tocnumber">3.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-51"><a href="Virtual_IO_Internals.html#Instruction_Execution_2"><span class="tocnumber">3.2</span> <span class="toctext">Instruction Execution</span></a></li> +<li class="toclevel-2 tocsection-52"><a href="Virtual_IO_Internals.html#Memory_Management_2"><span class="tocnumber">3.3</span> <span class="toctext">Memory Management</span></a></li> +<li class="toclevel-2 tocsection-53"><a href="Virtual_IO_Internals.html#Scheduling_2"><span class="tocnumber">3.4</span> <span class="toctext">Scheduling</span></a></li> +<li class="toclevel-2 tocsection-54"><a href="Virtual_IO_Internals.html#SR-IOV_Mode_Requirements"><span class="tocnumber">3.5</span> <span class="toctext">SR-IOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-55"><a href="Virtual_IO_Internals.html#SIOV_Mode"><span class="tocnumber">4</span> <span class="toctext">SIOV Mode</span></a> +<ul> +<li class="toclevel-2 tocsection-56"><a href="Virtual_IO_Internals.html#Knowledge_Resources_Used_4"><span class="tocnumber">4.1</span> <span class="toctext">Knowledge Resources Used</span></a></li> +<li class="toclevel-2 tocsection-57"><a href="Virtual_IO_Internals.html#Memory_Management_3"><span class="tocnumber">4.2</span> <span class="toctext">Memory Management</span></a> +<ul> +<li class="toclevel-3 tocsection-58"><a href="Virtual_IO_Internals.html#IOMMU_Aware_Mediated_Device"><span class="tocnumber">4.2.1</span> <span class="toctext">IOMMU Aware Mediated Device</span></a></li> +<li class="toclevel-3 tocsection-59"><a href="Virtual_IO_Internals.html#Shared_Hardware_Workqueues"><span class="tocnumber">4.2.2</span> <span class="toctext">Shared Hardware Workqueues</span></a></li> +</ul> +</li> +<li class="toclevel-2 tocsection-60"><a href="Virtual_IO_Internals.html#SIOV_Mode_Requirements"><span class="tocnumber">4.3</span> <span class="toctext">SIOV Mode Requirements</span></a></li> +</ul> +</li> +<li class="toclevel-1 tocsection-61"><a href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)"><span class="tocnumber">5</span> <span class="toctext">References (Talks & Reading Material)</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="All_Modes">All Modes</span></h2> +<p>This section will cover concepts which apply both to <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a>, <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> & <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SIOV_Mode">SIOV Mode</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Alex Williamson. +</p><p>See references 2, 14, & 22 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Binding_VFIO_devices">Binding VFIO devices</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Vfio-pci_driver_bindings.png.html" class="image"><img alt="" src="../images/thumb/9/9e/Vfio-pci_driver_bindings.png/300px-Vfio-pci_driver_bindings.png" decoding="async" width="300" height="218" class="thumbimage" srcset="../images/thumb/9/9e/Vfio-pci_driver_bindings.png/450px-Vfio-pci_driver_bindings.png 1.5x, ../images/thumb/9/9e/Vfio-pci_driver_bindings.png/600px-Vfio-pci_driver_bindings.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Vfio-pci_driver_bindings.png.html" class="internal" title="Enlarge"></a></div><b>Figure 1:</b> VFIO group nodes are unit of ownership that VFIO uses. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:IOCTL_set_VFIO_container.png.html" class="image"><img alt="" src="../images/thumb/3/33/IOCTL_set_VFIO_container.png/300px-IOCTL_set_VFIO_container.png" decoding="async" width="300" height="242" class="thumbimage" srcset="../images/thumb/3/33/IOCTL_set_VFIO_container.png/450px-IOCTL_set_VFIO_container.png 1.5x, ../images/thumb/3/33/IOCTL_set_VFIO_container.png/600px-IOCTL_set_VFIO_container.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:IOCTL_set_VFIO_container.png.html" class="internal" title="Enlarge"></a></div><b>Figure 2:</b> IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER) places the VFIO Group inside the VFIO Container. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="image"><img alt="" src="../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/300px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png" decoding="async" width="300" height="214" class="thumbimage" srcset="../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/450px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 1.5x, ../images/thumb/4/40/Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png/600px-Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioctl-VFIO_IOMMU_MAP-UNMAP_DMA.png.html" class="internal" title="Enlarge"></a></div><b>Figure 3:</b> Using interrupts IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP), IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP) to map memory and pin pages. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="image"><img alt="" src="../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/300px-Ioctl-VFIO_GROUP_GET_FD.png" decoding="async" width="300" height="204" class="thumbimage" srcset="../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/450px-Ioctl-VFIO_GROUP_GET_FD.png 1.5x, ../images/thumb/3/3f/Ioctl-VFIO_GROUP_GET_FD.png/600px-Ioctl-VFIO_GROUP_GET_FD.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioctl-VFIO_GROUP_GET_FD.png.html" class="internal" title="Enlarge"></a></div><b>Figure 4:</b> Using interrupt IOCTL(GROUP2, VFIO_GROUP_GET_FD, "0000:01:00.0") to obtain the VFIO Group file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 1:</b> Binding devices to the vfio-pci driver results in VFIO group nodes. +</p><p>Opening the file "/dev/vfio/vfio" creates a VFIO Container. +</p><p><b>Figure 2:</b> The interrupt routine <b><code>IOCTL(GROUP, VFIO_GROUP_SET_CONTAINER, &CONTAINER)</code></b> places the VFIO group inside the VFIO container. +</p> +<h3><span class="mw-headline" id="Programming_the_IOMMU">Programming the IOMMU</span></h3> +<p>When this has been done <b><code>IOCTL(CONTAINER, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU)</code></b> can then be used to set an IOMMU type for the container which places it in a user interactable state. +</p><p>Once this IOMMU type state has been set and the VFIO container has been made interactable additional VFIO groups may be added to the container without requiring that the group's IOMMU type be set again as newly added groups automatically inherit the container's IOMMU context. +</p> +<h3><span class="mw-headline" id="VFIO_Memory_Mapped_IO">VFIO Memory Mapped IO</span></h3> +<p><b>Figure 3:</b> Once the VFIO Groups have been placed inside the VFIO container and the IOMMU type has been set the user may then map and unmap which will automatically inserts Memory Mapped IO (MMIO) entries into the IOMMU as well as pin/unpin pages as necessary. This can be accomplished using <b><code>IOCTL(CONTAINER, VFIO_IOMMU_MAP_DMA, &MAP)</code></b> for map/pin and <b><code>IOCTL(CONTAINER, VFIO_IOMMU_UNMAP_DMA, &UNMAP)</code></b> for unmap/unpin. +</p> +<h3><span class="mw-headline" id="Getting_the_VFIO_Group_File_Descriptor">Getting the VFIO Group File Descriptor</span></h3> +<p><b>Figure 4:</b> Once the device has been bound to a VFIO driver, set in a VFIO container, the VFIO container has it's IOMMU type set, and a memory map/page pin of the VFIO device has been completed a file descriptor can then be obtained for the device. This file descriptor can be used for interrupts (ioctls), to probe for information about the BAR regions, and configure the IRQs. +</p> +<h3><span class="mw-headline" id="VFIO_device_file_descriptor">VFIO device file descriptor</span></h3> +<p>VFIO device file descriptors are divided into regions and each region is mapped into a device resource. Region count and info (file offset, allowable access, ect..) can be discovered through interrupt (IOCTL). Each file descriptor region corresponding to a PCI resource is represented as a file offset. +</p><p>In the case of RPC Mode this structure is emulated whereas in SR-IOV Mode the structure is mapped to a real PCI resource. +</p> +<table class="wikitable"> +<caption>BAR regions in a VGA PCI device. +</caption> +<tbody><tr> +<th>00:00.0 VGA compatible controller +</th></tr> +<tr> +<td>Region 0 Bar0 (Config Space) starts at offset 0 +</td></tr> +<tr> +<td>Region 1 Bar1 (MSI - Message Signaled Interrupts) +</td></tr> +<tr> +<td>Region 2 Bar2 (MSIX) +</td></tr> +<tr> +<td>Region 3 Bar3 +</td></tr> +<tr> +<td>Region 4 Bar4 +</td></tr> +<tr> +<td>Region 5 Bar5 (IO port space) +</td></tr> +<tr> +<td>Expansion ROM +</td></tr></tbody></table> +<p>Below is what the file offsets looks like internally for each BAR region starting from address 0 and growing with the addition of former regions as you progress through the file. +</p> +<table class="wikitable"> +<caption>VFIO representation of PCI BAR regions offsets. +</caption> +<tbody><tr> +<th colspan="5"><- File Offset -> +</th></tr> +<tr> +<th>0 -> A +</th> +<th>A -> (A+B) +</th> +<th>(A+B) -> (A+B+C) +</th> +<th>(A+B+C) -> (A+B+C+D) +</th> +<th>... +</th></tr> +<tr> +<td>Region 0 (size A) +</td> +<td>Region 1 (size B) +</td> +<td>Region 2 (size C) +</td> +<td>Region 3 (size D) +</td> +<td>... +</td></tr></tbody></table> +<h3><span class="mw-headline" id="VFIO_Interrupts">VFIO Interrupts</span></h3> +<p>Guests communicate with the host via VFIO Interrupt Requests (<a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt_request_(PC_architecture)">IRQs</a>). These are sent via an irqfd (IRQ <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">File Descriptor</a>). Similarly, the host receives these interrupts via <a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> (Event File Descriptor). The resulting data can be returned via a <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callback</a>. +</p> +<h4><span class="mw-headline" id="IRQs">IRQs</span></h4> +<p>Device properties discovered via interrupt (IOCTL). +</p> +<h5><span class="mw-headline" id="Get_Device_Info">Get Device Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_device_info +</td></tr> +<tr> +<td rowspan="7"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="3"> +</td> +<td>VFIO_DEVICE_FLAGS_PCI +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_PLATFORM +</td></tr> +<tr> +<td>VFIO_DEVICE_FLAGS_RESET +</td></tr> +<tr> +<td>num_irqs +</td> +<td> +</td></tr> +<tr> +<td>num_regions +</td> +<td> +</td></tr></tbody></table> +<p>The IRQ <b><code>VFIO_DEVICE_GET_INFO</code></b> can provide information to distinguish between PCI and platform devices as well as the number of regions and IRQs for a particular device. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L194">here (vfio.h)</a></b>. +</p><p><b>Sample mdev code</b> to service this request can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L470">here</a></b>, and <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L522">here</a></b>. +</p> +<h5><span class="mw-headline" id="Get_Region_Info">Get Region Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_REGION_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_region_info +</td></tr> +<tr> +<td rowspan="10"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>cap_offset +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_REGION_INFO_FLAG_CAPS +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_MMAP +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_READ +</td></tr> +<tr> +<td>VFIO_REGION_INFO_FLAG_WRITE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>offset +</td> +<td> +</td></tr> +<tr> +<td>size +</td> +<td> +</td></tr></tbody></table> +<p>Once the interrupt user knows the number of regions within a VFIO device they can use IRQ <b><code>VFIO_DEVICE_GET_REGION_INFO</code></b> to probe each region for additional information. This interrupt will return information such as if it can be read from or written to, if the device supports MMAP, as well as what the offset and size of the region is within the VFIO file descriptor. +</p><p>The upstream API can be read <a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L240"><b>here (vfio.h)</b></a>. +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L425"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L545"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Get_IRQ_Info">Get IRQ Info</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_GET_IRQ_INFO +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_info +</td></tr> +<tr> +<td rowspan="8"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="4"> +</td> +<td>VFIO_IRQ_INFO_AUTOMASKED +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_MASKABLE +</td></tr> +<tr> +<td>VFIO_IRQ_INFO_NORESIZE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_GET_IRQ_INFO</b></code> is used to retrieve information about a device IRQ. +</p><p><b><code>VFIO_IRQ_INFO_AUTOMASKED</code></b> is used to mask interrupts when they occur to protect the host. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L480">here (vfio.h)</a></b> +</p><p><b>Sample mdev code</b> to service this request can be found <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L463"><b>here</b></a>, and <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L570"><b>here</b></a>. +</p> +<h5><span class="mw-headline" id="Set_IRQs">Set IRQs</span></h5> +<table class="wikitable"> +<caption> +</caption> +<tbody><tr> +<th colspan="3">VFIO_DEVICE_SET_IRQS +</th></tr> +<tr> +<td colspan="3">struct vfio_irq_set +</td></tr> +<tr> +<td rowspan="12"> +</td> +<td>argz +</td> +<td> +</td></tr> +<tr> +<td>count +</td> +<td> +</td></tr> +<tr> +<td>data[] +</td> +<td> +</td></tr> +<tr> +<td>flags +</td> +<td> +</td></tr> +<tr> +<td rowspan="6"> +</td> +<td>VFIO_IRQ_SET_ACTION_MASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_TRIGGER +</td></tr> +<tr> +<td>VFIO_IRQ_SET_ACTION_UNMASK +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_BOOL +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_EVENTFD +</td></tr> +<tr> +<td>VFIO_IRQ_SET_DATA_NONE +</td></tr> +<tr> +<td>index +</td> +<td> +</td></tr> +<tr> +<td>start +</td> +<td> +</td></tr></tbody></table> +<p><code><b>VFIO_DEVICE_SET_IRQS</b></code> is used to setup IRQs. Actions can be configured such as trigger which is when the device triggers an interrupt (IOCTL), masking and unmasking actions can be set. Bool and None data types are used for loopback testing of the device. Start and index may be used to modify subregions. +</p><p>The upstream API can be read <b><a rel="nofollow" class="external text" href="https://github.com/torvalds/linux/blob/47700948a4abb4a5ae13ef943ff682a7f327547a/include/uapi/linux/vfio.h#L524">here (vfio.h)</a></b>. +</p> +<h3><span id="Device_Decomposure.2FRecomposure"></span><span class="mw-headline" id="Device_Decomposure/Recomposure">Device Decomposure/Recomposure</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="image"><img alt="Figure 5: Device Decomposure and Recomposure via VFIO." src="../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/300px-Device_Decomposure_and_Recomposure_via_VFIO.png" decoding="async" width="300" height="147" class="thumbimage" srcset="../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/450px-Device_Decomposure_and_Recomposure_via_VFIO.png 1.5x, ../images/thumb/9/90/Device_Decomposure_and_Recomposure_via_VFIO.png/600px-Device_Decomposure_and_Recomposure_via_VFIO.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Device_Decomposure_and_Recomposure_via_VFIO.png.html" class="internal" title="Enlarge"></a></div><b>Figure 5:</b> Device Decomposure and Recomposure via VFIO. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<p><b>Figure 5:</b> Virtual Function IO (VFIO) devices are deconstructed in userspace into a set of VFIO primitives (MMIO pages, VFIO/IOMMU Groups, VFIO IRQs, File Descriptors). Recomposure of these devices occurs upon assignment of a Virtual Function (VF) to a QEMU virtual machine. +</p> +<h3><span id="Memory_Management_Unit_.28MMU.29"></span><span class="mw-headline" id="Memory_Management_Unit_(MMU)">Memory Management Unit (MMU)</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 275px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_6-_MMU_-_GMMU_IOVA_translation-isolation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 6:</b> MMU - GMMU IOVA translation/isolation.</div></div></div> +<p><b>Figure 6:</b> This section will touch upon the mechanisms used for enforcement of Host Physical Address (HPA) to Guest Physical Address (GPA) isolation. +</p> +<h4><span id="MMIO_Isolation_.28Platform_MMU.29"></span><span class="mw-headline" id="MMIO_Isolation_(Platform_MMU)">MMIO Isolation (Platform MMU)</span></h4> +<p>The platform's CPU communicates with the GPU by reading/writing to and from pinned MMIO pages in <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Random-access_memory">Random Access Memory (RAM)</a>. MMIO pages within the RAM are subject to IO Virtual Address (IOVA) translations by the platform's discrete MMU controller which is programmed by the CPU. These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the platform. +</p> +<h4><span id="VRAM_Isolation_.28GPU_GMMU.29"></span><span class="mw-headline" id="VRAM_Isolation_(GPU_GMMU)">VRAM Isolation (GPU GMMU)</span></h4> +<p>The GPU core performs virtualized operations by reading/writing to and from shadow page tables in onboard <a href="https://en.wikipedia.org/wiki/Video_random_access_memory" class="extiw" title="wikipedia:Video random access memory">Video Random Access Memory (VRAM)</a>. Shadow pages within the VRAM are subject to IO Virtual Address (IOVA) translations by the GPU's discrete GPU MMU controller (GMMU) which is programmed by the Embedded CPU (GPU co-processor). These IOVA translations serve as a mechanism to enforce HPA to GPA isolation in the context of the virtual GPUs and multi-process isolation in single user environments. +</p> +<h4><span id="Platform_MMIO_.3C-.3E_GPU_Shadow_Pages"></span><span class="mw-headline" id="Platform_MMIO_<->_GPU_Shadow_Pages">Platform MMIO <-> GPU Shadow Pages</span></h4> +<p>In the context of VFIO pinned MMIO pages in RAM act as an interface to communicate with VRAM shadow pages allowing GPU drivers on the platform to send instructions to the GPU. When the GPU or Platform alters memory contained in a shadow page or pinned MMIO page the change is mirrored in the corresponding IO Virtual Address (IOVA). For example if shadow page 0 is changed by the GPU this change is mirrored in MMIO page 0 on the platform (the reverse example also applies). When communications occur between the platform and GPU the information first moves through the MMU/GMMU and is then written to RAM/VRAM. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="image"><img alt="Figure 7: A depiction of region overlays within a VFIO file descriptor." src="../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/300px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png" decoding="async" width="300" height="268" class="thumbimage" srcset="../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/450px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 1.5x, ../images/thumb/4/48/Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png/600px-Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_7-_A_depiction_of_region_overlays_within_a_VFIO_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 7:</b> A depiction of region overlays within a VFIO file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span id="VFIO_Quirks_.28region_traps.29"></span><span class="mw-headline" id="VFIO_Quirks_(region_traps)">VFIO Quirks (region traps)</span></h3> +<p><b>Figure 7:</b> Regions of the PCI BAR require emulation (slow path) via emulated traps (known as quirks). These regions are primarily in PCI configuration space. QEMU may overlap a region overlay which when read/written to/from triggers a VM-exit to trap and emulate the region in order that appropriate translations may occur (such as those concerned with IO Virtual Address - IOVA). +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="image"><img alt="Peer-to-Peer DMA Isolation under IOMMU" src="../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/300px-Screen_Shot_2022-05-06_at_10.46.59_AM.png" decoding="async" width="300" height="224" class="thumbimage" srcset="../images/thumb/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png/450px-Screen_Shot_2022-05-06_at_10.46.59_AM.png 1.5x, ../images/1/13/Screen_Shot_2022-05-06_at_10.46.59_AM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Screen_Shot_2022-05-06_at_10.46.59_AM.png.html" class="internal" title="Enlarge"></a></div><b>Figure 8:</b> Peer-to-Peer DMA Isolation under IOMMU. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[2]</a></div></div></div> +<h3><span class="mw-headline" id="Known_IOMMU_Issues">Known IOMMU Issues</span></h3> +<p><b>DMA Aliasing</b> +</p> +<ul><li>Not all devices generate unique IDs.</li> +<li>Not all devices generate IDs they should.<br /></li></ul> +<p><b>DMA Isolation</b> +</p> +<ul><li><b>Figure 8:</b> Peer-to-Peer DMA Isolation. In many circumstances IO Virtual Address (IOVA) translations do not occur properly in the context of DMA peering. Transactions that occur through the IOMMU are unaffected.</li></ul> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="image"><img alt="Figure 0: Approches to GPU Virtualization." src="../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/300px-Figure_0-_Approches_to_GPU_Virtualization..png" decoding="async" width="300" height="153" class="thumbimage" srcset="../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/450px-Figure_0-_Approches_to_GPU_Virtualization..png 1.5x, ../images/thumb/6/6a/Figure_0-_Approches_to_GPU_Virtualization..png/600px-Figure_0-_Approches_to_GPU_Virtualization..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_0-_Approches_to_GPU_Virtualization..png.html" class="internal" title="Enlarge"></a></div><b>Figure 0:</b> Approaches to GPU Virtualization. See slides from: <a rel="nofollow" class="external text" href="Virtual_I/O_Internals.html#References_(Talks_&_Reading_Material)">[61]</a></div></div></div> +<h2><span class="mw-headline" id="Mdev_Mode">Mdev Mode</span></h2> +<p><b>Mdev Mode (VFIO Mediated Device)</b> is a method of virtualizing I/O devices enabling full API capabilities without the requirement for hardware assistance. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_2">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Neo Jia, Kirti Wankhede, Kevin Tian, Yiying Zhang, David Cowperthwaite, Kun Tian, Yaozu Dong, Tina Zhang, Gerd Hoffmann, & Zhi Wang. +</p><p>See references 1, 7, 8, 17, 18, 19, 70 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Mediated_Core">Mediated Core</span></h3> +<p>The mediated device framework made 3 major changes to the VFIO driver. +</p> +<ul><li><b>1: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_core.c">Mediated core module (new)</a></b> <br /> -Mediated bus driver, create mediated device. <br /> -Physical device interface for vendor callbacks. <br /> -Generic Mediated device management user interface (sysfs).</li> +<li><b>2: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/mdev/mdev_driver.c">Mediated device module (new)</a></b> <br /> -Manage created mediated device, fully compatible with VFIO user API (UAPI).</li> +<li><b>3: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/vfio/vfio_iommu_type1.c">VFIO IOMMU driver (enhancement)</a></b> <br /> -VFIO IOMMU API Type1 compatible, easy to extend to non-Type1.</li></ul> +<p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lists.gnu.org/archive/html/qemu-devel/2016-10/msg03922.html"><b>lists.gnu.org Qemu-devel</b> mailing list archive</a>. +</p> +<h3><span class="mw-headline" id="Device_Initialization">Device Initialization</span></h3> +<p>This section will deal with how an Mdev driver is initialized. +</p><p><b>Sample mdev code</b> for device initialization can be found <b><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L229">here</a></b>. +</p> +<h4><span class="mw-headline" id="Registering_VFIO_MDEV_as_a_driver">Registering VFIO MDEV as a driver</span></h4> +<p>VFIO Mdev must be registered as a driver. This register event occurs between the Mdev Driver Register Interface and the VFIO MDEV interface. +</p> +<h4><span class="mw-headline" id="Registering_PCIE_Device_with_the_Mediated_Core">Registering PCIE Device with the Mediated Core</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Mdev-gpu.png.html" class="image"><img alt="Registering the mediated device." src="../images/thumb/7/75/Mdev-gpu.png/300px-Mdev-gpu.png" decoding="async" width="300" height="208" class="thumbimage" srcset="../images/thumb/7/75/Mdev-gpu.png/450px-Mdev-gpu.png 1.5x, ../images/thumb/7/75/Mdev-gpu.png/600px-Mdev-gpu.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Mdev-gpu.png.html" class="internal" title="Enlarge"></a></div><b>Figure 9:</b> Registering the mediated device. This step may be accomplished via the vendor driver or via <a rel="nofollow" class="external text" href="">GVM/Mdev-GPU</a> for drivers which do not include support for Mdev functionality and/or do not support arbitrary Mdev types.</div></div></div> +<p><b>Figure 9:</b> The vendor driver must register with the Mediated Core's Device Register Interface. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span id="Registering_Mediated_Callbacks_.28CBs.29"></span><span class="mw-headline" id="Registering_Mediated_Callbacks_(CBs)">Registering Mediated Callbacks (CBs)</span></h4> +<p><b>Figure 9:</b> The vendor driver must now register Mediated Callbacks which it expects to receive from Mdev devices. The example shown uses the <a rel="nofollow" class="external text" href="">GVM Project</a>'s <a rel="nofollow" class="external text" href="">Mdev-GPU</a> component to accomplish this step on behalf of the vendor driver. +</p> +<h4><span class="mw-headline" id="Creating_a_Mediated_Device_via_mdev-sysfsdev_API">Creating a Mediated Device via mdev-sysfsdev API</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="image"><img alt="" src="../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/300px-Echoing_a_UUID_into_the_sysfsdev_API.png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/450px-Echoing_a_UUID_into_the_sysfsdev_API.png 1.5x, ../images/thumb/e/ef/Echoing_a_UUID_into_the_sysfsdev_API.png/600px-Echoing_a_UUID_into_the_sysfsdev_API.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Echoing_a_UUID_into_the_sysfsdev_API.png.html" class="internal" title="Enlarge"></a></div><b>Figure 10:</b> Echoing a UUID into the mdev-sysfsdev API. This functionality is included in <a rel="nofollow" class="external text" href="https://github.com/mdevctl/mdevctl">mdevctl</a> and in <a rel="nofollow" class="external text" href=""></a>. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 10:</b> The user of an mdev capable device driver may echo values such as a UUID into the mdev-sysfsdev interface to create a unique mediated device. UUIDs must be unique per mdev device within a host. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="image"><img alt="Figure 10: QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor." src="../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/300px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png" decoding="async" width="300" height="231" class="thumbimage" srcset="../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/450px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 1.5x, ../images/thumb/6/63/QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png/600px-QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_creates_VFIO-mdev_IOMMU_binding_and_acquires_mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 11:</b> QEMU creates VFIO-mdev IOMMU binding and acquires mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<h4><span class="mw-headline" id="QEMU_adds_VFIO_device_to_IOMMU_container-group">QEMU adds VFIO device to IOMMU container-group</span></h4> +<p><b>Figure 11:</b> When starting a QEMU process with a VFIO-mdev attached QEMU calls the VFIO API to add the VFIO device to an IOMMU container/group. QEMU then runs the IOCTL to obtain a file descriptor for the device. +</p> +<h4><span class="mw-headline" id="QEMU_passes_mdev_device_file_descriptor_to_VM">QEMU passes mdev device file descriptor to VM</span></h4> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="image"><img alt="Figure 11: QEMU presenting the VFIO file descriptor into the virtual machine." src="../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/300px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png" decoding="async" width="300" height="234" class="thumbimage" srcset="../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/450px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 1.5x, ../images/thumb/7/7c/QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png/600px-QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_presenting_the_VFIO_file_descriptor_into_the_virtual_machine..png.html" class="internal" title="Enlarge"></a></div><b>Figure 12:</b> QEMU presenting the VFIO file descriptor into the virtual machine. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 12:</b> Once QEMU has obtained the VFIO file descriptor for the Mdev device via IOCTL it is then QEMU's job to present the file descriptor into the virtual machine so that the mdev may be used by the guest. +</p> +<h3><span class="mw-headline" id="Instruction_Execution">Instruction Execution</span></h3> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Ioeventfd-and-irqfd.png.html" class="image"><img alt="" src="../images/thumb/a/aa/Ioeventfd-and-irqfd.png/300px-Ioeventfd-and-irqfd.png" decoding="async" width="300" height="215" class="thumbimage" srcset="../images/thumb/a/aa/Ioeventfd-and-irqfd.png/450px-Ioeventfd-and-irqfd.png 1.5x, ../images/thumb/a/aa/Ioeventfd-and-irqfd.png/600px-Ioeventfd-and-irqfd.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Ioeventfd-and-irqfd.png.html" class="internal" title="Enlarge"></a></div><b>Figure 13:</b> A simple diagram of signalling from host to guest (via irqfd) & guest to host (via ioeventfd) From <a rel="nofollow" class="external text" href="http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">blog.allenx</a></div></div></div> +<p><b>Figure 13:</b> Mdev Mode moves instruction information across a virtual function (VF) device using <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Remote_procedure_call">Remote Procedure Calls</a> generally by way of <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Interrupt">software interrupt</a> (<a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a>). Signals to and from the guest and the host GPU driver may be passed over file descriptors such as the <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">Interrupt Request File Descriptor (irqfd)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">IO Event File Descriptor (ioeventfd)</a>. +The irqfd may be used to signal from the host into the guest whereas the ioeventfd may be used to signal from the guest into the host. Guest GPU instructions which would normally serialize as pRPCs (physical Remote Procedure Calls) are instead serialized from the guest as vRPCs (virtual Remote Procedure Calls) which are executed by the host mediated driver. +</p> +<h4><span class="mw-headline" id="IRQ_remapping">IRQ remapping</span></h4> +<p>Interrupt Requests (IRQs) must be remapped (trapped for virtualized execution) to protect the host from sensitive instructions which may affect global memory state. +</p> +<h4><span class="mw-headline" id="Interrupt_Injection">Interrupt Injection</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p> +<h3><span class="mw-headline" id="Memory_Management">Memory Management</span></h3> +<p>Mdev memory management is handled by vendor driver software. +</p> +<h4><span class="mw-headline" id="Region_Passthrough">Region Passthrough</span></h4> +<p>Guests may be presented with emulated memory regions or via passthrough regions or a mixture of the two such as in the case of passthrough regions with BAR 0 configuration space emulation while other regions are passthrough'd. +</p> +<h5><span class="mw-headline" id="Emulated_Regions">Emulated Regions</span></h5> +<p>Emulated memory regions use indirect emulated communication requiring a VM-exit (slow). These regions are often used for virtual PCI config space such as <a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/c0adb9957c0b22bfdbc18395e81dd2b476addac5/mdpy.c#L112">in this sample code</a>. +</p> +<h5><span class="mw-headline" id="Passthrough_Regions">Passthrough Regions</span></h5> +<p>Passthrough memory regions use direct communication requiring no VM-exit (fast). +</p> +<h5><span class="mw-headline" id="Region_Access">Region Access</span></h5> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="image"><img alt="Figure 13: QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs" src="../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/300px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png" decoding="async" width="300" height="236" class="thumbimage" srcset="../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/450px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 1.5x, ../images/thumb/f/fa/QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png/600px-QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_gets_region_info_via_VFIO_UAPI_from_vendor_driver_through_vfio-mdev_and_Mediated_CBs.png.html" class="internal" title="Enlarge"></a></div><b>Figure 14:</b> QEMU gets region info via VFIO UAPI from vendor driver through vfio-mdev and Mediated CBs. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 14:</b> QEMU gets region information via VFIO User API (UAPI) from the vendor driver through VFIO-mdev and Mediated Callbacks. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><div class="MediaTransformError" style="width: 300px; height: 238px; display:inline-block;">Error creating thumbnail: File missing</div> <div class="thumbcaption"><div class="magnify"><a href="./File:Guest_driver_accessing_Mdev_MMIO_space_backed_by_mdev_file_descriptor_triggers_EPT_violation..png.html" class="internal" title="Enlarge"></a></div><b>Figure 15:</b> Guest driver accessing Mdev MMIO space backed by mdev file descriptor triggers EPT violation. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 15:</b> The guest's vendor driver accesses the Mdev MMIO trapped region backed by a mdev file descriptor (fd) which triggers an Extended Page Table (EPT) violation. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="image"><img alt="Figure 15: KVM services EPT violation and forwards to QEMU VFIO PCI driver." src="../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/300px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/450px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 1.5x, ../images/thumb/4/43/KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png/600px-KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:KVM_services_EPT_violation_and_forwards_to_QEMU_VFIO_PCI_driver..png.html" class="internal" title="Enlarge"></a></div><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 16:</b> KVM services EPT violation and forwards to QEMU VFIO PCI driver. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="image"><img alt="Figure 16: QEMU convert request from KVM to Read/Write acess to Mdev file descriptor." src="../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/300px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png" decoding="async" width="300" height="235" class="thumbimage" srcset="../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/450px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 1.5x, ../images/thumb/2/27/QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png/600px-QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_convert_request_from_KVM_to_Read-Write_acess_to_Mdev_file_descriptor..png.html" class="internal" title="Enlarge"></a></div><b>Figure 17:</b> QEMU convert request from KVM to Read/Write acess to Mdev file descriptor. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 17:</b> QEMU convert request from KVM to R/W access to Mdev file descriptor. +</p> +<h4><span class="mw-headline" id="EPT_Page_Violations">EPT Page Violations</span></h4> +<p>Guest <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Memory-mapped_I/O">Memory Mapped IO (MMIO)</a> trips Extended Page Table (EPT) violations which are trapped by the host MMU. KVM services EPT violations and forwards to QEMU VFIO PCI driver. QEMU then converts the request from KVM to R/W access to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/File_descriptor">Mdev File Descriptor (FD)</a>. Reads and writes are then handled by the host GPU device driver via mediated <a rel="nofollow" class="external text" href="https://infogalactic.com/info/Callback_(computer_programming)">callbacks (CBs)</a> and <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO-mdev</a>. +</p> +<h4><span class="mw-headline" id="Mediated_DMA_Translations">Mediated DMA Translations</span></h4> +<p><b>--</b> +</p><p><b>--Researching--</b> +</p><p><b>--</b> +</p><p>Because memory is not statically allocated by the vendor driver under the mediated device framework there is no requirement to make use of traditional VFIO pinned pages (via the vfio-pci module) rather MMIO memory can be mapped at runtime incrementally. As a result non-standard mediated device vfio stub modules may be used. +</p><p><b>Figure 18:</b> Memory regions get added by QEMU. +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Memory_Regions_Added_by_QEMU.png.html" class="image"><img alt="Memory Regions Added by QEMU" src="../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/300px-Memory_Regions_Added_by_QEMU.png" decoding="async" width="300" height="225" class="thumbimage" srcset="../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/450px-Memory_Regions_Added_by_QEMU.png 1.5x, ../images/thumb/5/58/Memory_Regions_Added_by_QEMU.png/600px-Memory_Regions_Added_by_QEMU.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Memory_Regions_Added_by_QEMU.png.html" class="internal" title="Enlarge"></a></div><b>Figure 18:</b> Memory Regions Added by QEMU. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 19:</b> QEMU calls VFIO_DMA_MAP via Memory listener. (not just guest physical memory but also device memory will be added through this memory listener) +</p> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="image"><img alt="QEMU calls VFIO DMA MAP via Memory listener" src="../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/300px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/450px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 1.5x, ../images/thumb/2/21/QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png/600px-QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:QEMU_calls_VFIO_DMA_MAP_via_Memory_listener.png.html" class="internal" title="Enlarge"></a></div><b>Figure 19:</b> QEMU calls VFIO DMA MAP via Memory listener. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="image"><img alt="Type 1 IOMMU Tracks VA-GFN" src="../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/300px-Type_1_IOMMU_Tracks_VA-GFN.png" decoding="async" width="300" height="237" class="thumbimage" srcset="../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/450px-Type_1_IOMMU_Tracks_VA-GFN.png 1.5x, ../images/thumb/1/1d/Type_1_IOMMU_Tracks_VA-GFN.png/600px-Type_1_IOMMU_Tracks_VA-GFN.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Type_1_IOMMU_Tracks_VA-GFN.png.html" class="internal" title="Enlarge"></a></div><b>Figure 20:</b> Type 1 IOMMU Tracks <VA, GFN>. See slides from: <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#References_(Talks_&_Reading_Material)">[1]</a></div></div></div> +<p><b>Figure 20:</b> Type 1 IOMMU tracks <VA, GFN (Guest Frame Number)>. We build a table to list the QEMU VAs and track the their mapping relation to Guest Frame Numbers (GFNs). +</p> +<h3><span class="mw-headline" id="Scheduling">Scheduling</span></h3> +<p>Scheduling is handled by the host mdev driver. +</p> +<h3><span class="mw-headline" id="Kernel_API">Kernel API</span></h3> +<p>Kernel documentation used for implementing a VFIO Mediated Device may be found at <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/driver-api/vfio-mediated-device.html">kernel.org</a>. +</p> +<h3><span class="mw-headline" id="Sample_Code">Sample Code</span></h3> +<p>Sample code for various mdev implementations may be found below: +</p><p><b>Mediated Virtual PCI Display Host Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy.c">mdpy.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mdpy-fb.c">mdpy-fb.c</a></li> +<li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mbochs.c">mbochs.c</a>.</li></ol> +<p><b>Serial PCI Port-based Mediated Device:</b> +</p> +<ol><li><a rel="nofollow" class="external text" href="https://github.com/Open-IOV/VFIO-Mdev_Samples/blob/master/mtty.c">mtty.c</a>.</li></ol> +<h6><span class="mw-headline" id="Compilation">Compilation</span></h6> +<p>To compile the kernel modules linked above you should have your distro's equivalent of the build-essential package installed. The included Makefile should provide all that is necessary to successfully compile the kernel modules. You can type the following command to compile the modules from within the directory: +</p><p><code>make</code> +</p><p>When the make operation has been completed successfully the directory will now contain .ko files. These files are the binary kernel modules. +</p> +<h6><span class="mw-headline" id="Loading_Kernel_Modules">Loading Kernel Modules</span></h6> +<p>Now that you have compiled the kernel modules you may load them via the insmod command. +</p><p>For example to load the <b>mtty.ko</b> module run the following command from within the directory where you built the modules: +</p><p><code>insmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Unloading_Kernel_Modules">Unloading Kernel Modules</span></h6> +<p>To unload any of the kernel modules you may make use of the rmmod command. +</p><p>For example to unload the <b>mtty.ko</b> module run the following command: +</p><p><code>rmmod mtty.ko</code> +</p> +<h6><span class="mw-headline" id="Additional_Documentation">Additional Documentation</span></h6> +<p>An additional guide explaining how to make use of the mtty.c sample code may be found at <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294#n308">line 308</a> of the kernel.org VFIO Mediated Device documentation. +</p> +<h3><span class="mw-headline" id="Mdev_Mode_Requirements">Mdev Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Software HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SR-IOV_Mode">SR-IOV Mode</span></h2> +<p><b>SR-IOV Mode (Single Root I/O Virtualization)</b> involves hardware assisted virtualization on I/O peripherals. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_3">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Zheng Xiao, Jerry Jiang, & Ken Xue. +</p><p>See reference 6 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Instruction_Execution_2">Instruction Execution</span></h3> +<p>SR-IOV communicates instructions from a virtual function (VF) directly to the <a rel="nofollow" class="external text" href="https://infogalactic.com/info/PCI_configuration_space">PCI BAR</a>. +</p> +<h3><span class="mw-headline" id="Memory_Management_2">Memory Management</span></h3> +<p>Guests are presenting with passthrough memory regions by the device firmware. +</p> +<h3><span class="mw-headline" id="Scheduling_2">Scheduling</span></h3> +<p>Scheduling may be handled by the host mdev driver and/or the device firmware. +</p> +<h3><span class="mw-headline" id="SR-IOV_Mode_Requirements">SR-IOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SR-IOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span class="mw-headline" id="SIOV_Mode">SIOV Mode</span></h2> +<p><b>SIOV (Scalable I/O Virtualization)</b> involves the combination of concepts form both <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#SR-IOV_Mode">SR-IOV Mode</a> and <a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Mdev_Mode">Mdev Mode</a> as well as novel concepts like shared IOMMU aware buffers and offloading of PCI config space VM-exits (slow path) to a discrete controller. +</p><p><b>Revision 1.0 of the SIOV specification</b> can be read on the <a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Open Compute Project website</a>. +</p> +<h3><span class="mw-headline" id="Knowledge_Resources_Used_4">Knowledge Resources Used</span></h3> +<p>This section is supported by significant contributions in open source by Kevin Tian, Tina Zhang, Xin Zeng, Yi Liu. +</p><p>See references 3, 4, 5, 16, 17, 18, 19, 20, 21 in the <a rel="nofollow" class="external text" href="Virtual_IO_Internals.html#References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</a> section. +</p> +<h3><span class="mw-headline" id="Memory_Management_3">Memory Management</span></h3> +<p>Enhancements to <a rel="nofollow" class="external text" href="https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/002/intel-virtualization-technology-for-directed-i-o/">Intel VT-d</a> introduce new 'Scalable Mode' to allow the platform to assign more granular IOMMU allocations to mediated devices (<a rel="nofollow" class="external text" href="Mediated_Device_Internals.html#Memory_Management">mdev memory management</a>). This change is referred to as an IOMMU Aware Mediated Device. +</p> +<h4><span class="mw-headline" id="IOMMU_Aware_Mediated_Device">IOMMU Aware Mediated Device</span></h4> +<p>SIOV made several changes to the VFIO driver, Intel IOMMU, and Mediated Device Framework. +</p><p>The full list of these changes can be seen in the <a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">mailing list archive on <b>lwn.net</b> under <b>(vfio/mdev: IOMMU aware mediated device)</b></a>. +</p> +<h4><span class="mw-headline" id="Shared_Hardware_Workqueues">Shared Hardware Workqueues</span></h4> +<p>SIOV makes use of Shared Hardware Workqueues which may be accessed by processes or Virtual Machines. +</p><p><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">According to <b>kernel.org</b></a>: <i>"In order to allow the hardware to distinguish the context for which work is being executed in the hardware by SWQ interface, SIOV uses Process Address Space ID (PASID), which is a 20-bit number defined by the PCIe SIG. PASID value is encoded in all transactions from the device. This allows the IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe Resource Identifier (RID) which is the Bus/Device/Function."</i> +</p> +<h3><span class="mw-headline" id="SIOV_Mode_Requirements">SIOV Mode Requirements</span></h3> +<p>Driver Support. +</p><p>Device SIOV support. +</p><p>Firmware HPA<->GPA Boundary Enforcement. +</p> +<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&_Reading_Material)">References (Talks & Reading Material)</span></h2> +<ol><li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=Xs0TJU_sIPc">[2016] vGPU on KVM - A VFIO Based Framework by Neo Jia & Kirti Wankhede</a> - <a rel="nofollow" class="external text" href="https://www.linux-kvm.org/images/5/59/02x03-Neo_Jia_and_Kirti_Wankhede-vGPU_on_KVM-A_VFIO_based_Framework.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=WFkdTFTOTpA">[2016] An Introduction to PCI Device Assignment with VFIO by Alex Williamson</a> - <a rel="nofollow" class="external text" href="http://events17.linuxfoundation.org/sites/events/files/slides/An%20Introduction%20to%20PCI%20Device%20Assignment%20with%20VFIO%20-%20Williamson%20-%202016-08-30_0.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://events19.linuxfoundation.cn/wp-content/uploads/2017/11/Intel%C2%AE-Scalable-I_O-Virtualization_Kevin-Tian.pdf">[2017] Scalable I/O Virtualization by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=G6D-jaCs6sc">[2019] Bring a Scalable IOV Capable Device into Linux World by Xin Zeng & Yi Liu</a> - <a rel="nofollow" class="external text" href="https://static.sched.com/hosted_files/kvmforum2019/5e/Bring%20a%20scalable%20IOV%20capable%20device%20into%20Linux%20-%20KVM%202019.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.opencompute.org/documents/ocp-scalable-io-virtualization-technical-specification-revision-1-v1-2-pdf">Scalable I/O Virtualization Revision 1.0</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=_tB3EbFDcRQ">[2018] Live Migration Support for GPU with SRIOV by Zheng Xiao, Jerry Jiang & Ken Xue</a> - <a rel="nofollow" class="external text" href="https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Live-Migration-Support-for-GPU-with-SRIOV-Challenges-and-Solution-Zheng-Xiao-Alibaba-Cloud-Jerry-Jiang-Ken-Xue-AMD.pdf">slides</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=UODxW1opfn0">[2017] Intel GVT-g: From Production to Upstream - Zhi Wang, Intel</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=DKYvQ3FdFeo">[2016] Qemu Graphics Update 2016 by Gerd Hoffmann</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/ioctl.rst">IOCTL</a></li> +<li><a rel="nofollow" class="external text" href="https://man7.org/linux/man-pages/man2/eventfd.2.html">eventfd</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/eventfd.c">root/virt/kvm/eventfd.c</a></li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=721eecbf4fe995ca94a9edec0c9843b1cc0eaaf3">KVM: irqfd</a>)</li> +<li>(kernel diff:: <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d34e6b175e61821026893ec5298cc8e7558df43a">KVM: add ioeventfd support</a>)</li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220120223711/http://blog.allenx.org/2015/07/05/kvm-irqfd-and-ioeventfd">KVM irqfd & ioeventfd</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio.rst">VFIO - Virtual Function I/O</a> - <a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/virt/kvm/vfio.c">root/virt/kvm/vfio.c</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/vfio-mediated-device.rst">VFIO Mediated Devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/ml/linux-kernel/20190222021927.13132-1-baolu.lu@linux.intel.com/">IOMMU Aware Mediated Device</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=95KSKrZM8oQ">Hardware-Assisted Mediated Pass-Through with VFIO by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=cHMLBcHplhk">[2017] Generic Buffer Sharing Mechanism for Mediated Devices by Tina Zhang</a></li> +<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=KWRKx_uxUDI">[2019] Toward a Virtualization World Built on Mediated Pass-Through - Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git/tree/Documentation/driver-api/auxiliary_bus.rst?h=driver-core-next&id=7de3697e9cbd4bd3d62bafa249d57990e1b8f294">Auxiliary Bus</a></li> +<li><a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/sva.html">Shared Virtual Addressing</a></li> +<li><a rel="nofollow" class="external text" href="https://vfio.blogspot.com/">vfio.blogspot.com</a></li> +<li><a rel="nofollow" class="external text" href="https://01.org/sites/default/files/xengt.pdf">XenGT by Kevin Tian</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130721094438/http://labs.vmware.com/academic/publications/gpu-virtualization">VMWare Academic Publications: GPU Virtualization by Micah Dowty & Jeremy Sugerman</a></li> +<li><a rel="nofollow" class="external text" href="https://pcisig.com/specifications/iov">PCI SIG I/O Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120108034526/http://sysweb.cs.toronto.edu/vmgl">VMGL by the University of Toronto Computer Science Department</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120518125815/http://www.nvidia.com/object/vgx-hypervisor.html">Kepler VGX Hypervisor</a></li> +<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090218010221/http://software.intel.com/en-us/articles/intel-virtualization-technology-for-directed-io-vt-d-enhancing-intel-platforms-for-efficient-virtualization-of-io-devices">Intel Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices</a></li> +<li><a rel="nofollow" class="external text" href="https://lwn.net/2001/0712/a/dma-interface.php3">DMA-Mapping.txt (Dynamic DMA Mapping)</a></li> +<li><a rel="nofollow" class="external text" href="https://events.static.linuxfound.org/slides/2011/linuxcon-japan/lcj2011_guangrong.pdf">KVM MMU Virtualization by Xiao Guangrong</a></li> +<li><a rel="nofollow" class="external text" href="https://wiki.osdev.org/PCI">OSDEV: PCI</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1">Down to the TLP: How PCI express devices talk (Part I)</a></li> +<li><a rel="nofollow" class="external text" href="http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2">Down to the TLP: How PCI express devices talk (Part II)</a></li> +<li><a rel="nofollow" class="external text" href="https://projectacrn.github.io/latest/tutorials/sriov_virtualization.html">Intel ACRN: Enabling SR-IOV Virtualization</a></li> +<li><a rel="nofollow" class="external text" href="https://docs.kernel.org/admin-guide/abi-testing.html#abi-file-testing-sysfs-bus-pci">Kernel.org sysfs-bus-pci</a></li> +<li><a rel="nofollow" class="external text" href="https://linux-kernel-labs.github.io/refs/heads/master/labs/memory_mapping.html">Linux Kernel Labs: Memory Mapping</a></li> +<li><a rel="nofollow" class="external text" href="https://rayanfam.com/topics/inside-windows-page-frame-number-part1/">Inside Windows Page Frame Number (PFN) - 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+</head> +<body class="mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject page-Virtualization_Fundamentals rootpage-Virtualization_Fundamentals skin-vector action-view skin-vector-legacy"><div id="mw-page-base" class="noprint"></div> +<div id="mw-head-base" class="noprint"></div> +<div id="content" class="mw-body" role="main"> + <a id="top"></a> + <div id="siteNotice"></div> + <div class="mw-indicators"> + </div> + <h1 id="firstHeading" class="firstHeading" >Virtualization Fundamentals</h1> + <div id="bodyContent" class="vector-body"> + <div id="siteSub" class="noprint">From Open-IOV</div> + <div id="contentSub"></div> + <div id="contentSub2"></div> + + <div id="jump-to-nav"></div> + <a class="mw-jump-link" href="Virtualization_Fundamentals.html#mw-head">Jump to navigation</a> + <a class="mw-jump-link" href="Virtualization_Fundamentals.html#searchInput">Jump to search</a> + <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>This following page is intended to index and summarize information related to the fundamentals of virtualization of computer systems.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization. +</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation. +</p><p> +Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote> +<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div> +<ul> +<li class="toclevel-1 tocsection-1"><a href="Virtualization_Fundamentals.html#Popek_and_Goldberg_Virtualization_Requirements"><span class="tocnumber">1</span> <span class="toctext">Popek and Goldberg Virtualization Requirements</span></a></li> +<li class="toclevel-1 tocsection-2"><a href="Virtualization_Fundamentals.html#Goldberg_Survey_of_Virtual_Machine_Research"><span class="tocnumber">2</span> <span class="toctext">Goldberg Survey of Virtual Machine Research</span></a></li> +<li class="toclevel-1 tocsection-3"><a href="Virtualization_Fundamentals.html#Microkernels_Meet_Recursive_Virtual_Machines"><span class="tocnumber">3</span> <span class="toctext">Microkernels Meet Recursive Virtual Machines</span></a></li> +<li class="toclevel-1 tocsection-4"><a href="Virtualization_Fundamentals.html#A_Comparison_of_Software_and_Hardware_Techniques_for_x86_Virtualization"><span class="tocnumber">4</span> <span class="toctext">A Comparison of Software and Hardware Techniques for x86 Virtualization</span></a></li> +<li class="toclevel-1 tocsection-5"><a href="Virtualization_Fundamentals.html#Virtualizing_I/O_Devices_on_VMware_Workstation’s_Hosted_Virtual_Machine_Monitor"><span class="tocnumber">5</span> <span class="toctext">Virtualizing I/O Devices on VMware Workstation’s Hosted Virtual Machine Monitor</span></a></li> +<li class="toclevel-1 tocsection-6"><a href="Virtualization_Fundamentals.html#Dynamic_binary_translation_and_optimization"><span class="tocnumber">6</span> <span class="toctext">Dynamic binary translation and optimization</span></a></li> +<li class="toclevel-1 tocsection-7"><a href="Virtualization_Fundamentals.html#Xen_and_the_Art_of_Virtualization"><span class="tocnumber">7</span> <span class="toctext">Xen and the Art of Virtualization</span></a></li> +</ul> +</div> + +<h2><span class="mw-headline" id="Popek_and_Goldberg_Virtualization_Requirements"><a rel="nofollow" class="external text" href="https://en.m.wikipedia.org/wiki/Popek_and_Goldberg_virtualization_requirements">Popek and Goldberg Virtualization Requirements</a></span></h2> +<p>The <b>Popek and Goldberg virtualization requirements</b> are a set of conditions sufficient for a computer architecture to support system virtualization efficiently. They were introduced by Gerald J. Popek and Robert P. Goldberg in their 1974 article "Formal Requirements for Virtualizable Third Generation Architectures". Even though the requirements are derived under simplifying assumptions, they still represent a convenient way of determining whether a computer architecture supports efficient virtualization and provide guidelines for the design of virtualized computer architectures. +</p> +<h2><span class="mw-headline" id="Goldberg_Survey_of_Virtual_Machine_Research"><a rel="nofollow" class="external text" href="https://inst.eecs.berkeley.edu//~cs252/sp17/papers/goldberg-vm-survey.pdf">Goldberg Survey of Virtual Machine Research</a></span></h2> +<p>The complete instruction-by-instruction simulation of one computer system on a different system is a well-known computing technique. It is often used for software development when a hardware base is being altered. For example, if a programmer is developing software for some new special purpose (e.g., aerospace) computer X which is under construction and as yet unavailable, he will likely begin by writing a simulator for that computer on some available general-purpose machine G. The simulator will provide a detailed simulation of the special-purpose environment X, including its processor, memory, and I/O devices. Except for possible timing dependencies, programs which run on the “simulated machine X” can later run on the “real machine X” (when it is finally built and checked out) with identical effect. The programs running on X can be arbitrary — including code to exercise simulated I/O devices, move data and instructions anywhere in simulated memory, or execute any instruction of the simulated machine. The simulator provides a layer of software filtering which protects the resources of the machine G from being misused by programs on X. +</p> +<h2><span class="mw-headline" id="Microkernels_Meet_Recursive_Virtual_Machines"><a rel="nofollow" class="external text" href="https://www.flux.utah.edu/download?uid=106">Microkernels Meet Recursive Virtual Machines</a></span></h2> +<p>This paper describes a novel approach to providing mod- ular and extensible operating system functionality and en- capsulated environments based on a synthesis of micro- kernel and virtual machine concepts. We have developed a software-based virtualizable architecture called Fluke that allows recursive virtual machines (virtual machines running on other virtual machines) to be implemented ef- ficiently by a microkernel running on generic hardware. A complete virtual machine interface is provided at each level; efficiency derives from needing to implement only new functionality at each level. This infrastructure allows common OS functionality, such as process management, demand paging, fault tolerance, and debugging support, to be provided by cleanly modularized, independent, stack- able virtual machine monitors, implemented as user pro- cesses. It can also provide uncommon or unique OS fea- tures, including the above features specialized for particu- lar applications’ needs, virtual machines transparently dis- tributed cross-node, or security monitors that allow arbi- trary untrusted binaries to be executed safely. Our proto- type implementation of this model indicates that it is prac- tical to modularize operating systems this way. Some types of virtual machine layers impose almost no overhead at all, while others impose some overhead (typically 0–35%), but only on certain classes of applications. +</p> +<h2><span class="mw-headline" id="A_Comparison_of_Software_and_Hardware_Techniques_for_x86_Virtualization"><a rel="nofollow" class="external text" href="https://www.vmware.com/pdf/asplos235_adams.pdf">A Comparison of Software and Hardware Techniques for x86 Virtualization</a></span></h2> +<p>Until recently, the x86 architecture has not permitted classical trap-and-emulate virtualization. Virtual Machine Monitors for x86, such as VMwareR Workstation and Virtual PC, have instead used binary translation of the guest kernel code. However, both Intel and AMD have now introduced architectural extensions to support classical virtualization. We compare an existing software VMM with a new VMM designed for the emerging hardware support. Surprisingly, the hardware VMM often suffers lower performance than the pure software VMM. To determine why, we study architecture-level events such as page table updates, context switches and I/O, and find their costs vastly different among native, software VMM and hardware VMM execution. We find that the hardware support fails to provide an unambiguous performance advantage for two primary reasons: first, it offers no support for MMU virtualization; second, it fails to co-exist with existing software techniques for MMU virtualization. We look ahead to emerging techniques for addressing this MMU virtualization problem in the context of hardware-assisted virtualization. +</p> +<h2><span id="Virtualizing_I.2FO_Devices_on_VMware_Workstation.E2.80.99s_Hosted_Virtual_Machine_Monitor"></span><span class="mw-headline" id="Virtualizing_I/O_Devices_on_VMware_Workstation’s_Hosted_Virtual_Machine_Monitor"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050204163917/http://www.cis.upenn.edu/~cis700-6/04f/papers/sugerman-vmware-devices.pdf">Virtualizing I/O Devices on VMware Workstation’s Hosted Virtual Machine Monitor</a></span></h2> +<p>Virtual machines were developed by IBM in the 1960’s to provide concurrent, interactive access to a mainframe computer. Each virtual machine is a replica of the underlying physical machine and users are given the illusion of running directly on the physical machine. Virtual machines also provide benefits like isolation and resource sharing, and the ability to run multiple flavors and configurations of operating systems. VMware tmWorkstation brings such mainframe-class virtual machine technology to PC-based desktop and workstation computers. This paper focuses on VMware Workstation’s approach to virtualizing I/O devices. PCs have a staggering variety of hardware, and are usually pre-installed with an operating system. Instead of replacing the pre-installed OS, VMware Workstation uses it to host a user-level application (VMApp) component, as well as to schedule a privileged virtual machine monitor (VMM) component. The VMM directly provides high-performance CPU virtualization while the VMApp uses the host OS to virtualize I/O devices and shield the VMM from the variety of devices. A crucial question is whether virtualizing devices via such a hosted architecture can meet the performance required of high throughput, low latency devices. To this end, this paper studies the virtualization and performance of an Ethernet adapter on VMware Workstation. Results indicate that with optimizations, VMware Workstation’s hosted virtualization architecture can match native I/O throughput on standard PCs. Although a straightforward hosted implementation is CPU-limited due to virtualization overhead on a 733 MHz PentiumR III system on a 100 Mb/s Ethernet, a series of optimizations targeted at reducing CPU utilization allows the system to match native network throughput. Further optimizations are discussed both within and outside a hosted architecture. +</p> +<h2><span class="mw-headline" id="Dynamic_binary_translation_and_optimization"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20050204152215/https://www.cis.upenn.edu/~cis700-6/04f/papers/ebcioglu-bin-trans.pdf">Dynamic binary translation and optimization</a></span></h2> +<p>We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach o�ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime pro�le information to optimize translations so as to extract instruction level parallelism. This work reports different design trade-offs in the DAISY system, and their impact on �nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage. Keywords| dynamic compilation, binary translation, dynamic optimization, just-in-time compilation, adaptive code generation, pro�le-directed feedback, instruction-level parallelism, very long instruction word architectures, virtual machines, instruction set architectures, instruction set layering. +</p> +<h2><span class="mw-headline" id="Xen_and_the_Art_of_Virtualization"><a rel="nofollow" class="external text" href="https://www.cl.cam.ac.uk/research/srg/netos/papers/2003-xensosp.pdf">Xen and the Art of Virtualization</a></span></h2> +<p>Numerous systems have been designed which use virtualization to subdivide the ample resources of a modern computer. Some require specialized hardware, or cannot support commodity operating systems. Some target 100% binary compatibility at the expense of performance. Others sacrifice security or functionality for speed. Few offer resource isolation or performance guarantees; most provide only best-effort provisioning, risking denial of service. This paper presents Xen, an x86 virtual machine monitor which allows multiple commodity operating systemsto share conventional hardware in a safe and resource managed fashion, but without sacrificing either performance or functionality. This is achieved by providing an idealized virtual machine abstraction to which operating systems such as Linux, BSD and Windows XP, can be ported with minimal effort. Our design is targeted at hosting up to 100 virtual machine instances simultaneously on a modern server. The virtualization approach taken by Xen is extremely efficient: we allow operating systems such as Linux and Windows XP to be hosted simultaneously for a negligible performance overhead — at most a few percent compared with the unvirtualized case. We considerably outperform competing commercial and freely available solutions in a range of microbenchmarks and system-wide tests. +</p> +<!-- +NewPP limit report +Cached time: 20260911161559 +Cache expiry: 86400 +Reduced expiry: false +Complications: [] +CPU time usage: 0.008 seconds +Real time usage: 0.010 seconds +Preprocessor visited node count: 21/1000000 +Post‐expand include size: 0/2097152 bytes +Template argument size: 0/2097152 bytes +Highest expansion depth: 2/40 +Expensive parser function count: 0/100 +Unstrip recursion depth: 0/20 +Unstrip post‐expand size: 0/5000000 bytes +--> +<!-- +Transclusion expansion time report (%,ms,calls,template) +100.00% 0.000 1 -total +--> + +<!-- Saved in parser cache with key my_wiki:pcache:idhash:39-0!canonical and timestamp 20260911161559 and revision id 23743. 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