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authorOpen-IOV <dev@open-iov.org>2026-09-23 05:44:08 -0400
committerOpen-IOV <dev@open-iov.org>2026-09-23 05:46:43 -0400
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open-iov-2302fc09080bad51c73f293294e19fd4db464eb0.zip
Open-IOV: initial public release
Open-IOV virtualizes NVIDIA GPUs so that unmodified guest drivers run with real GPU functionality - CUDA first, 3D and video to follow - on unmodified hosts, without a proprietary vGPU license and without patching any driver, firmware or hypervisor. Core principle: emulate the interface, pass through the work. kernel/ open-iov-vfio.ko - host VFIO mdev driver: virtual GPU device (PCI config space, BAR shadows, MSI-X), GSP boot emulation, GSP-RM message-queue/RPC emulation, memory model (GPU-VA to guest-PA discovery) and the semaphore-completion service that advances guest UVM progress. userspace/ libiov.so management API and examples. tools/ guest diagnostics, firmware analysis wrappers, RM probes. scripts/ stack manager, VM harness, build/load/test automation. config/ hardware/version profiles (the portability surface). docs/ documentation tree - start at docs/README.md. wiki/ long-form firmware and protocol deep dives. Status: initialization works end to end for a stock 570.144 Linux guest on Turing (TU104): driver probe, nvidia-smi, the full GSP-RM control battery, object creation and the early CUDA/UVM start-up path. GPU work forwarding - the step that makes CUDA kernels execute on real hardware - is the active work item; see docs/04-implementation/01-known-knowns-and-unknowns.md. License: BSD-3-Clause for the project; GPL-2.0 for kernel modules that link GPL-only kernel interfaces. See LICENSE and docs/09-reference/legal-and-licensing.md.
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+ <h1 id="firstHeading" class="firstHeading" >GPU Firmware</h1>
+ <div id="bodyContent" class="vector-body">
+ <div id="siteSub" class="noprint">From Open-IOV</div>
+ <div id="contentSub"></div>
+ <div id="contentSub2"></div>
+
+ <div id="jump-to-nav"></div>
+ <a class="mw-jump-link" href="GPU_Firmware.html#mw-head">Jump to navigation</a>
+ <a class="mw-jump-link" href="GPU_Firmware.html#searchInput">Jump to search</a>
+ <div id="mw-content-text" class="mw-body-content mw-content-ltr" lang="en" dir="ltr"><div class="mw-parser-output"><p>GPUs have become highly complex systems containing a number of different embedded controllers. This page will attempt to document embedded GPU firmware and support for IO virtualization through various firmware functions.</p><blockquote><p>An absence of critical technical documentation has historically slowed growth and adoption of developer ecosystems for GPU virtualization.
+</p><p>This <a rel="nofollow" class="external text" href="https://creativecommons.org/licenses/by/4.0/">CC-BY-4.0</a> licensed content can either be used with attribution, or used as inspiration for new documentation, created by GPU vendors for public commercial distribution as developer documentation.
+</p><p>
+Where possible, this documentation will clearly label dates and versions of observed-but-not-guaranteed behaviour vs. vendor-documented stable interfaces/behaviour with guarantees of forward or backward compatibility.</p></blockquote>
+<div id="toc" class="toc" role="navigation" aria-labelledby="mw-toc-heading"><input type="checkbox" role="button" id="toctogglecheckbox" class="toctogglecheckbox" style="display:none" /><div class="toctitle" lang="en" dir="ltr"><h2 id="mw-toc-heading">Contents</h2><span class="toctogglespan"><label class="toctogglelabel" for="toctogglecheckbox"></label></span></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="GPU_Firmware.html#Intel"><span class="tocnumber">1</span> <span class="toctext">Intel</span></a>
+<ul>
+<li class="toclevel-2 tocsection-2"><a href="GPU_Firmware.html#Firmware_Images"><span class="tocnumber">1.1</span> <span class="toctext">Firmware Images</span></a>
+<ul>
+<li class="toclevel-3 tocsection-3"><a href="GPU_Firmware.html#Intel_Firmware_Support_Package_(FSP)"><span class="tocnumber">1.1.1</span> <span class="toctext">Intel Firmware Support Package (FSP)</span></a>
+<ul>
+<li class="toclevel-4 tocsection-4"><a href="GPU_Firmware.html#FSP_Configuration"><span class="tocnumber">1.1.1.1</span> <span class="toctext">FSP Configuration</span></a>
+<ul>
+<li class="toclevel-5 tocsection-5"><a href="GPU_Firmware.html#Editing_FSP_Configuration"><span class="tocnumber">1.1.1.1.1</span> <span class="toctext">Editing FSP Configuration</span></a></li>
+</ul>
+</li>
+<li class="toclevel-4 tocsection-6"><a href="GPU_Firmware.html#FSP_Binary_Format"><span class="tocnumber">1.1.1.2</span> <span class="toctext">FSP Binary Format</span></a></li>
+</ul>
+</li>
+<li class="toclevel-3 tocsection-7"><a href="GPU_Firmware.html#Known_Firmware_Package_Variations"><span class="tocnumber">1.1.2</span> <span class="toctext">Known Firmware Package Variations</span></a></li>
+</ul>
+</li>
+<li class="toclevel-2 tocsection-8"><a href="GPU_Firmware.html#Embedded_Controllers"><span class="tocnumber">1.2</span> <span class="toctext">Embedded Controllers</span></a>
+<ul>
+<li class="toclevel-3 tocsection-9"><a href="GPU_Firmware.html#GuC"><span class="tocnumber">1.2.1</span> <span class="toctext">GuC</span></a>
+<ul>
+<li class="toclevel-4 tocsection-10"><a href="GPU_Firmware.html#Hardware_Architecture"><span class="tocnumber">1.2.1.1</span> <span class="toctext">Hardware Architecture</span></a></li>
+<li class="toclevel-4 tocsection-11"><a href="GPU_Firmware.html#Software_Architecture"><span class="tocnumber">1.2.1.2</span> <span class="toctext">Software Architecture</span></a>
+<ul>
+<li class="toclevel-5 tocsection-12"><a href="GPU_Firmware.html#GuC_Blob_Checksum_&amp;_Code_Signing"><span class="tocnumber">1.2.1.2.1</span> <span class="toctext">GuC Blob Checksum &amp; Code Signing</span></a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</li>
+<li class="toclevel-1 tocsection-13"><a href="GPU_Firmware.html#Nvidia"><span class="tocnumber">2</span> <span class="toctext">Nvidia</span></a>
+<ul>
+<li class="toclevel-2 tocsection-14"><a href="GPU_Firmware.html#Firmware_Images_2"><span class="tocnumber">2.1</span> <span class="toctext">Firmware Images</span></a></li>
+<li class="toclevel-2 tocsection-15"><a href="GPU_Firmware.html#Embedded_Controllers_2"><span class="tocnumber">2.2</span> <span class="toctext">Embedded Controllers</span></a>
+<ul>
+<li class="toclevel-3 tocsection-16"><a href="GPU_Firmware.html#Falcon_/_NV-RISCV"><span class="tocnumber">2.2.1</span> <span class="toctext">Falcon / NV-RISCV</span></a></li>
+<li class="toclevel-3 tocsection-17"><a href="GPU_Firmware.html#GSP"><span class="tocnumber">2.2.2</span> <span class="toctext">GSP</span></a>
+<ul>
+<li class="toclevel-4 tocsection-18"><a href="GPU_Firmware.html#GSP_Initialization_&amp;_Offload"><span class="tocnumber">2.2.2.1</span> <span class="toctext">GSP Initialization &amp; Offload</span></a></li>
+</ul>
+</li>
+<li class="toclevel-3 tocsection-19"><a href="GPU_Firmware.html#CMU"><span class="tocnumber">2.2.3</span> <span class="toctext">CMU</span></a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li class="toclevel-1 tocsection-20"><a href="GPU_Firmware.html#AMD"><span class="tocnumber">3</span> <span class="toctext">AMD</span></a></li>
+<li class="toclevel-1 tocsection-21"><a href="GPU_Firmware.html#References_(Talks_&amp;_Reading_Material)"><span class="tocnumber">4</span> <span class="toctext">References (Talks &amp; Reading Material)</span></a></li>
+</ul>
+</div>
+
+<h2><span class="mw-headline" id="Intel">Intel</span></h2>
+<h3><span class="mw-headline" id="Firmware_Images">Firmware Images</span></h3><p>
+This section will cover firmware images used in Intel GPUs.</p><div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html" class="image"><img alt="Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification." src="../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/300px-Screen_Shot_2022-11-18_at_4.14.32_PM.png" decoding="async" width="300" height="261" class="thumbimage" srcset="../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/450px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 1.5x, ../images/thumb/0/0e/Screen_Shot_2022-11-18_at_4.14.32_PM.png/600px-Screen_Shot_2022-11-18_at_4.14.32_PM.png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Screen_Shot_2022-11-18_at_4.14.32_PM.png.html" class="internal" title="Enlarge"></a></div>Figure 1: The FSP Binary Layout from Intel® Firmware Support Package External Architecture Specification. <a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/736809">Source</a></div></div></div>
+<h4><span id="Intel_Firmware_Support_Package_.28FSP.29"></span><span class="mw-headline" id="Intel_Firmware_Support_Package_(FSP)">Intel Firmware Support Package (FSP)</span></h4>
+<p>Much like CPUs Intel's GPUs also contain a Firmware Support Package (FSP).
+</p><p>The Coreboot project provides public domain information on the FSP <a rel="nofollow" class="external text" href="https://doc.coreboot.org/soc/intel/fsp/index.html">here</a>.
+</p>
+<h5><span class="mw-headline" id="FSP_Configuration">FSP Configuration</span></h5>
+<p>In the context of GPUs the FSP configures several functions of the device.
+</p><p>Those functions are as follows:
+</p>
+<table class="wikitable">
+<caption>GPU Firmware Support Package
+</caption>
+<tbody><tr>
+<th>FSP Parameter
+</th>
+<th>Possible Values
+</th></tr>
+<tr>
+<td>GFSP Status
+</td>
+<td>0x00
+</td></tr>
+<tr>
+<td>FIVR SSC Value
+</td>
+<td>*.*%
+</td></tr>
+<tr>
+<td>FIVR RFI Value
+</td>
+<td>*.*MHz
+</td></tr>
+<tr>
+<td>GT Subsystem Vendor ID
+</td>
+<td>0x8086
+</td></tr>
+<tr>
+<td>GT Subsystem Device ID
+</td>
+<td>0x**
+</td></tr>
+<tr>
+<td>HDA Subsystem Vendor ID
+</td>
+<td>0x0000
+</td></tr>
+<tr>
+<td>HDA Subsystem Device ID
+</td>
+<td>0x0000
+</td></tr>
+<tr>
+<td>P2SB Enable
+</td>
+<td>Yes/No
+</td></tr>
+<tr>
+<td>LMEBAR
+</td>
+<td>Max
+</td></tr>
+<tr>
+<td>GTMMADDR Prefetch Capability
+</td>
+<td>Prefetch Enabled
+</td></tr>
+<tr>
+<td><a rel="nofollow" class="external text" href="Merged_Drivers.html">Display Present</a>
+</td>
+<td>Enabled/Disabled
+</td></tr>
+<tr>
+<td>I2C For Third Party Devices
+</td>
+<td>Enabled/Disabled
+</td></tr>
+<tr>
+<td>I2C Device Address 1
+</td>
+<td>0x0000
+</td></tr>
+<tr>
+<td>I2C Device Address 2
+</td>
+<td>0x0000
+</td></tr>
+<tr>
+<td>I2C Bus Speed
+</td>
+<td>Standard mode (0 to 100Kbps)
+</td></tr></tbody></table>
+<h6><span class="mw-headline" id="Editing_FSP_Configuration">Editing FSP Configuration</span></h6>
+<p>The FSP configuration editor can be downloaded <a rel="nofollow" class="external text" href="https://github.com/tianocore/edk2/tree/master/IntelFsp2Pkg/Tools/ConfigEditor">here</a> and it's user manual is available <a rel="nofollow" class="external text" href="https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Tools/UserManuals/ConfigEditorUserManual.md">here</a>.
+</p>
+<h5><span class="mw-headline" id="FSP_Binary_Format">FSP Binary Format</span></h5>
+<p>The FSP's binary layout is detailed within the <a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/736809">Intel® FSP External Architecture Specification v2.4</a> on page 14.
+</p>
+<h4><span class="mw-headline" id="Known_Firmware_Package_Variations">Known Firmware Package Variations</span></h4>
+<p>Some firmware packages may include an **End of Manufacturing Flash Protection Mode** status of Protected or Unprotected.
+</p>
+<div class="thumb tright"><div class="thumbinner" style="width:302px;"><a href="./File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html" class="image"><img alt="Figure 2: Firmware status information for an Intel DG2 device." src="../images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/300px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png" decoding="async" width="300" height="613" class="thumbimage" srcset="../images/thumb/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png/450px-Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 1.5x, ../images/2/28/Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png 2x" /></a> <div class="thumbcaption"><div class="magnify"><a href="./File:Figure_2-_Firmware_status_information_for_an_Intel_DG2_device..png.html" class="internal" title="Enlarge"></a></div>Figure 2: Firmware status information for an Intel DG2 device.</div></div></div>
+<p>Similar <a rel="nofollow" class="external text" href="https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/">SPI Write Protection</a> functionality is made available through Intel CPUs under <a href="https://en.wikipedia.org/wiki/System_Management_Mode" class="extiw" title="wikipedia:System Management Mode">System Management Mode (SMM)</a>.
+</p>
+<h3><span class="mw-headline" id="Embedded_Controllers">Embedded Controllers</span></h3>
+<p>This section will cover firmware images as they apply to various embedded controllers within the Intel GPU.
+</p>
+<h4><span class="mw-headline" id="GuC">GuC</span></h4>
+<p>The Graphics micro (µ) Controller (GuC) is an embedded controller contained within Intel's embedded and discrete graphics (DG*) series GPUs.
+</p>
+<h5><span class="mw-headline" id="Hardware_Architecture">Hardware Architecture</span></h5>
+<p><i>The following section is supported by <a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">igor-blue.github.io</a> (see reference <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&amp;_Reading_Material)">1</a>, <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&amp;_Reading_Material)">2</a>):</i>
+</p><p><i>"The GuC - an embedded <a rel="nofollow" class="external text" href="https://www.wikiwand.com/en/I486">i486</a> core that supports graphics scheduling, power management and firmware attestation."</i>
+</p>
+<h5><span class="mw-headline" id="Software_Architecture">Software Architecture</span></h5>
+<p><i>The following section is supported by <a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">igor-blue.github.io</a> (see reference <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&amp;_Reading_Material)">1</a>, <a rel="nofollow" class="external text" href="GPU_Firmware.html#References_(Talks_&amp;_Reading_Material)">2</a>):</i>
+</p><p><i>"The μOS kernel runs in 32-bit protected mode, with no paging and old-style segments model (CS, DS, etc’). All code run in ring0. The OS handles HW/SW exceptions and crashes, and supplies debugging and logging services."</i>
+</p><p><i>"It runs a single process - which initializes the system and then waits for interrupts/events in a loop."</i>
+</p>
+<h6><span id="GuC_Blob_Checksum_.26_Code_Signing"></span><span class="mw-headline" id="GuC_Blob_Checksum_&amp;_Code_Signing">GuC Blob Checksum &amp; Code Signing</span></h6>
+<p><i>"The bootrom verifies the firmware with a digital signature using a SHA256 hash + PKCSv2.1 RSA signature, and if the test passes copies it to SRAM and starts executing."</i>
+</p>
+<h2><span class="mw-headline" id="Nvidia">Nvidia</span></h2>
+<h3><span class="mw-headline" id="Firmware_Images_2">Firmware Images</span></h3>
+<p>This section will cover firmware images used in Nvidia GPUs.
+</p>
+<h3><span class="mw-headline" id="Embedded_Controllers_2">Embedded Controllers</span></h3>
+<p>This section will cover firmware images as they apply to various embedded controllers within the Nvidia GPU.
+</p>
+<h4><span id="Falcon_.2F_NV-RISCV"></span><span class="mw-headline" id="Falcon_/_NV-RISCV">Falcon / NV-RISCV</span></h4>
+<p>The Fast Logic CONtroller (Falcon) and Nvidia RISC-V (<a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2016/07/Tue1100_Nvidia_RISCV_Story_V2.pdf">NV-RISCV</a>) processors run the NvOS.
+</p>
+<h4><span class="mw-headline" id="GSP">GSP</span></h4>
+<p>The GPU System Processor (GSP) is an embedded controller used for offload of the RM Core.
+</p><p>The GSP runs <a rel="nofollow" class="external text" href="https://lwn.net/Articles/637658/">Library Operating System (LibOS)</a>.
+</p>
+<h5><span id="GSP_Initialization_.26_Offload"></span><span class="mw-headline" id="GSP_Initialization_&amp;_Offload">GSP Initialization &amp; Offload</span></h5>
+<p>The <a rel="nofollow" class="external text" href="GPU_Driver_Internals.html#Initialization_3">GSP is initialized multiple times</a> during the system's bring up and runtime.
+</p><p>GSP offload may occur during:
+</p>
+<ul><li>Hardware bring up when a cached version of the RM Core is loaded from SPI flash</li></ul>
+<ul><li>During host driver bring up when the RM Core is offloaded by the <a rel="nofollow" class="external text" href="OpenRM.html">OpenRM driver</a>.</li>
+<li>During guest driver bring up when the RM Core is offloaded.</li></ul>
+<table class="wikitable">
+<caption>Possible GSP Offloads
+</caption>
+<tbody><tr>
+<th>Load Source
+</th>
+<th>Payload
+</th>
+<th>Notes
+</th></tr>
+<tr>
+<td><a rel="nofollow" class="external text" href="https://wiki.segger.com/SPI_Flash">SPI Flash</a>
+</td>
+<td>Cached RM Core
+</td>
+<td>Used as a fallback in case of no rm offload.
+</td></tr>
+<tr>
+<td>OpenRM
+</td>
+<td>RM Core
+</td>
+<td>This is the RM Core which was traditionally contained in the proprietary RM driver.
+</td></tr>
+<tr>
+<td>VGX Guest
+</td>
+<td>Guest RM Core
+</td>
+<td>Future OpenRM guests may accomplish RM offload via GSP stubs (controlled via <a rel="nofollow" class="external text" href="https://github.com/NVIDIA/open-gpu-kernel-modules/blob/758b4ee8189c5198504cb1c3c5bc29027a9118a3/src/common/sdk/nvidia/inc/ctrl/ctrla081.h#L102">gspHeapSize</a>?).
+</td></tr></tbody></table>
+<h4><span class="mw-headline" id="CMU">CMU</span></h4>
+<h2><span class="mw-headline" id="AMD">AMD</span></h2>
+<h2><span id="References_.28Talks_.26_Reading_Material.29"></span><span class="mw-headline" id="References_(Talks_&amp;_Reading_Material)">References (Talks &amp; Reading Material)</span></h2>
+<ol><li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/10/graphics-part1.html">Security of the Intel Graphics Stack - Part 1 - Introduction</a></li>
+<li><a rel="nofollow" class="external text" href="https://igor-blue.github.io/2021/02/24/graphics-part2.html">Security of the Intel Graphics Stack - Part 2 - FW &lt;-&gt; GuC</a></li>
+<li><a rel="nofollow" class="external text" href="https://eclypsium.com/2022/09/19/firmware-security-realizations-part-3-spi-write-protections/">Firmware Security Realizations Part 3: SPI Write Protections</a></li>
+<li><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/fsp-firmware-solutions-iot-video.html">Intel® FSP: Firmware Solutions for the Internet of Things</a></li></ol>
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