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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-31 03:20:57 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-31 03:20:57 -0400 |
| commit | 6a48a4a2420cfe3171a135fe7621ec16967d2021 (patch) | |
| tree | 08f445a4a2558101c83f720dbad20189471fb995 /wiki/open-iov.org/index.php?title=Intel&action=edit.html | |
| parent | 667491fe59737ebfb327804d361b2eb0a8b170bb (diff) | |
| download | open-iov-6a48a4a2420cfe3171a135fe7621ec16967d2021.tar.gz open-iov-6a48a4a2420cfe3171a135fe7621ec16967d2021.zip | |
vgsp+diag: attr/pipeline prelude (families 0x1100-0x1200/0x2000-0x2060, dedup, 512w, program-pair VA record; emitted via patch_window relocation, run-aligned after MME prelude), mature-prelude gate (>=64 0x114 code words, sema_gr_prelude_gate_ms=60000 busy-defer), pin_gr_stream 0.75s pass, trap regs in sked sampler - first clean DS+MME (ds_esr=80000000 mme_esr=80000000, a2040a00 gone); 0x1168 CLASS ERROR persists as MME-MACRO-GENERATED WRITE (no 0x1168 header in emitted stream; macro(2) args [0,0,600000,0,610800]); next: disassemble macro (2) at pc 0xa + trapped-addr read pre-latch - SESSION 153 r1095-r1100
Diffstat (limited to 'wiki/open-iov.org/index.php?title=Intel&action=edit.html')
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