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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-09 19:27:48 -0500 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-09 19:27:48 -0500 |
| commit | a478f0b418bd3dd5fbcc6260979865160ca25cf0 (patch) | |
| tree | e29fb7ec56741b9be1d8e747c108cb661b89d6c2 /wiki/open-iov.org/images/4 | |
| parent | 4a2cf8292ad37767de22a26e7e35d0a8a06edad3 (diff) | |
| download | open-iov-a478f0b418bd3dd5fbcc6260979865160ca25cf0.tar.gz open-iov-a478f0b418bd3dd5fbcc6260979865160ca25cf0.zip | |
vgsp: raise the GSP engine event interrupt so guest ISR drains events and wakes poll() waiters
The emulated GSP only signalled the MSI-X eventfd when it queued a status
record. The guest's primary ISR (nvidia_isr) decides pending from the
CPU_INTR leaf registers, which we never set for the GSP stall vector, so it
returned IRQ_NONE: IRQ 33 counted thousands of interrupts while the nvidia
event thread sat idle and a client blocked in poll() on /dev/nvidia0 (a GLX
swap) waited forever even though the event was already in the status queue.
Mirror what a real GSP-RM does when it queues an event:
- program RISC-V IRQMASK/IRQDEST for SWGEN0 (read-only to the guest; the
GSP firmware owns them),
- set SWGEN0 in the falcon IRQSTAT,
- latch GSP stall vector 155 in the CPU interrupt tree (LEAF[4] bit 27,
UVM_SHARED subtree 2 -> TOP[0] bit 2),
- signal MSI-X.
Raise it only for POST_EVENT records (replies are polled by the client).
Verified on r1680: the guest now writes IRQSCLR SWGEN0, kgspService_TU102
drains events, and glxgears renders (was a hard hang).
Diffstat (limited to 'wiki/open-iov.org/images/4')
0 files changed, 0 insertions, 0 deletions
