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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-08 07:54:29 -0400
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-08 07:54:29 -0400
commitaabddc5e114569d1489f0dafe3e565f69edb6acd (patch)
tree8367f8ad17a4f453d14df15074b5f4675aae81c8 /wiki/GPU_Driver_Internals.md
parentc8ccdd772c7650f19d14f143f34b700813575746 (diff)
downloadopen-iov-aabddc5e114569d1489f0dafe3e565f69edb6acd.tar.gz
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sema: fix GR counter-slot mapping to fixed pool total (20)
The counter slot for GR rank r is 0x20400fec0 + (TOTAL-1-r)*0x10 with TOTAL the fixed pool total. The autoreg used a live high-water channel count instead; channels register progressively, so an early pass with a partial count (16) registered the ranks present at the wrong slots and every later rank's correct slot was then rejected as owned. Result: ranks 10..19 never got a counter, no counter was ever published, and the client's userspace tracker never advanced (cudaMalloc stall while the guest RM polled MC_SERVICE_INTERRUPTS). Validated on a live boot: 20/20 slots registered with 0 collisions (previously ranks 6..9 installed at the n_gr=16 mapping and ranks 10..19 rejected).
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