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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 19:45:12 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 19:46:02 -0400 |
| commit | 43c05ccc9640451b7b9fc371944b6e528524742e (patch) | |
| tree | 1a0655b6d5eab3eef6df2fd10e043ecb244506cd /userspace/tests | |
| parent | 0e89c75e3cbab07e56e28bef40dafbb459fa3d07 (diff) | |
| download | open-iov-43c05ccc9640451b7b9fc371944b6e528524742e.tar.gz open-iov-43c05ccc9640451b7b9fc371944b6e528524742e.zip | |
vgsp: add read-only gsp-phys-reg-probe debugfs register snapshot
Add a read-only BAR0 register-liveness probe at
/sys/kernel/debug/vgsp/gsp-phys-reg-probe that prints "name addr value"
for the PMC chip-id/clock gate, PGRAPH status/fault, SKED/HWW and
FECS/GPCCS falcon state, the front-end QMD virtual-window controls and
the GSP context registers, followed by decoded field lines.
Read-only (readl only); additive to gsp_phys_boot_debugfs_init(); no
ladder logic changed. Used to distinguish a clock/power-gated engine
from a halted or running one during a physical cycle.
Diffstat (limited to 'userspace/tests')
0 files changed, 0 insertions, 0 deletions
