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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-15 16:45:32 -0500 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-15 16:45:32 -0500 |
| commit | 45dbcdcd4bd9c21b367806251b41172f86afe0e9 (patch) | |
| tree | f5a1f029bd98e40f9aecad9255b76c4fc517be86 /tools | |
| parent | 37b4d5756977b92d2c9f65ff9f3fa36462309c18 (diff) | |
| download | open-iov-45dbcdcd4bd9c21b367806251b41172f86afe0e9.tar.gz open-iov-45dbcdcd4bd9c21b367806251b41172f86afe0e9.zip | |
vgsp: eng65 - allow per-stage SPH disable on the all-slots bind boot (TCS-off DS A/B)
c788 achieved DRAW_IAB (MME-FAST macro-status=00122266 mpc=614
mac=0x22 run=1 via MME-DRAW-MOVE) but the draw latched DS 0x84000420
(SPH5 VSB c1, SPH10 TCS c2, M_PIPE_STAGE TI) and stores stayed 0
(NOWRITE-CONFIRMED wrote=0). The DS-ESR post-clear=84000420 then the
retire reads ds=80000000, so the pending validation error is the draw's.
The per-stage disable mask was only honoured with sema_gl_sph_bind=0,
so the all-slots boot could not disable TCS while keeping the window's
own VSB bind and the other synth slots. Read the mask unconditionally;
default 0 keeps the emitted bytes identical. params-r1624 sets
sema_gl_sph_stage_disable=0x04 (TCS disable record 0x2080<-0x20, synth
j2 bind skipped) for the next A/B.
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/guest-diag/params-r1624.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/guest-diag/params-r1624.txt b/tools/guest-diag/params-r1624.txt index c97f0ee..c72a4a3 100644 --- a/tools/guest-diag/params-r1624.txt +++ b/tools/guest-diag/params-r1624.txt @@ -6,3 +6,4 @@ sema_gl_mme_partial_keep_window=1 sema_gl_mme_pack_keep_gen=1 sema_gl_mme_cb_ali sema_ddx_tracker_auth=1 sema_gl_mme_pack_carry=1 sema_gl_mme_pack_carry_ms=100 sema_gl_mme_pack_release=1 sema_gl_mme_pack_release_ms=100 sema_gl_sph_bind_pair_safe=1 sema_gl_mme_sa_golden_fill=1 sema_gl_mme_release_sa_arm=1 + sema_gl_sph_stage_disable=0x04 |