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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-12 23:25:00 -0500 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-12 23:25:00 -0500 |
| commit | 770d6b4af7f44acc104c6149b9c473de1db607e7 (patch) | |
| tree | 5422c6b1eb8547664c95b131edaccef446743e23 /tools/cuda-ab/run/streams2 | |
| parent | 6ebc7cd40b09b6c922e8b87209a74da60f347739 (diff) | |
| download | open-iov-770d6b4af7f44acc104c6149b9c473de1db607e7.tar.gz open-iov-770d6b4af7f44acc104c6149b9c473de1db607e7.zip | |
vgsp: flip-event delivery defaults to assoc+strict (clears Flip event timeout); DDX latch reset clauses
Wall (b) 'Flip event timeout on head 0' fix (validated c171): NVKMS/kernel-
callback events register hSrcResource=0, so every display UPDATE completion
rode the all-events shotgun (6-7 POST_EVENT records each), the guest's
status-queue read cursor fell 20-44 slots behind (rc=-11 ring-full bursts)
and flip records arrived past the 3 s NvDrm window. Default the r1765 pair
ON - gsp_rm_ev_assoc (hSrc==0 -> alloc-parent channel) and
gsp_disp_events_strict (armed UPDATE posts only to that channel's events,
no fallback) - the exact combination r1771 measured as '0 flip WARNs'.
Validating cycle c171: registrations carry real sources (hEvent=0x1007a
hSrc=0x1001b etc.), UPDATE posts are exact 1:1 (posts=27), WARN count 1 for
the boot, serial timeouts=0 (c160 pre-fix: 34). Both stay runtime-writable.
Also stage the gsp_sema_service.c candidates for wall (a) (the later-DMA
0x51 is a consequence of 'Failed to idle DMA' on a recycled channel): the
served-refusal in svc_userd_ddx_reprobe now exempts a latch reset to put==0,
and the put-reset latch keep extends to the DDX family (was kick-only).
These clauses target c171's observed reset/junk-adopt sequence; validation
pending on a roll where wall (a) is otherwise survivable.
Diffstat (limited to 'tools/cuda-ab/run/streams2')
0 files changed, 0 insertions, 0 deletions
