r431 sysmem leaf-PTE aperture fix (root-cause candidate): map every host dma_alloc_coherent page as SYSTEM_COHERENT (aperture 2) instead of SYSTEM_NON_COHERENT (3) - the reference RM picks the aperture from the allocation's CPU cache attribute, and non-coherent L2 let engine stores linger invisibly (the no-execute wedge) while re-staged copy-in content stayed invisible to the engine; gsp_phys_rmcall_pte_coh=0 restores the historical aperture for a boot-time A/B

1 files changed, 30 insertions, 1 deletions

diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index f43691d..5350f90 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -9631,9 +9631,38 @@ static u64 gsp_phys_rmcall_pde(u64 pa)
 	return 0xeull | ((pa >> 12) << 8);
 }
 
+/*
+ * r431 COHERENCY ROOT-CAUSE CANDIDATE: the leaf-PTE aperture for every host
+ * page this backend maps (the ladder windows, the win0 shadow pool, the
+ * bounce/data regions, the release/scratch shadows) was hardcoded to
+ * aperture 3 = SYSTEM_NON_COHERENT_MEMORY. The reference RM picks the
+ * aperture from the allocation's CPU cache attribute
+ * (fabric_vaspace.c:1123-1134): NV_MEMORY_CACHED -> SYSTEM_COHERENT (2),
+ * otherwise NON_COHERENT (3). Every page here is dma_alloc_coherent (CPU
+ * cached/coherent by construction), so 3 is wrong: the GPU's L2 does not
+ * snoop the CPU, which makes the engine's stores linger in L2 (the host's
+ * retire scan reads stale memory = the "no-execute wedge") and the host's
+ * re-staged copy-in content invisible to the engine (the retries re-read
+ * stale lines). gsp_phys_rmcall_pte_coh selects aperture 2 (default 1) for
+ * a one-flag A/B against the historical 3 (0); the PTEs are planted before
+ * the engine's first fetch, so the flag is boot-time only.
+ */
+static bool gsp_phys_rmcall_pte_coh_param = true;
+module_param_named(gsp_phys_rmcall_pte_coh, gsp_phys_rmcall_pte_coh_param,
+		   bool, 0444);
+MODULE_PARM_DESC(gsp_phys_rmcall_pte_coh,
+		 "r431: sysmem leaf-PTE aperture: 1 = SYSTEM_COHERENT (correct for dma_alloc_coherent host pages), 0 = SYSTEM_NON_COHERENT (historical)");
+
 static u64 gsp_phys_rmcall_pte(u64 pa)
 {
-	return 0xfull | ((pa >> 12) << 8);
+	/*
+	 * Low nibble: VALID (1) | APERTURE<<1 | VOL (8). Aperture 2 =
+	 * SYSTEM_COHERENT_MEMORY -> 1|4|8 = 0xd; aperture 3 = NON_COHERENT
+	 * -> 1|6|8 = 0xf.
+	 */
+	u64 base = gsp_phys_rmcall_pte_coh_param ? 0xdull : 0xfull;
+
+	return base | ((pa >> 12) << 8);
 }
 
 /*