gsp-phys: read-only falcon state probe for the boot rung

Logs both falcons' run/halt bits, the RISC-V active bit, WPR2 up/down and
the security-falcon mailboxes when the physical GPU is claimed. Verified
live: GSP and SEC2 halted, RISC-V inactive, WPR2 down (HI=0). This is the
read-only half of the real boot rung; no device state is written.

1 files changed, 42 insertions, 0 deletions

diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c
index fddfae1..df46c5a 100644
--- a/kernel/gsp_phys_gpu.c
+++ b/kernel/gsp_phys_gpu.c
@@ -43,6 +43,17 @@ MODULE_PARM_DESC(gsp_phys_fw, "GSP firmware image to load (default " GSP_PHYS_FW
 #define GSP_PHYS_GSP_MAILBOX1	0x00110044
 #define GSP_PHYS_GSP_CPUCTL	0x00110100
 #define GSP_PHYS_ENGINE		0x001103c0
+#define GSP_PHYS_RISCV_STATUS	0x00111240
+#define GSP_PHYS_WPR2_ADDR_LO	0x001fa824
+#define GSP_PHYS_WPR2_ADDR_HI	0x001fa828
+#define GSP_PHYS_SEC2_CPUCTL	0x00840100
+#define GSP_PHYS_SEC2_MAILBOX0	0x00840040
+#define GSP_PHYS_SEC2_MAILBOX1	0x00840044
+
+/* Falcon CPUCTL bits (same encoding on the GSP and SEC2 falcons). */
+#define GSP_PHYS_CPUCTL_STARTCPU	BIT(1)
+#define GSP_PHYS_CPUCTL_HALTED		BIT(4)
+#define GSP_PHYS_RISCV_ACTIVE		BIT(0)
 
 struct gsp_phys_gpu {
 	struct pci_dev *pdev;
@@ -197,6 +208,35 @@ static void gsp_phys_unmap(struct pci_dev *pdev)
 	}
 }
 
+/*
+ * Rung 3 stage 3a: read-only falcon state probe. Logs the boot-relevant
+ * register state before any boot attempt: both falcons' run/halt bits, the
+ * RISC-V active bit, WPR2 up/down and the security-falcon mailboxes (the
+ * booter reports its result there).
+ */
+static void gsp_phys_dump_falcon(void)
+{
+	u32 gsp_cpuctl = readl(phys.bar0 + GSP_PHYS_GSP_CPUCTL);
+	u32 sec2_cpuctl = readl(phys.bar0 + GSP_PHYS_SEC2_CPUCTL);
+	u32 riscv = readl(phys.bar0 + GSP_PHYS_RISCV_STATUS);
+	u32 wpr2_lo = readl(phys.bar0 + GSP_PHYS_WPR2_ADDR_LO);
+	u32 wpr2_hi = readl(phys.bar0 + GSP_PHYS_WPR2_ADDR_HI);
+
+	pr_info("gsp-phys: GSP falcon CPUCTL=0x%08x [%s%s]\n", gsp_cpuctl,
+		gsp_cpuctl & GSP_PHYS_CPUCTL_STARTCPU ? "started " : "",
+		gsp_cpuctl & GSP_PHYS_CPUCTL_HALTED ? "halted" : "running");
+	pr_info("gsp-phys: SEC2 falcon CPUCTL=0x%08x [%s%s] MAILBOX0=0x%08x "
+		"MAILBOX1=0x%08x\n", sec2_cpuctl,
+		sec2_cpuctl & GSP_PHYS_CPUCTL_STARTCPU ? "started " : "",
+		sec2_cpuctl & GSP_PHYS_CPUCTL_HALTED ? "halted" : "running",
+		readl(phys.bar0 + GSP_PHYS_SEC2_MAILBOX0),
+		readl(phys.bar0 + GSP_PHYS_SEC2_MAILBOX1));
+	pr_info("gsp-phys: RISCV_STATUS=0x%08x [%sactive] WPR2_LO=0x%08x "
+		"WPR2_HI=0x%08x [%s]\n", riscv,
+		riscv & GSP_PHYS_RISCV_ACTIVE ? "" : "not ",
+		wpr2_lo, wpr2_hi, wpr2_hi ? "up" : "down");
+}
+
 static int gsp_phys_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	u32 boot0, boot1;
@@ -254,6 +294,8 @@ static int gsp_phys_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		readl(phys.bar0 + GSP_PHYS_ENGINE),
 		readl(phys.bar0 + GSP_PHYS_FALCON_OS));
 
+	gsp_phys_dump_falcon();
+
 	phys.pdev = pdev;
 	phys.claimed = true;
 	pr_info("gsp-phys: claimed %s\n", pci_name(pdev));