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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 11:05:24 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 11:05:24 -0400 |
| commit | a9202a257373aee9e469947b0327df88ab556347 (patch) | |
| tree | 40426699fd3d1b693229ea7b6fc316b352e315fd /kernel/memory.c.iommu | |
| parent | 0af8085561305d4df339bf641e12f6dff429553b (diff) | |
| download | open-iov-a9202a257373aee9e469947b0327df88ab556347.tar.gz open-iov-a9202a257373aee9e469947b0327df88ab556347.zip | |
gr-regs/vgsp: sample PGRAPH_INTR + PGRAPH_INTR_EN at the dispatch window
The m75/m78/m79 launch windows show FECS_CTXSW_STATUS_FE_0.GR_INTR_REQ
(bit17) asserted through the SKED CWD ACTIVE state and a following CTXSW_REQ
(bit0) that results in the context save/unload. The real driver carries
GR_INTR only transiently during its context load and clears it before ACTIVE.
The PGRAPH interrupt latch (0x400100) names what the engine is signaling
(e.g. ILLEGAL_METHOD bit4, SEMAPHORE bit1, NOTIFY); sampled by the external
sampler and dumped in the launch post-mortem.
Diffstat (limited to 'kernel/memory.c.iommu')
0 files changed, 0 insertions, 0 deletions