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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-28 09:09:13 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-28 09:09:13 -0400 |
| commit | 448d1d9a6f9168006910a79e177d4bed331bacc6 (patch) | |
| tree | 5e628d80c4a07f1e6f50824ba63ce2a42715f399 /kernel/main.c | |
| parent | 17e1f522e4e9e04d13c4ca9495a2f4f1bdc58c36 (diff) | |
| download | open-iov-448d1d9a6f9168006910a79e177d4bed331bacc6.tar.gz open-iov-448d1d9a6f9168006910a79e177d4bed331bacc6.zip | |
sem: run GR channels - accept CE methods on subchannel 0, discover GR rings
- The CE semaphore/memset method groups also arrive on subchannel 0 (CUDA's
push library binds the copy class on compute channels to carry the
work-submission releases), so the stream decoder accepts both 0 and 4.
- GR (compute) channel rings live in the same video-memory allocation as the
CE rings, 0x3000 bytes per channel after them: ring (0x2000) at
ce_end + 0x3000*rank, USERD at +0x2000. Discover and pin them once the CE
ranks are known; verified against ring entry 0 (1 MB aligned push VA in
the client window, sane length) and the USERD's put/get, so a layout
change costs a failed pin, not a wrong one. Gated by sema_gr_rings
(default on).
- memprobe: require the sem-VA triple in the sem-object scanner (a bare
qword in the window matches thousands of unrelated pointers once the
ring/pushbuffer windows are part of the range).
Live evidence: ring entries read through the guest's /proc/pid/mem decode to
the GR channels' first pushes; pinning the ring (fb 0x140000+0x3000*rank),
USERD (ring+0x2000) and first-push pages made all 20 GR channels execute
their entry 0 for the first time (get=1 sub=1).
Diffstat (limited to 'kernel/main.c')
| -rw-r--r-- | kernel/main.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/kernel/main.c b/kernel/main.c index f23be27..4f7f9ee 100644 --- a/kernel/main.c +++ b/kernel/main.c @@ -2265,6 +2265,14 @@ module_param_cb(chan_dump, &nv_vgpu_chan_dump_ops, NULL, 0200); MODULE_PARM_DESC(chan_dump, "Dump the sema service channel table (any value)"); /* + * GR ring discovery: pin the compute channels' rings/USERDs, which follow the + * CE rings in the channel video-memory allocation. Default on; set 0 to leave + * GR channels untranslated when debugging push-execution side effects. + */ +module_param_named(sema_gr_rings, gsp_sema_gr_rings, bool, 0644); +MODULE_PARM_DESC(sema_gr_rings, "Auto-discover+pin GR channel rings (default 1)"); + +/* * Debug: inject a verified {GPU VA -> guest PA} translation into the * semaphore service (used when the client's mapping cannot be discovered * from guest structures): |