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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-22 17:07:34 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-22 17:07:34 -0400 |
| commit | bc58d7e1c97e7a189adec5f61e46b5c570acfc9b (patch) | |
| tree | f3cbcc65026c9f18abddc32c72e1f8dd7bfcbaab /kernel/gsp_sema_service.h | |
| parent | b366b162a4442f694639d7622a0e00f0cfc6fee8 (diff) | |
| download | open-iov-bc58d7e1c97e7a189adec5f61e46b5c570acfc9b.tar.gz open-iov-bc58d7e1c97e7a189adec5f61e46b5c570acfc9b.zip | |
r494 the GL 3D-channel classification: NV2080_ENGINE_TYPE_GRAPHICS (1) is a GR channel
With the real-GSP KGR snapshot in place the X driver's 3D-engine selection
succeeds; the next wall was 'Failed to initialize DMA' / 'Failed to allocate
push buffer' - the X driver's pushbuffer NOP test never saw its GPFIFO entry
consumed. Root: the wire's NV_CHANNEL_ALLOC_PARAMS engineType carries
NV2080_ENGINE_TYPE_* (NULL=0, GR0/GRAPHICS=1, COPY0=9); CUDA's kernel-RM GR
channels arrive with NULL=0 and the progress service's convention is
'engine_type == 0 means GR', so the X/GL 3D channel's real GR0 value 1 was
misclassified as a CE - the CE path then demanded a ring translation the
channel does not have (rrc=-2 'norrng'), never probed the USERD, and the pump
never executed a single entry (submissions=0 at the 10 s timeout).
Normalize GR0..GR7 (1..8) to 0 at channel registration; every other engine
id is >= COPY0 (9) so no CE can be captured. Also fixes the KGR snapshot
max-size constant: KGR_GET_INFO is 3712 bytes (8 engines x 58 x 8), which
the 1664-byte cap silently dropped - the one snapshot the engine selection
actually needs.
Diffstat (limited to 'kernel/gsp_sema_service.h')
0 files changed, 0 insertions, 0 deletions
