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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-07 02:12:31 -0500 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-11-07 02:12:31 -0500 |
| commit | e6a21a49f50929ed8010d52378a180afeb7eb39c (patch) | |
| tree | 5c6b96a87138acd3b328d48c72a1b0bac7e5619d /kernel/gsp_sema_service.c | |
| parent | 56dadb41d6644c602b494059288410b1872b0fa6 (diff) | |
| download | open-iov-e6a21a49f50929ed8010d52378a180afeb7eb39c.tar.gz open-iov-e6a21a49f50929ed8010d52378a180afeb7eb39c.zip | |
vgsp-gl: author the PS/TCS stage images for the emitted mask slots
Diffstat (limited to 'kernel/gsp_sema_service.c')
| -rw-r--r-- | kernel/gsp_sema_service.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/kernel/gsp_sema_service.c b/kernel/gsp_sema_service.c index 6972172..e42e23d 100644 --- a/kernel/gsp_sema_service.c +++ b/kernel/gsp_sema_service.c @@ -10587,14 +10587,25 @@ static void svc_gl_flush(struct nv_vgpu_device *vgpu, ~(u64)(SEMA_PAGE_SIZE - 1); u32 k; - for (k = 0; gsp_phys_rmcall_gr_sph_bind_value() && - k < 2u && n_recs < SVC_GL_PROG_MAX; k++) { + /* + * CONT 25: author exactly the slots the booter emits. + * The booter emits j5 (PS) on mask 0x20 and j2 (TCS) + * on 0x04 when the all-slots bool is off; gate each + * image on the same condition instead of the bool + * alone (the r1575 zero-PS re-capture). + */ + for (k = 0; k < 2u && n_recs < SVC_GL_PROG_MAX; k++) { + u32 slot_bit = k ? 0x04u : 0x20u; u64 dst = fam + (k ? 0x200u : 0x0u); const u8 *b = k ? svc_gl_vs : svc_gl_ps; u32 bl = k ? svc_gl_vs_len : svc_gl_ps_len; bool dup = false; u32 pi3; + if (!(gsp_phys_rmcall_gr_sph_bind_value() || + (gsp_phys_rmcall_gr_sph_bind_mask_value() & + slot_bit))) + continue; if (!b || bl < 4u) continue; for (pi3 = 0; pi3 < svc_gl.n_progs; pi3++) |