r481 sema_push_raw diagnostic: dump the decoded method stream of the first N large GR-class pushes (default 0 off, no behaviour change) so the launch push's acquire/release method groups are visible verbatim; needed to prove which ordering mechanism the driver relies on for async-stream H2D -> kernel dependencies (streams_events st2 vadd copy-in ran ~115 ms before its stream's H2D soft copies)

1 files changed, 61 insertions, 0 deletions

diff --git a/kernel/gsp_sema_service.c b/kernel/gsp_sema_service.c
index ea96595..eddc73d 100644
--- a/kernel/gsp_sema_service.c
+++ b/kernel/gsp_sema_service.c
@@ -8985,6 +8985,60 @@ static void svc_qmd_accum(struct nv_vgpu_device *vgpu, struct svc_channel *ch,
 
 static u64 svc_pass_hash;	/* r391f: this decode pass's push content hash */
 
+/*
+ * r481 RISK-REDUCTION diagnostic (default 0): dump the full decoded method
+ * stream of the first few large GR-class pushes (len >= 1024) so the launch
+ * push's acquire/release method groups (or their absence) are visible
+ * verbatim. The streams_events class evidence shows the st2 vadd's copy-in
+ * running ~115 ms BEFORE its stream's H2D soft copies; the ordering the
+ * driver relied on is only provable by reading the push's own methods.
+ * Bounded: gsp_sema_push_raw dumps, at most once per push VA.
+ */
+unsigned gsp_sema_push_raw;
+static u64 svc_pushraw_last_va;
+static u32 svc_pushraw_n;
+
+static void svc_push_raw_dump(const u8 *buf, u32 len, u64 push_va,
+			      u32 h_object)
+{
+	u32 off = 0, gi = 0;
+
+	if (svc_pushraw_n >= gsp_sema_push_raw || !gsp_sema_push_raw)
+		return;
+	if (push_va == svc_pushraw_last_va)
+		return;
+	svc_pushraw_last_va = push_va;
+	svc_pushraw_n++;
+	pr_info("sema-pushraw: BEGIN h=0x%x va=0x%llx len=%u n=%u\n",
+		h_object, push_va, len, svc_pushraw_n);
+	while (off + 4 <= len && gi < 128) {
+		u32 hdr, cnt, addr, v[8], k, n;
+
+		memcpy(&hdr, buf + off, 4);
+		if ((hdr >> 29) != 1) {
+			pr_info("sema-pushraw:  off=0x%x raw=%08x (not a method header)\n",
+				off, hdr);
+			break;
+		}
+		cnt = (hdr >> 16) & 0xfff;
+		addr = (hdr & 0x1fff) << 2;
+		n = cnt > 8 ? 8 : cnt;
+		for (k = 0; k < n && off + 4 + 4 * k + 4 <= len; k++)
+			memcpy(&v[k], buf + off + 4 + 4 * k, 4);
+		pr_info("sema-pushraw:  [%u] off=0x%x addr=0x%x cnt=%u v0=%08x v1=%08x v2=%08x v3=%08x v4=%08x\n",
+			gi, off, addr, cnt,
+			n > 0 ? v[0] : 0, n > 1 ? v[1] : 0,
+			n > 2 ? v[2] : 0, n > 3 ? v[3] : 0,
+			n > 4 ? v[4] : 0);
+		if (!cnt)
+			break;
+		off += 4 + cnt * 4;
+		gi++;
+	}
+	pr_info("sema-pushraw: END h=0x%x va=0x%llx consumed=0x%x/%u\n",
+		h_object, push_va, off, len);
+}
+
 static void svc_decode_stream(struct nv_vgpu_device *vgpu, const u8 *buf,
 			      u32 len, u64 page_pa, bool allow_ops,
 			      struct svc_channel *ch, u32 entry_idx,
@@ -9049,6 +9103,13 @@ static void svc_decode_stream(struct nv_vgpu_device *vgpu, const u8 *buf,
 		allow_ops = false;
 	}
 
+	/*
+	 * r481: verbatim method-stream dump for large GR-class pushes
+	 * (default 0 = off). See svc_push_raw_dump.
+	 */
+	if (gsp_sema_push_raw && ch && !ch->engine_type && len >= 1024)
+		svc_push_raw_dump(buf, len, push_va, ch->h_object);
+
 	memset(&st, 0, sizeof(st));
 	st.push_va = push_va;
 	/*