kernel: coherent GSP-RM replies for engine-context creation

- GSP_RM_ALLOC: echo the request payload back with status forced to NV_OK.
  The kernel driver copies the reply params over the caller's params buffer
  using the class-expected size, so a zeroed reply smashed libcuda's stack
  (SIGSEGV at the engine-registration continuation); echoing makes the
  copy-back idempotent.
- CE_GET_PHYSICAL_CAPS / CE_GET_ALL(_PHYSICAL)_CAPS: report sysmem, P2P and
  BL copy caps and mark the GR-synchronous CE (GRCE, COPY0). Without a GRCE
  the client's context walk ends with an empty secondary-engine record and
  the engine RM alloc is issued with class 0 (rejected -> cuCtxCreate fails).
- TU104 engine table: CE0 shares the GR PBDMA ids (the driver's GR/GRCE
  runqueue validation requires it), plus an entry for the async copy engine
  (COPY14) advertised in the GSP static info engine caps.
- tools/guest-diag/ioctl_trace: decode the RM status fields of alloc,
  control and free so the first failing driver call is visible in traces.

gitignore: keep the CUDA analysis scratch tree (incl. WORKING-HERE.md) local.

1 files changed, 44 insertions, 5 deletions

diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h
index 6a19726..74d1ba3 100644
--- a/kernel/gsp_rm_tu104.h
+++ b/kernel/gsp_rm_tu104.h
@@ -142,6 +142,7 @@ struct tu104_get_constructed_falcon_info_params {
 #define TU104_ENG_CE2		0x793ceb02
 #define TU104_ENG_CE3		0x793ceb03
 #define TU104_ENG_CE4		0x793ceb04
+#define TU104_ENG_CES		0x793ceb0e	/* classId(OBJCE) inst 14 (async) */
 #define TU104_ENG_NVDEC0	0x8f99e100	/* classId(OBJBSP)=0x8f99e1, inst 0 */
 #define TU104_ENG_NVDEC1	0x8f99e101
 #define TU104_ENG_NVENC0	0xe97b6c00	/* classId(OBJMSENC)=0xe97b6c, inst 0 */
@@ -159,6 +160,7 @@ struct tu104_get_constructed_falcon_info_params {
 #define TU104_RM_ENGINE_CE2		0x0b
 #define TU104_RM_ENGINE_CE3		0x0c
 #define TU104_RM_ENGINE_CE4		0x0d
+#define TU104_RM_ENGINE_CES		0x17	/* RM_ENGINE_TYPE_COPY14 */
 #define TU104_RM_ENGINE_NVDEC0		0x1d
 #define TU104_RM_ENGINE_NVDEC1		0x1e
 #define TU104_RM_ENGINE_NVENC0		0x25
@@ -178,6 +180,7 @@ struct tu104_get_constructed_falcon_info_params {
 #define TU104_MC_ENGINE_CE2		17
 #define TU104_MC_ENGINE_CE3		18
 #define TU104_MC_ENGINE_CE4		19
+#define TU104_MC_ENGINE_CES		29	/* MC_ENGINE_IDX_CE14 */
 #define TU104_MC_ENGINE_NVDEC0		65
 #define TU104_MC_ENGINE_NVDEC1		66
 #define TU104_MC_ENGINE_NVENC0		38
@@ -193,6 +196,7 @@ struct tu104_get_constructed_falcon_info_params {
 #define TU104_FAULT_ID_CE2		17
 #define TU104_FAULT_ID_CE3		18
 #define TU104_FAULT_ID_CE4		19
+#define TU104_FAULT_ID_CES		29
 #define TU104_FAULT_ID_NVDEC0		10
 #define TU104_FAULT_ID_NVDEC1		25
 #define TU104_FAULT_ID_NVENC0		11
@@ -241,6 +245,7 @@ struct tu104_get_constructed_falcon_info_params {
 #define TU104_TAG_CE2			3
 #define TU104_TAG_CE3			4
 #define TU104_TAG_CE4			5
+#define TU104_TAG_CES			6
 #define TU104_TAG_NVDEC0		10
 #define TU104_TAG_NVDEC1		11
 #define TU104_TAG_NVENC0		13
@@ -282,7 +287,7 @@ static const struct tu104_fifo_device_entry tu104_engine_table[] = {
 		.numPbdmas     = 1,
 		.engineName    = "GRAPHICS",
 	},
-	/* [1] CE0 */
+	/* [1] CE0 - the GR-synchronous CE (GRCE); shares the GR PBDMA */
 	{
 		.engineData = {
 			[EI_ENG_DESC]       = TU104_ENG_CE0,
@@ -302,8 +307,8 @@ static const struct tu104_fifo_device_entry tu104_engine_table[] = {
 			[EI_CHRAM_PRI_BASE]       = 0,
 			[EI_KERNEL_RM_MAX]        = 0,
 		},
-		.pbdmaIds      = {1, 0},
-		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 1, 0},
+		.pbdmaIds      = {0, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 0, 0},
 		.numPbdmas     = 1,
 		.engineName    = "CE0",
 	},
@@ -407,7 +412,36 @@ static const struct tu104_fifo_device_entry tu104_engine_table[] = {
 		.numPbdmas     = 1,
 		.engineName    = "CE4",
 	},
-	/* [6] NVDEC0 */
+	/* [6] CES - async copy engine (RM COPY14 / OBJCE instance 14).
+	 * Clients (libcuda) refuse to finish context creation without it: the
+	 * async/secondary engine record stays empty and the engine-context RM
+	 * alloc is issued with class 0. Not on a runlist of its own; shares the
+	 * CE runlist. */
+	{
+		.engineData = {
+			[EI_ENG_DESC]       = TU104_ENG_CES,
+			[EI_FIFO_TAG]       = TU104_TAG_CES,
+			[EI_RM_ENGINE_TYPE] = TU104_RM_ENGINE_CES,
+			[EI_RUNLIST]        = 5,
+			[EI_MMU_FAULT_ID]   = TU104_FAULT_ID_CES,
+			[EI_RC_MASK]        = TU104_RC_CE4,
+			[EI_RESET]          = 5,
+			[EI_INTR]           = 5,
+			[EI_MC]             = TU104_MC_ENGINE_CES,
+			[EI_DEV_TYPE_ENUM]  = TU104_PTOP_TYPE_LCE,
+			[EI_INSTANCE_ID]    = 14,
+			[EI_RUNLIST_PRI_BASE]     = 0,
+			[EI_IS_HOST_DRIVEN_ENGINE] = 1,
+			[EI_RUNLIST_ENGINE_ID]    = 0,
+			[EI_CHRAM_PRI_BASE]       = 0,
+			[EI_KERNEL_RM_MAX]        = 0,
+		},
+		.pbdmaIds      = {5, 0},
+		.pbdmaFaultIds = {TU104_PBDMA_FAULT_ID_BASE + 5, 0},
+		.numPbdmas     = 1,
+		.engineName    = "CES",
+	},
+	/* [7] NVDEC0 */
 	{
 		.engineData = {
 			[EI_ENG_DESC]       = TU104_ENG_NVDEC0,
@@ -559,7 +593,7 @@ static const struct tu104_fifo_device_entry tu104_engine_table[] = {
 	},
 };
 
-#define TU104_ENGINE_TABLE_SIZE	12
+#define TU104_ENGINE_TABLE_SIZE	13
 
 /* ============================================================
  * TU104 Interrupt Table (from intr_phys_tu102.c, kernel table)
@@ -706,6 +740,7 @@ static const struct tu104_internal_device_info tu104_internal_device_table[] = {
 #define TU104_CTRL_CE_GET_CE_PCE_MASK			0x20802a02
 
 /* CE capability bits (NV2080_CTRL_CE_CAPS_*, ctrl2080ce.h: byte:bit) */
+#define TU104_CE_CAPS0_GRCE		0x01	/* synchronous with GR (GRCE) */
 #define TU104_CE_CAPS0_SYSMEM_READ	0x04
 #define TU104_CE_CAPS0_SYSMEM_WRITE	0x08
 #define TU104_CE_CAPS0_SYSMEM		0x20
@@ -721,6 +756,10 @@ static const struct tu104_internal_device_info tu104_internal_device_table[] = {
 /* ENGINE_TYPE_COPY0 = 0x9, COPY(i) = COPY0 + i (cl2080_notification.h) */
 #define TU104_ENGINE_TYPE_COPY0	0x00000009
 #define TU104_NUM_CES		5
+/* The GR-synchronous CE (GRCE): the one sharing the GR PBDMA. Clients pick
+ * it as their compute companion (ceForCompute); the driver accepts a CE on
+ * the GR runqueue only when it shares GR's PBDMA ids. */
+#define TU104_GRCE_IDX		0
 #define TU104_CTRL_INTERNAL_GMMU_GET_STATIC_INFO	0x20800a59
 #define TU104_CTRL_STATIC_KGR_GET_GLOBAL_SM_ORDER	0x20800a22
 #define TU104_CTRL_STATIC_KGR_GET_INFO		0x20800a2a