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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
| commit | 4649ee9c83584b2a59b2c72ce67a1f08d3240810 (patch) | |
| tree | 89771f293d99f33eefb87126ea4d3c113ec53f2e /kernel/gsp_rm_tu104.h | |
| parent | ffa76c353e28437535e10388d64734ac06f93b9f (diff) | |
| download | open-iov-4649ee9c83584b2a59b2c72ce67a1f08d3240810.tar.gz open-iov-4649ee9c83584b2a59b2c72ce67a1f08d3240810.zip | |
gsp-rm: fill GR info indices 7/9/0x17/0x22 (libcuda clock-table path; e94 TPC count)
Diffstat (limited to 'kernel/gsp_rm_tu104.h')
| -rw-r--r-- | kernel/gsp_rm_tu104.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h index ac90e38..7cd5a4b 100644 --- a/kernel/gsp_rm_tu104.h +++ b/kernel/gsp_rm_tu104.h @@ -958,15 +958,29 @@ struct tu104_gr_static_info { }; /* infoList indices we populate (ctrl0080gr.h) */ +#define TU104_GR_INFO_IDX_SHADER_PIPE_COUNT 0x07 +#define TU104_GR_INFO_IDX_SHADER_PIPE_SUB_COUNT 0x09 #define TU104_GR_INFO_IDX_LITTER_NUM_GPCS 0x14 #define TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC 0x17 #define TU104_GR_INFO_IDX_GPU_CORE_COUNT 0x1d #define TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC 0x20 +#define TU104_GR_INFO_IDX_RT_CORE_COUNT 0x22 #define TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC 0x2a #define TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT 0x2c #define TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT 0x2d #define TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT 0x2e +/* Values libcuda fetches through NV2080_CTRL_CMD_GR_GET_INFO (0x20801201) + * by info index (host-oracle observed on TU104): index 9 feeds the + * ucode-image clock table (devstate+0xe94 == TPC count 24); index 0x17 + * feeds the same table (devstate+0xb0 TPC / +0xb4 SM count); 7 and 0x22 + * feed the SM/RT caps. Zero here makes FUN_003e35f0 reject the clock + * table with NV_ERR_INVALID_ARGUMENT (cuCtxCreate rc=999). */ +#define TU104_GR_INFO_SHADER_PIPE_COUNT 6 +#define TU104_GR_INFO_SHADER_PIPE_SUB_COUNT 24 +#define TU104_GR_INFO_LITTER_NUM_TPC_PER_GPC 6 +#define TU104_GR_INFO_RT_CORE_COUNT 48 + /* TU104 max subcontexts (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT) */ #define TU104_MAX_SUBCONTEXT_COUNT 64 |