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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-07 02:53:24 -0500
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-07 02:53:24 -0500
commita4210abc27634294cba528a3e6e450076cb3161e (patch)
treee215c78fe4e27ee92fc4530efebfd30654cd1052 /kernel/gsp_rm_emulation.c
parente6a21a49f50929ed8010d52378a180afeb7eb39c (diff)
downloadopen-iov-a4210abc27634294cba528a3e6e450076cb3161e.tar.gz
open-iov-a4210abc27634294cba528a3e6e450076cb3161e.zip
vgsp-rm: report GPU GART size + DMA flags in BUS_GET_INFO_V2
Diffstat (limited to 'kernel/gsp_rm_emulation.c')
-rw-r--r--kernel/gsp_rm_emulation.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c
index d0f9e61..ceb3314 100644
--- a/kernel/gsp_rm_emulation.c
+++ b/kernel/gsp_rm_emulation.c
@@ -2845,6 +2845,11 @@ static void gsp_rm_handle_clk_domain_info(struct gsp_emu_context *ctx, u32 cmd,
* sysmem connection type"). Report a PCIe Gen3 x16 link for the emulated
* vGPU and echo every requested index.
*/
+static u32 gsp_rm_bus_gart_mb = 4096;
+module_param_named(bus_gart_mb, gsp_rm_bus_gart_mb, uint, 0644);
+MODULE_PARM_DESC(bus_gart_mb,
+ "BUS_GET_INFO_V2 GPU_GART_SIZE in MiB (default 4096; 0 = historical zero reply, A/B)");
+
static u32 tu104_bus_info_data(u32 index)
{
switch (index) {
@@ -2865,6 +2870,14 @@ static u32 tu104_bus_info_data(u32 index)
return TU104_PCIE_LINK_CTRL_STATUS_GEN3_X16;
case TU104_BUS_INFO_IDX_SYSMEM_CONNECTION_TYPE:
return TU104_BUS_INFO_SYSMEM_CONN_PCIE;
+ case TU104_BUS_INFO_IDX_GPU_GART_SIZE:
+ return READ_ONCE(gsp_rm_bus_gart_mb);
+ case TU104_BUS_INFO_IDX_GPU_GART_SIZE_ALT:
+ return 0;
+ case TU104_BUS_INFO_IDX_GPU_GART_DMA_FLAGS_0:
+ case TU104_BUS_INFO_IDX_GPU_GART_DMA_FLAGS_1:
+ /* GPUGART | CTXDMA (bits 0 | 2). */
+ return 0x5u;
default:
return 0;
}