r651-r653 display path: DISPLAY_GET_STATIC_INFO reports the one-head/8-window model (feHwSysCap head-0, windowPresentMask 0xff, numDispChannels 81 for the cursor channel numbers) - live gdb pinned the 0x56 to kdispGetChannelNum_v03_00 requiring windowPresentMask&NVBIT32(instance) for dispChnClass_Win and HEAD_EXISTS for Curs; + INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (displayMask=1 numHeads=1; dispswConstruct rejected every head against numHeads=0); + NVC370_CTRL_CMD_GET_CHANNEL_INFO reports IDLE immediately (nvRMSyncEvoChannel polls 2s for IDLE after every kickoff)

1 files changed, 129 insertions, 3 deletions

diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c
index ec6ca20..54ae801 100644
--- a/kernel/gsp_rm_emulation.c
+++ b/kernel/gsp_rm_emulation.c
@@ -1913,7 +1913,20 @@ static void gsp_rm_handle_bus_get_pci_bar_info(struct gsp_emu_context *ctx,
  * 36 bytes (observed paramsSize): feHwSysCap(0) windowPresentMask(4)
  * bFbRemapperEnabled(8) numHeads(12) i2cPort(16) internalDispActiveMask(20)
  * embeddedDisplayPortMask(24) muxSupported(28) numDispChannels(32).
- * Report a minimal headless display: 1 head, 1 (core) channel.
+ *
+ * r651: this reply is also the gate for the WINDOW-channel alloc path.
+ * Live gdb on the guest nvidia.ko pinned the display path 0x56 to
+ * kdispGetChannelNum_v03_00: for dispChnClass_Win it requires
+ * pStaticInfo->windowPresentMask & NVBIT32(instance) and returns
+ * NV_ERR_NOT_SUPPORTED (0x56) when the bit is clear; the Curs class reads
+ * HEAD_EXISTS bits from feHwSysCap the same way (0x49+instance channel num).
+ * The previous reply left both masks zero, so nvRmApiAlloc(0xc57e) died in
+ * the guest's local resource construct (clientAllocResource ->
+ * resservResourceFactory -> dispchnConstruct -> kdispGetChannelNum) before
+ * any GSP-RM RPC was issued. Report the same one-head / 8-window model the
+ * NV0073 shim and the caps notifier expose (feHwSysCap head-0 exists,
+ * windowPresentMask bits 0..7, numDispChannels covering the cursor channel
+ * numbers 73..80, i.e. 81 entries).
  */
 static void gsp_rm_handle_display_get_static_info(struct gsp_emu_context *ctx,
 						  u32 sequence,
@@ -1925,15 +1938,115 @@ static void gsp_rm_handle_display_get_static_info(struct gsp_emu_context *ctx,
 
 	memset(out_params, 0, 36);
 
+	/*
+	 * feHwSysCap: NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) occupies bit i
+	 * (dev_disp.h v03_00); head 0 exists on the emulated board.
+	 */
+	val32 = 0x1;
+	memcpy(out_params + 0, &val32, 4);
+
+	/*
+	 * windowPresentMask: bit i = window instance i present. Mirrors the
+	 * caps notifier's SYS_CAPB=0xff and the NV0073 window assignment
+	 * (windows 0/1 flexible) - eight usable windows.
+	 */
+	val32 = 0xff;
+	memcpy(out_params + 4, &val32, 4);
+
 	val32 = 1;	/* numHeads */
 	memcpy(out_params + 12, &val32, 4);
-	val32 = 1;	/* numDispChannels (core channel) */
+
+	/*
+	 * numDispChannels sizes pClientChannelTable[], indexed by the packed
+	 * channel number kdispGetChannelNum returns: CORE=0, WIN(i)=1+i,
+	 * WINIM(i)=33+i, CURS(i)=73+i. Cover CURS(7)=80 -> 81 entries so any
+	 * instance the guest allocates stays in bounds.
+	 */
+	val32 = 81;
 	memcpy(out_params + 32, &val32, 4);
 
 	*out_params_size = 36;
 	*out_status = 0;
 
-	nv_vgpu_info(ctx->vgpu, "vgsp-rm: DISPLAY_GET_STATIC_INFO -> heads=1 dispChannels=1");
+	nv_vgpu_info(ctx->vgpu,
+		     "vgsp-rm: DISPLAY_GET_STATIC_INFO -> heads=1 dispChannels=81 winMask=0xff feHwSysCap=0x1");
+}
+
+/*
+ * INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES (0x20800a5d)
+ *
+ * dispswConstruct_IMPL (disp_sw.c) asks for {displayMask, numHeads} and
+ * rejects every logicalHeadId >= numHeads with "invalid logical head
+ * number: N" + NV_ERR_INSUFFICIENT_RESOURCES; the generic all-zero reply
+ * made numHeads = 0, so nvkms' DISPLAY_SW objects could not be constructed
+ * on any head (observed r653: heads 0..3 all rejected -> vkCreateDevice -3).
+ * Report the same one-head model as DISPLAY_GET_STATIC_INFO: display id 0
+ * active, one head.
+ *
+ * Params ABI (NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS,
+ * 8 bytes): displayMask(0) numHeads(4).
+ */
+static void gsp_rm_handle_display_active_devices(struct gsp_emu_context *ctx,
+						 u32 *out_status, u8 *out_params,
+						 u32 *out_params_size)
+{
+	u32 displayMask = 0x1;	/* display id 0 */
+	u32 numHeads = 1;
+
+	memcpy(out_params + 0, &displayMask, 4);
+	memcpy(out_params + 4, &numHeads, 4);
+
+	*out_params_size = 8;
+	*out_status = 0;
+
+	nv_vgpu_info(ctx->vgpu,
+		     "vgsp-rm: DISPLAY_GET_ACTIVE_DISPLAY_DEVICES -> displayMask=0x1 numHeads=1");
+}
+
+/*
+ * NVC370_CTRL_CMD_GET_CHANNEL_INFO (0xc3700104)
+ *
+ * nvRMSyncEvoChannel() (nvkms-rm.c) polls this control through the display
+ * object after every EVO channel kickoff and waits up to 2 s for the channel
+ * to report NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE, otherwise it logs
+ * "Idling display engine timed out: <class>:<instance>:<sd>:<token>" and
+ * fails the whole modeset init (observed on the r652 window path: 0xc57d and
+ * 0xc57e instances 0/1). The emulated display engine has no pushbuffer
+ * consumer, so the state would never leave BUSY; report IDLE immediately.
+ *
+ * Params ABI (NVC370_CTRL_CMD_GET_CHANNEL_INFO_PARAMS, 20 bytes):
+ *   subdeviceIndex(0) channelClass(4) channelInstance(8)
+ *   IsChannelInDebugMode(12) channelState(16 = NVBIT(0) IDLE).
+ * Echo the request so class/instance round-trip and set the state word.
+ */
+static void gsp_rm_handle_display_channel_info(struct gsp_emu_context *ctx,
+					       const u8 *in_params, u32 in_size,
+					       u32 *out_status, u8 *out_params,
+					       u32 *out_params_size)
+{
+	u32 idle = 1;	/* NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE */
+	u32 class_id = 0, instance = 0;
+	u32 size = in_size;
+
+	if (size > 64)
+		size = 64;	/* defensive cap; the real params are 20 bytes */
+	if (size >= 20) {
+		memcpy(out_params, in_params, size);
+		memcpy(&class_id, in_params + 4, 4);
+		memcpy(&instance, in_params + 8, 4);
+		memcpy(out_params + 16, &idle, 4);
+	} else {
+		memset(out_params, 0, 20);
+		memcpy(out_params + 16, &idle, 4);
+		size = 20;
+	}
+
+	*out_params_size = size;
+	*out_status = 0;
+
+	nv_vgpu_info(ctx->vgpu,
+		     "vgsp-rm: GET_CHANNEL_INFO class=0x%x instance=%u -> IDLE",
+		     class_id, instance);
 }
 
 /*
@@ -3777,6 +3890,19 @@ static void gsp_rm_handle_rm_control(struct gsp_emu_context *ctx,
 			reply + GSP_RM_CTRL_HDR_SIZE, &out_params_size);
 		break;
 
+	case 0xc3700104: /* NVC370_CTRL_CMD_GET_CHANNEL_INFO */
+		gsp_rm_handle_display_channel_info(ctx,
+			req_data + GSP_RM_CTRL_HDR_SIZE, req.paramsSize,
+			&out_status,
+			reply + GSP_RM_CTRL_HDR_SIZE, &out_params_size);
+		break;
+
+	case 0x20800a5d: /* NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES */
+		gsp_rm_handle_display_active_devices(ctx,
+			&out_status,
+			reply + GSP_RM_CTRL_HDR_SIZE, &out_params_size);
+		break;
+
 	case 0x730102:	/* NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS */
 	case 0x730287:	/* NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK */
 	case 0x7302ad:	/* NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT */