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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 10:19:13 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 10:19:13 -0400 |
| commit | bfbe85f50f5243e601d98fe40b43e364c3e8901f (patch) | |
| tree | 755674d61d8c3e739b8d5d573925cce7e17cc7fb /kernel/gsp_phys_gpu.h | |
| parent | ea9130180949fd72eca534e4f5a83336ad7e5d4a (diff) | |
| download | open-iov-bfbe85f50f5243e601d98fe40b43e364c3e8901f.tar.gz open-iov-bfbe85f50f5243e601d98fe40b43e364c3e8901f.zip | |
vgsp: m76 - R2 lane tail (TSG PREEMPT bWait + device-sched off + perf boost)
The real client's context-creation tail after the lane-enable trio is
#1073 NVA06C_CTRL_CMD_PREEMPT on the TSG with bWait=1, #1075
NV0080 device-sched disable, #1077 PERF_BOOST_SET_2X. The explicit preempt
makes the RM perform a clean context save/switch-out at setup time so the
first dispatch loads the context normally; without it our lane's context sits
loaded from the ladder and task activation ends in a save/unload instead of
execution (m72/m73/m75 signature). Gated by gsp_phys_rmcall_gr_lane_tail
(default 0).
Diffstat (limited to 'kernel/gsp_phys_gpu.h')
| -rw-r--r-- | kernel/gsp_phys_gpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h index ebed0cb..3a590ea 100644 --- a/kernel/gsp_phys_gpu.h +++ b/kernel/gsp_phys_gpu.h @@ -354,6 +354,10 @@ int gsp_phys_rmcall_gr_inst_sys_value(void); * ordering; default 0 = legacy R1-after-F2). */ int gsp_phys_rmcall_gr_r1_first_value(void); +/* m76: send the R2 #1073/#1075/#1077 lane tail after the mode-35 lane + * enable (TSG preempt bWait, device-sched off, perf boost; default 0). */ +int gsp_phys_rmcall_gr_lane_tail_value(void); + /* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * 0 = FERMI_VASPACE_A is allocated IS_EXTERNALLY_OWNED (historical ladder |