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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 13:28:37 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 13:28:37 -0400 |
| commit | a58eb29859c55fc38c30bc9433b5dfd16ae9e4d2 (patch) | |
| tree | 083847d99451cf793bb3f0ca2cd7daac917b67d4 /kernel/gsp_phys_gpu.c | |
| parent | 359345cdda1d047fb1e2ba5259502ec47a7aac37 (diff) | |
| download | open-iov-a58eb29859c55fc38c30bc9433b5dfd16ae9e4d2.tar.gz open-iov-a58eb29859c55fc38c30bc9433b5dfd16ae9e4d2.zip | |
vgsp: m95 - program GPC MMU_CTRL from PFB MMU_CTRL (RM grInitGPCMmuPRIRegs copy)
The real RM initialises every GPC's NV_PGPC_PRI_MMU_CTRL (0x500880 +
gpc*0x8000) from NV_PFB_PRI_MMU_CTRL (0x100C80) using the TU102
hub-to-GPC matching fields (VM_PG_SIZE, COMP_FAULT, MISS_GRAN, CACHE_MODE,
USE_PDB_BIG_PAGE_SIZE, ATOMIC_CAPABILITY_MODE, ATOMIC_CAPABILITY_SYS_NCOH;
ext-tree gr_gk104.c:3340-3380 + gr_tu102.c:229-238). Our ladder never
programmed it (grep-verified). The m93 INST dump shows the server's SC(0)
PDB carries USE_VER2_PT_FORMAT + BIG_PAGE_SIZE=1, so a GPC/hub MMU_CTRL
mismatch is a candidate for the GPC-side walker refusing the SM I-fetch
with MMU_NACK while hub-side reads resolve. Gated by
gsp_phys_rmcall_gr_gpc_mmu_init (default 0); sampler now reads
GPC0/GPC1_MMU_CTRL (0x500880/0x508880) and PFB_MMU_CTRL (0x100C80).
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index 629bd3a..3b2feb4 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -994,6 +994,24 @@ int gsp_phys_rmcall_gr_ptr_guest_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_ptr_guest_value); /* + * m95: program each GPC's MMU_CTRL from the hub's PFB MMU_CTRL (the real RM's + * grInitGPCMmuPRIRegs matching-fields copy) before a forwarded launch. The + * GPC-side walker refuses the SM I-fetch with MMU_NACK while hub-side reads + * resolve; a GPC/hub MMU_CTRL mismatch is one candidate. Default 0. + */ +static int gsp_phys_rmcall_gr_gpc_mmu_init_param; +module_param_named(gsp_phys_rmcall_gr_gpc_mmu_init, + gsp_phys_rmcall_gr_gpc_mmu_init_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_gpc_mmu_init, + "Program GPC MMU_CTRL from PFB MMU_CTRL matching fields before a forwarded launch (default 0)"); + +int gsp_phys_rmcall_gr_gpc_mmu_init_value(void) +{ + return gsp_phys_rmcall_gr_gpc_mmu_init_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_gpc_mmu_init_value); + +/* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * The H1 GR promote wall is a direct consequence of the ladder's * externally-owned FERMI_VASPACE_A: with IS_EXTERNALLY_OWNED the RM treats |