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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 23:50:00 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 23:50:00 -0400 |
| commit | 374292ae2d6379ffab6ed5b7eeedf712581365ab (patch) | |
| tree | 49a5b7a934d7c559219d56a036fc6f1ae7b43f19 /kernel/gsp_phys_gpu.c | |
| parent | 8948759ebdfd1372829222c03c90edfa44d93d72 (diff) | |
| download | open-iov-374292ae2d6379ffab6ed5b7eeedf712581365ab.tar.gz open-iov-374292ae2d6379ffab6ed5b7eeedf712581365ab.zip | |
vgsp: m69 - window-0 shadow pool for the QMD program/param pages
m68 proved the program page's shadow copy contains real SASS (SASS_version
0x75) and the prefetch pair is fixed, yet the engine still never completes
and never writes its release anywhere - including a window-0 module sem.
Best remaining suspect: the window-1 scratch VA range (PT chain installed by
DMA_UPDATE_PDE_2 pdeIndex=1) has never been proven readable by the GR engine
core, unlike the window-0 GPFIFO/PB/QMDWIN small-PT line. m69 plants 8
module pages at VAs 0x108000..0x10f000 (slots 0x108..0x10f, same 128 B PT
fetch line, planted before first fetch like qmdwin), copies the resolved
program/param page content into them at launch and rewrites the QMD pointer
pairs there (param=32, program=48). Param: gsp_phys_rmcall_gr_shadow_win0.
Diffstat (limited to 'kernel/gsp_phys_gpu.c')
| -rw-r--r-- | kernel/gsp_phys_gpu.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/kernel/gsp_phys_gpu.c b/kernel/gsp_phys_gpu.c index 3429507..1029b2e 100644 --- a/kernel/gsp_phys_gpu.c +++ b/kernel/gsp_phys_gpu.c @@ -746,6 +746,27 @@ int gsp_phys_rmcall_faultbuf_sys_value(void) EXPORT_SYMBOL_GPL(gsp_phys_rmcall_faultbuf_sys_value); /* + * m69 window-0 shadow pool (gsp_phys_rmcall_gr_shadow_win0; default 0). When + * set, the forwarded GR launch copies the QMD's program/param pages into the + * window-0 shadow pool (module pages at VAs 0x108000..0x10f000, PTEs planted + * at stage 3 in the proven GPFIFO/PB/QMDWIN small-PT line) and rewrites the + * QMD pointer pairs there, instead of mapping them through the window-1 + * scratch range whose DMA_UPDATE_PDE_2 PT chain has never been proven + * readable by the GR engine core. + */ +static int gsp_phys_rmcall_gr_shadow_win0_param; +module_param_named(gsp_phys_rmcall_gr_shadow_win0, + gsp_phys_rmcall_gr_shadow_win0_param, int, 0644); +MODULE_PARM_DESC(gsp_phys_rmcall_gr_shadow_win0, + "Copy forwarded GR program/param pages into the window-0 shadow pool (proven PT line; default 0)"); + +int gsp_phys_rmcall_gr_shadow_win0_value(void) +{ + return gsp_phys_rmcall_gr_shadow_win0_param; +} +EXPORT_SYMBOL_GPL(gsp_phys_rmcall_gr_shadow_win0_value); + +/* * Ladder VAS ownership selector (gsp_phys_rmcall_vas_shared; default 0). * The H1 GR promote wall is a direct consequence of the ladder's * externally-owned FERMI_VASPACE_A: with IS_EXTERNALLY_OWNED the RM treats |