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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-06 21:06:54 -0500
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-06 21:06:54 -0500
commiteca8e29dcaf4d31ba0f97518d0b408c3e79412cb (patch)
tree7698f4b92f4cec58f852020975aa02528d485076 /kernel/gsp_phys_booter.c
parent88e0b15326a7bacb6c02f351b26a4b28a7933ad8 (diff)
downloadopen-iov-eca8e29dcaf4d31ba0f97518d0b408c3e79412cb.tar.gz
open-iov-eca8e29dcaf4d31ba0f97518d0b408c3e79412cb.zip
vgsp-gl: GS-mode/FASTGS variants for the synth GS SPH
Diffstat (limited to 'kernel/gsp_phys_booter.c')
-rw-r--r--kernel/gsp_phys_booter.c54
1 files changed, 52 insertions, 2 deletions
diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index fdd8e88..213aa22 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -18657,6 +18657,29 @@ u32 gsp_phys_rmcall_gr_sph_gs_maps_value(void)
{
return READ_ONCE(gsp_phys_rmcall_gr_sph_gs_maps);
}
+
+/*
+ * SESSION 155 CONT 13: GS-mode context variant for the synthesized GS SPH.
+ * The mesh per-primitive dummy-GS contract (the only driver precedent for
+ * a fake GS SPH) requires ENABLE_FAST_G_S in the header and writes
+ * SET_GS_MODE(FAST_GS) + POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK. Our replay
+ * channel never receives those (the client has no GS program). Bit j:
+ * 1 = set FASTGS in the SPH header and emit
+ * 0x0208 <- 1 (SET_GS_MODE FAST_GS)
+ * 0x1240..0x125c <- 0 (POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK)
+ * 2 = enable the stage (final SET_PIPELINE_SHADER(4) = 0x41)
+ * Default 0 = the CONT 11 disabled/no-fastgs form.
+ */
+static u32 gsp_phys_rmcall_gr_sph_gs_mode;
+module_param_named(sema_gl_sph_gs_mode, gsp_phys_rmcall_gr_sph_gs_mode,
+ uint, 0644);
+MODULE_PARM_DESC(sema_gl_sph_gs_mode,
+ "Synth GS SPH mode bits: 1=FASTGS header + SET_GS_MODE(FAST_GS)+skip-mask, 2=enable stage (0x41); 0=disabled/no-fastgs (default)");
+
+u32 gsp_phys_rmcall_gr_sph_gs_mode_value(void)
+{
+ return READ_ONCE(gsp_phys_rmcall_gr_sph_gs_mode);
+}
static bool gsp_phys_gr_mme_pairs_emitted; /* launch emitted a pair run */
static u32 gsp_phys_gr_mme_pairs_gen; /* gen whose pairs retired OK */
static u32 gsp_phys_gr_mme_launch_gen; /* last built launch's gen */
@@ -29715,6 +29738,8 @@ gr_page_unmapped:
*/
bool emit_gsimg =
READ_ONCE(gsp_phys_rmcall_gr_sph_gs_img);
+ u32 gs_mode =
+ READ_ONCE(gsp_phys_rmcall_gr_sph_gs_mode);
/*
* SESSION 155 CONT 9: the prelude is prepended ahead of
@@ -29918,7 +29943,8 @@ gr_page_unmapped:
(emit_j2 ? (bind_binding ? 8u : 7u) : 0u) +
(emit_j4 ? (bind_binding ? 8u : 7u) : 0u) +
(emit_j5 ? (bind_binding ? 8u : 7u) : 0u) +
- (emit_gsimg ? 9u : 0u) <= 96u) {
+ (emit_gsimg ? (9u + ((gs_mode & 1u) ? 11u : 0u)) : 0u)
+ <= 96u) {
/*
* SESSION 155 CONT 9: pair_safe emits each
* synthesized stage's SET_PIPELINE_SHADER
@@ -30135,9 +30161,33 @@ gr_page_unmapped:
(0x2114u >> 2);
in[nfin++] = (u32)(gva >> 32) & 0xffu;
in[nfin++] = (u32)gva & 0xfffffffcu;
+ /*
+ * CONT 13: the mesh-dummy GS
+ * contract also writes the GS mode
+ * and the post-VTG attribute skip
+ * mask (both zero default state).
+ */
+ if (gs_mode & 1u) {
+ in[nfin++] = 0x20000000u |
+ (1u << 16) |
+ (0x0208u >> 2);
+ in[nfin++] = 0x1u;
+ in[nfin++] = 0x20000000u |
+ (8u << 16) |
+ (0x1240u >> 2);
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ in[nfin++] = 0u;
+ }
in[nfin++] = 0x20000000u | (1u << 16) |
(0x2100u >> 2);
- in[nfin++] = 0x40u;
+ in[nfin++] = (gs_mode & 2u) ? 0x41u :
+ 0x40u;
}
/*
* nrun counts only the ADDRESS-bearing