vgsp: eng65 - allow per-stage SPH disable on the all-slots bind boot (TCS-off DS A/B)

c788 achieved DRAW_IAB (MME-FAST macro-status=00122266 mpc=614
mac=0x22 run=1 via MME-DRAW-MOVE) but the draw latched DS 0x84000420
(SPH5 VSB c1, SPH10 TCS c2, M_PIPE_STAGE TI) and stores stayed 0
(NOWRITE-CONFIRMED wrote=0). The DS-ESR post-clear=84000420 then the
retire reads ds=80000000, so the pending validation error is the draw's.

The per-stage disable mask was only honoured with sema_gl_sph_bind=0,
so the all-slots boot could not disable TCS while keeping the window's
own VSB bind and the other synth slots. Read the mask unconditionally;
default 0 keeps the emitted bytes identical. params-r1624 sets
sema_gl_sph_stage_disable=0x04 (TCS disable record 0x2080<-0x20, synth
j2 bind skipped) for the next A/B.

1 files changed, 12 insertions, 3 deletions

diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index 74b0300..e927d2d 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -32400,9 +32400,18 @@ gr_page_unmapped:
 			 * all-slots knob is off, matching the r1561 bool's
 			 * !sph_bind_all gate.
 			 */
-			u32 stage_disable_mask = !sph_bind_all ?
-				(READ_ONCE(gsp_phys_rmcall_gr_sph_stage_disable) &
-				 0x3fu) : 0u;
+			/*
+			 * eng65 DS A/B: the per-stage disable mask used to be
+			 * gated on !sph_bind_all, so the current campaign's
+			 * sema_gl_sph_bind=1 boot could not disable one stage
+			 * (TCS/VSA) while keeping the window's own binds and
+			 * the other synth slots. The mask defaults to 0, so
+			 * the emitted bytes are unchanged unless a bit is set;
+			 * the gate now allows the A/B on the all-slots boot.
+			 */
+			u32 stage_disable_mask =
+				READ_ONCE(gsp_phys_rmcall_gr_sph_stage_disable) &
+				0x3fu;
 			bool stage_disable = stage_disable_mask != 0u;
 			bool emit_j2 = !(stage_disable_mask & 0x04u) &&
 				       (sph_bind_all || (sph_bind_mask & 0x04u));