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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 12:55:38 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 12:55:38 -0400 |
| commit | 3dd883f43c325f942b25be1accad82c7b431520c (patch) | |
| tree | 6b6f869af0e7ebb762615c2c5997853e82f62ab7 /kernel/gsp_phys_booter.c | |
| parent | 1052a4162a7b4440ed7b55cbebccebc5577ba0ee (diff) | |
| download | open-iov-3dd883f43c325f942b25be1accad82c7b431520c.tar.gz open-iov-3dd883f43c325f942b25be1accad82c7b431520c.zip | |
gr-regs: capture the faulting SM's WARP_ESR_PC/PC_HI and GPCMMU ESR
m90 decoded the TPC0 SM0 warp error as ESR.ERROR=0x20 ADDR_ERROR_TYPE=0xb
= MMU_NACK (the ESR.ERROR field is an enum, not a bitmask). Add the 4R
companion words (ESR_MASK 0x734, PC 0x738, PC_HI 0x73c) for GPC0/TPC0/SM0
and GPC1/TPC0/SM0 plus the per-GPC GPCMMU ESR at +0x324 so the next cycle
captures the faulting PC and the MMU-side latch.
Diffstat (limited to 'kernel/gsp_phys_booter.c')
0 files changed, 0 insertions, 0 deletions