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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-01 10:07:14 -0400
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-01 10:07:14 -0400
commitc295a1b785efd01547f7d86dc30270360edf817a (patch)
tree56e7c4e061536bdaee2319aad08dd4e80faa15b2 /kernel/firmware_analyzer.c
parent4b39627e2bed5d2dfe8b4b909516f8fa3094cb5a (diff)
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gsp-phys: real GSP boot stages 3d/3e and the GSP-RM run-sequencer event
Stage 3d stages the GSP-RM boot from host sysmem (FMC, radix3 over the GSP-RM ELF, signature, message queues, libos LOGINIT/LOGRM/RMARGS and GSP arguments) and runs Booter Load on SEC2: GSP RISC-V reset, libos mailbox, IMEM/DMEM direct load, BOOTVEC=0, M0==0, FALCON_OS, RISC-V active. Stage 3e links the status queue and polls for GSP-RM events; it now also executes the inline run-sequencer command buffer (event 0x1002) against BAR0 (REG_WRITE/MODIFY/POLL, DELAY, STORE, CORE_* including CORE_RESUME) and then waits for GSP_INIT_DONE 0x1001. Gated by gsp_phys_boot / gsp_phys_boot_dryrun (default off; the normal load path writes nothing). gsp_phys_fwsec=1 without gsp_phys_boot=1 is refused: a FWSEC-only carve cannot pass the booter-unload handoff gate. Release quiesces the GSP, runs the existing FWSEC-SB/booter-unload teardown and frees all staging. tools/gen_gsp_bindata.py decodes the public generated archives into the Booter Load image (prod signature patched at 0x8700) and the GSP-RM boot (FMC) image; both are self-checked at build time.
Diffstat (limited to 'kernel/firmware_analyzer.c')
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