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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-26 12:07:01 -0400
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-26 12:07:01 -0400
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docs/04-real-render-walls: SESSION 133 section 13 - the SASS delivery shape is FOUND (the driver embeds the program bytes INLINE in a CE LAUNCH_DMA push: in=0x120a00004 -> out=0x205000, 4096 B/run; the Vulkan CE channels carry the same-shaped entries) and the three gates that keep the copies from running are named: the CE ring/USERD boot-lottery (FB convention matched r763 only; the real USERDs sit at 0xfee00/0xff000/0xff200 so the rings are at unaligned offsets like 0xefe00), the VAS age-out vs CE grace race (sema_vas_cand_ms=5000 registers at +5s), and the volatile ring/USERD content that a periodic shadow scan misses; next steps: USERD-shape-derived ring resolution or first-submission latch, then the inline copies and the n_data wiring
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