vgsp: eng65 - allow per-stage SPH disable on the all-slots bind boot (TCS-off DS A/B)

c788 achieved DRAW_IAB (MME-FAST macro-status=00122266 mpc=614
mac=0x22 run=1 via MME-DRAW-MOVE) but the draw latched DS 0x84000420
(SPH5 VSB c1, SPH10 TCS c2, M_PIPE_STAGE TI) and stores stayed 0
(NOWRITE-CONFIRMED wrote=0). The DS-ESR post-clear=84000420 then the
retire reads ds=80000000, so the pending validation error is the draw's.

The per-stage disable mask was only honoured with sema_gl_sph_bind=0,
so the all-slots boot could not disable TCS while keeping the window's
own VSB bind and the other synth slots. Read the mask unconditionally;
default 0 keeps the emitted bytes identical. params-r1624 sets
sema_gl_sph_stage_disable=0x04 (TCS disable record 0x2080<-0x20, synth
j2 bind skipped) for the next A/B.

0 files changed, 0 insertions, 0 deletions