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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-02 11:44:31 -0400 |
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| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-02 11:44:31 -0400 |
| commit | 1c99bfbeffff04529f6f669601fdf835a73778da (patch) | |
| tree | 5867bab46e5848541df36c703f6fd8d6d0256e54 /debug/risc-v-gsp-rm-vm/sim/__init__.py | |
| parent | 2fd653044127a665e4677a2cdfb58120d7b3e16b (diff) | |
| download | open-iov-1c99bfbeffff04529f6f669601fdf835a73778da.tar.gz open-iov-1c99bfbeffff04529f6f669601fdf835a73778da.zip | |
rename (cosmetic): green-eye -> risc-v-gsp-rm-debugger in user-facing names, docs, CLI, launcher and CI workflow; internal greeneye package/module identifiers unchanged (includes in-flight greeneye module edits present in the tree)
Diffstat (limited to 'debug/risc-v-gsp-rm-vm/sim/__init__.py')
| -rw-r--r-- | debug/risc-v-gsp-rm-vm/sim/__init__.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/risc-v-gsp-rm-vm/sim/__init__.py b/debug/risc-v-gsp-rm-vm/sim/__init__.py index 5d7ab1f..ad20893 100644 --- a/debug/risc-v-gsp-rm-vm/sim/__init__.py +++ b/debug/risc-v-gsp-rm-vm/sim/__init__.py @@ -1,4 +1,4 @@ -"""green-eye native RV64IMAC simulator (M1). +"""risc-v-gsp-rm-debugger native RV64IMAC simulator (M1). Pure-Python, deterministic, stdlib-only. :class:`sim.machine.Machine` executes RV64IMAC from a 256 MiB RAM region with an NS16550A UART; the debugger-facing |