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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-01 20:30:44 -0400
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-10-01 20:30:44 -0400
commitd8abca80d93bc944cb53b4e797b7440e12e71f69 (patch)
tree9835dfcf1d39b3f41e45a17d65ca012978b3b123 /config
parente7fdfca258b268e23753305882b2a8b8e40f4824 (diff)
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gsp-phys: build the channel page directory and submit the CE copy through GPU VAs
Fill the external VAS root's GP10X v2 hierarchy (root/PD2/PD1/PD0-small/PT) around a 2 MB VA window so the PDBMA/CE can fetch the GPFIFO and pushbuffer by GPU VA; gpFifoOffset and the GPFIFO ring entry GET now carry those VAs. Allocate the USERD page in FBMEM (class 0x40, matching the reference default) with the sysmem chunk as fallback, and add the advisory TSG-level GPFIFO_SCHEDULE 0xa06c0101 after the channel BIND/schedule. Log the window, table DMAs and entries, and expose them in the debugfs state snapshot.
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