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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 12:48:02 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-07 12:48:02 -0400 |
| commit | 512b5c35bf5b939745889df362cf8eba77321afe (patch) | |
| tree | 7a121b8cd81179f6fbddfccc18c772cd0761be2e /config | |
| parent | 00d26377ab5b3e2903f848edd3243d020e6089b4 (diff) | |
| download | open-iov-512b5c35bf5b939745889df362cf8eba77321afe.tar.gz open-iov-512b5c35bf5b939745889df362cf8eba77321afe.zip | |
gr-regs: sample the faulting TPCs' SM HWW_WARP_ESR/ESR_INFO registers
GPC0/TPC0 and GPC1/TPC0 raised the exception (GPC_EXCEPTION bit16 = TPC0
bitmap). SM warp ESR registers (TPC aperture = GPC base + 0x4000 +
tpc*0x800; SM stride 0x80; ESR 0x730, INFO 0x76c) at 0x504730.. and 0x50c730..
carry the exact error code (ILLEGAL_INSTR_ENCODING 0x9, INVALID_CONST_ADDR_LDC
0x12, MMU_FAULT 0x17, MISALIGNED_PC 0x5, ...) plus the VEID/warp info.
Diffstat (limited to 'config')
0 files changed, 0 insertions, 0 deletions