STATE-CURRENT: hourly check-back snapshot (2026-11-06 19:12:01)

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 # Open-IOV Current State
 
+> **Snapshot: 2026-11-06 ~19:00 (SESSION 155 continued; r1562 committed
+> post-reboot; HEAD `2f5b838c`, 1 unpushed; supersedes the ~12:55 entry
+> below).** The DS SPH validation wall narrowed to a single bit this
+> afternoon: r1562 (per-stage synth SPH disable mask, `2f5b838c`) reached
+> `ds 80000000->81040000` = **SPH18 only** (GS check2, the geometry-stage
+> attribute map) with the client's own stage VAs
+> (0x01990900/0x01990300/0x01990200/0x01990000 across j0/j1/j2/j5). Two
+> fixes got there: the pair-safe synth bind (`fe03bfe8`) emits the class's
+> own END ahead of a carried-open BEGIN/END pair and orders TYPE/
+> REGISTER_COUNT before the SPH address pair - the r1558 EC 0x0d
+> ILLEGAL_METHOD_IN_BEGIN_END class is gone (r1560: 13 beef launches,
+> 3 DS-FAST, 0 Class Error); and the client's own stage-disable records
+> (`0x2000<-0`, `0x2080<-0x20`, `0x20c0<-0x30`, `0x2100<-0x40`) cleared
+> the VSB 5/7 tess-mode pair (r1561), proving the DS validates every
+> stage - even a disabled one. The DS bitmap is decoded: `SPH<n>`,
+> n = stage*4 + check over VSA/VSB/TCS/TES/GS/PS, with four checks
+> (type/version, mpipe/stage binding, attribute map, stream-out).
+>
+> The r1562 run then poisoned (`badf1201` priv-error, TSG preempt +
+> resched) and entered the known GR timeout/wedge cascade (MME-REGS /
+> FETCH-WIT / MME-FAST spin, 18:47:21); the VM was closed and the host was
+> rebooted cleanly (logind `systemd-reboot` 18:47:20-24; pstore empty, no
+> crash). The reboot is not recorded in the acting handoff (last write
+> 17:59) - reason inferable from dmesg; no post-reboot plan written
+> there. Post-reboot: fresh boot 18:47:56; apt nvidia 570.211.01 green
+> (RTX 2080 Super Max-Q); `vgsp` was down at the check moment; the acting
+> session resumed the stack at 18:56 (vfio prereqs) and r1563 is in
+> preparation (18:57).
+>
+> Afternoon wave since the 12:55 entry: `5fad0adb` (slot-selective
+> `sema_sph_bind_mask`), `c822fa34` (engine-visible MME selector + RT0
+> third-dimension seeds), `3bb62602` (bounded setup-push hold; hold>0
+> stalls the ring behind the unreadable 60216 B setup entry - 0 is the
+> reproducible base), `fe03bfe8` (pair-safe + per-stage bind disable),
+> `91a4b48e` (docs: real render walls), `2f5b838c` (r1562). Earlier in
+> the wave (r1541-r1558): the PS-stage-only bind, the `0x2390`
+> CB-selector poison fix, the EC 0xd2 colour-target third-dimension
+> decode and the completed RT0 bind - the draw validates and stage5
+> populates.
+>
+> Honest state: GATE1 still not met - r1561's two captures 60 s apart are
+> identical and nonblack=0 (black 800x600 window and black root); the
+> best copy-out is 1-2 engine-changed pages that do not land on the
+> visible surface. Milestone position: between M-GL1 and M-GL2. Estimate
+> (subjective): GS 18 is a single named wall (GS-specific attribute/
+> stream state - glxgears emits no GEOMETRY SPH), first non-black frames
+> hours-to-days if it behaves like its predecessors; 60 fps/no-forcing
+> and a video on the emulated vGPU weeks after that; full CUDA breadth,
+> multi-VM and Windows months.
+>
+> CUDA front unchanged (backgrounded while graphics holds the device; its
+> 10-30 status stands): `41343c63` green (`victory_mail` `VADD bad=0` +
+> `STATUS OK`; `vecadd_loop` 100 launches PASS); the fresh-boot battery's
+> red class is D2H-stage with release-discipline fixes staged; the
+> SESSION 143 Vulkan fence regression is not re-measured. Watch next:
+> r1563's DS bitmap (does GS 18 clear?), then a non-poison DS transition
+> with >2 changed pages before any pixel capture.
+>
 > **Snapshot: 2026-11-06 ~12:55 (SESSION 155 continued; r1538 live;
 > HEAD `81bde9b7`; supersedes the ~01:00 entry below).** The graphics
 > campaign moved from "the DRAW macro executes" to "**the first calls-kept