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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 22:50:15 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-10-06 22:50:15 -0400 |
| commit | d0a1ca21d24b4d05385d95eefa9930e505206b8f (patch) | |
| tree | 7d861da9134ddb5f923c358231ba524ad1a4ab75 /SBOM.md | |
| parent | 457cc086936a2733cf4e7e9be04fa5b850d3b0cf (diff) | |
| download | open-iov-d0a1ca21d24b4d05385d95eefa9930e505206b8f.tar.gz open-iov-d0a1ca21d24b4d05385d95eefa9930e505206b8f.zip | |
vgsp: mode 35 m62 readback + m63 E2 lane-enable tail
m62 diagnostic: V7 instance/ramfc on host-visible sysmem chunks so the
server's WFI-pointer/TARGET-bit writes are decodable (captured lane uses
unreadable FBMEM slices); decode calls post-promotes and post-construct.
m63 E2: send the real CUDA lane-enable tail after stage-4 schedules
(R2 #1059 NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE flags=CILP_SET
hChannelGroup=TSG cilp=CILP on the subdevice, #1061
NVA06C_CTRL_CMD_SET_TIMESLICE 0x800 on the TSG, #1063 NV01 device
0x00802009 enable=1). Ground truth: live real CUDA runs with
FECS_CURRENT_CTX VALID=1; our m61 snapshots show V7's context never valid,
and the SKED CWD table never leaves the cold value. Best-effort, mode-35
only.
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