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| author | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
|---|---|---|
| committer | Arthur Hanson Rasmusson <arthur@vgpu.io> | 2026-09-30 04:04:22 -0400 |
| commit | e4c3f8554d70dcf22567621528a4601d7444666b (patch) | |
| tree | 24fd8eeb2af00d8b6434b06e28f2fb2b1b50fffd | |
| parent | 13a75bcb0e0be7fa8a4e90b9bda91a791e9d919f (diff) | |
| download | open-iov-e4c3f8554d70dcf22567621528a4601d7444666b.tar.gz open-iov-e4c3f8554d70dcf22567621528a4601d7444666b.zip | |
gsp-rm: fill GR info indices 7/9/0x17/0x22 (libcuda clock-table path; e94 TPC count)
| -rw-r--r-- | kernel/gsp_rm_emulation.c | 16 | ||||
| -rw-r--r-- | kernel/gsp_rm_tu104.h | 14 |
2 files changed, 29 insertions, 1 deletions
diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c index 777c63c..a9b63b1 100644 --- a/kernel/gsp_rm_emulation.c +++ b/kernel/gsp_rm_emulation.c @@ -1775,11 +1775,25 @@ static void gsp_rm_handle_kgr_get_info(struct gsp_emu_context *ctx, /* TU104 litter topology: 6 GPC x 4 TPC x 2 SM = 48 SMs */ info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_GPCS].data = TU104_NUM_GPC; - info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC].data = + TU104_GR_INFO_LITTER_NUM_TPC_PER_GPC; info->infoList[TU104_GR_INFO_IDX_GPU_CORE_COUNT].data = TU104_NUM_SM; info->infoList[TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC].data = TU104_SM_PER_TPC; info->infoList[TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC].data = TU104_TPC_PER_GPC; + /* Indices libcuda fetches via NV2080_CTRL_CMD_GR_GET_INFO when it + * builds the ucode-image clock table (GR_GET_INFO copies + * pGrInfo->infoList[index].data). Observed on real TU104: index 9 + * -> 24 (devstate+0xe94 TPC count; 0 makes FUN_003e35f0 return + * NV_ERR_INVALID_ARGUMENT and cuCtxCreate fail 999), index 7 -> 6, + * index 0x17 -> 6 (devstate+0xb0/+0xb4 SM/TPC), index 0x22 -> 48. */ + info->infoList[TU104_GR_INFO_IDX_SHADER_PIPE_COUNT].data = + TU104_GR_INFO_SHADER_PIPE_COUNT; + info->infoList[TU104_GR_INFO_IDX_SHADER_PIPE_SUB_COUNT].data = + TU104_GR_INFO_SHADER_PIPE_SUB_COUNT; + info->infoList[TU104_GR_INFO_IDX_RT_CORE_COUNT].data = + TU104_GR_INFO_RT_CORE_COUNT; + /* subcontext (VEID) counts: 64 per hw */ info->infoList[TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; info->infoList[TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT].data = TU104_MAX_SUBCONTEXT_COUNT; diff --git a/kernel/gsp_rm_tu104.h b/kernel/gsp_rm_tu104.h index ac90e38..7cd5a4b 100644 --- a/kernel/gsp_rm_tu104.h +++ b/kernel/gsp_rm_tu104.h @@ -958,15 +958,29 @@ struct tu104_gr_static_info { }; /* infoList indices we populate (ctrl0080gr.h) */ +#define TU104_GR_INFO_IDX_SHADER_PIPE_COUNT 0x07 +#define TU104_GR_INFO_IDX_SHADER_PIPE_SUB_COUNT 0x09 #define TU104_GR_INFO_IDX_LITTER_NUM_GPCS 0x14 #define TU104_GR_INFO_IDX_LITTER_NUM_TPC_PER_GPC 0x17 #define TU104_GR_INFO_IDX_GPU_CORE_COUNT 0x1d #define TU104_GR_INFO_IDX_LITTER_NUM_SM_PER_TPC 0x20 +#define TU104_GR_INFO_IDX_RT_CORE_COUNT 0x22 #define TU104_GR_INFO_IDX_FAMILY_MAX_TPC_PER_GPC 0x2a #define TU104_GR_INFO_IDX_MAX_SUBCONTEXT_COUNT 0x2c #define TU104_GR_INFO_IDX_MAX_LEGACY_SUBCONTEXT_COUNT 0x2d #define TU104_GR_INFO_IDX_MAX_PER_ENGINE_SUBCONTEXT_COUNT 0x2e +/* Values libcuda fetches through NV2080_CTRL_CMD_GR_GET_INFO (0x20801201) + * by info index (host-oracle observed on TU104): index 9 feeds the + * ucode-image clock table (devstate+0xe94 == TPC count 24); index 0x17 + * feeds the same table (devstate+0xb0 TPC / +0xb4 SM count); 7 and 0x22 + * feed the SM/RT caps. Zero here makes FUN_003e35f0 reject the clock + * table with NV_ERR_INVALID_ARGUMENT (cuCtxCreate rc=999). */ +#define TU104_GR_INFO_SHADER_PIPE_COUNT 6 +#define TU104_GR_INFO_SHADER_PIPE_SUB_COUNT 24 +#define TU104_GR_INFO_LITTER_NUM_TPC_PER_GPC 6 +#define TU104_GR_INFO_RT_CORE_COUNT 48 + /* TU104 max subcontexts (NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT) */ #define TU104_MAX_SUBCONTEXT_COUNT 64 |