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authorArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-06 22:09:22 -0500
committerArthur Hanson Rasmusson <arthur@vgpu.io>2026-11-06 22:09:22 -0500
commitdb401573f1a8a2a926901f752b4401e8916d976c (patch)
tree24bb1b9264478143a9dde674d70db1b8fcdca1dc
parent0aec62b805c493a4200d2e8edf4e46c90890fd55 (diff)
downloadopen-iov-db401573f1a8a2a926901f752b4401e8916d976c.tar.gz
open-iov-db401573f1a8a2a926901f752b4401e8916d976c.zip
vgsp-gl: GS SPH placement/maps/context A/B knobs
-rw-r--r--kernel/gsp_phys_booter.c57
-rw-r--r--kernel/gsp_phys_gpu.h6
-rw-r--r--kernel/gsp_sema_service.c17
3 files changed, 77 insertions, 3 deletions
diff --git a/kernel/gsp_phys_booter.c b/kernel/gsp_phys_booter.c
index 0fc2ee7..96fdc46 100644
--- a/kernel/gsp_phys_booter.c
+++ b/kernel/gsp_phys_booter.c
@@ -18713,6 +18713,42 @@ bool gsp_phys_rmcall_gr_raster_pre_value(void)
{
return READ_ONCE(gsp_phys_rmcall_gr_raster_pre);
}
+
+/*
+ * SESSION 155 CONT 15: where the synthesized GS SPH lives inside the
+ * program-family page. 0 = family+0x780 (below the window's own VTG bind
+ * at family+0x900), 1 = family+0xe80 (above it; the DS's PROGRAM_REGION
+ * snapshot reads the bind VA, so a region starting there does not cover
+ * 0x780). Default 0 = legacy.
+ */
+static u32 gsp_phys_rmcall_gr_sph_gs_addr;
+module_param_named(sema_gl_sph_gs_addr, gsp_phys_rmcall_gr_sph_gs_addr,
+ uint, 0644);
+MODULE_PARM_DESC(sema_gl_sph_gs_addr,
+ "Synth GS SPH offset in the family page: 0=+0x780 (legacy), 1=+0xe80 (above the VTG bind)");
+
+u32 gsp_phys_rmcall_gr_sph_gs_addr_value(void)
+{
+ return READ_ONCE(gsp_phys_rmcall_gr_sph_gs_addr);
+}
+
+/*
+ * SESSION 155 CONT 15: GS context A/B words emitted with the synth GS bind.
+ * bit0: SET_MESH_CONTROL (0x114c) <- 0
+ * bit1: SET_GS_MODE (0x0208) <- 0 (TYPE_ANY)
+ * The client's per-frame push carries neither; if the init push left them
+ * set, the GS macro/mesh path may treat the stage specially. Default 0.
+ */
+static u32 gsp_phys_rmcall_gr_sph_gs_ctx;
+module_param_named(sema_gl_sph_gs_ctx, gsp_phys_rmcall_gr_sph_gs_ctx,
+ uint, 0644);
+MODULE_PARM_DESC(sema_gl_sph_gs_ctx,
+ "Extra GS context with the synth bind: bit0=SET_MESH_CONTROL(0x114c)<-0, bit1=SET_GS_MODE(0x0208)<-0 (default 0)");
+
+u32 gsp_phys_rmcall_gr_sph_gs_ctx_value(void)
+{
+ return READ_ONCE(gsp_phys_rmcall_gr_sph_gs_ctx);
+}
static bool gsp_phys_gr_mme_pairs_emitted; /* launch emitted a pair run */
static u32 gsp_phys_gr_mme_pairs_gen; /* gen whose pairs retired OK */
static u32 gsp_phys_gr_mme_launch_gen; /* last built launch's gen */
@@ -29776,6 +29812,8 @@ gr_page_unmapped:
READ_ONCE(gsp_phys_rmcall_gr_sph_gs_mode);
bool emit_raster =
READ_ONCE(gsp_phys_rmcall_gr_raster_pre);
+ u32 gs_addr = READ_ONCE(gsp_phys_rmcall_gr_sph_gs_addr);
+ u32 gs_ctx = READ_ONCE(gsp_phys_rmcall_gr_sph_gs_ctx);
/*
* SESSION 155 CONT 9: the prelude is prepended ahead of
@@ -30004,7 +30042,9 @@ gr_page_unmapped:
(emit_j2 ? (bind_binding ? 8u : 7u) : 0u) +
(emit_j4 ? (bind_binding ? 8u : 7u) : 0u) +
(emit_j5 ? (bind_binding ? 8u : 7u) : 0u) +
- (emit_gsimg ? (9u + ((gs_mode & 1u) ? 11u : 0u)) : 0u) +
+ (emit_gsimg ? (9u + ((gs_mode & 1u) ? 11u : 0u) +
+ ((gs_ctx & 1u) ? 2u : 0u) +
+ ((gs_ctx & 2u) ? 2u : 0u)) : 0u) +
(emit_raster ? 17u : 0u)
<= 96u) {
/*
@@ -30211,7 +30251,8 @@ gr_page_unmapped:
* run here (nrun++ below).
*/
if (emit_gsimg) {
- u64 gva = fam + 0x780u;
+ u64 gva = fam + (gs_addr ? 0xe80u :
+ 0x780u);
in[nfin++] = 0x20000000u | (1u << 16) |
(0x2100u >> 2);
@@ -30246,6 +30287,18 @@ gr_page_unmapped:
in[nfin++] = 0u;
in[nfin++] = 0u;
}
+ if (gs_ctx & 1u) {
+ in[nfin++] = 0x20000000u |
+ (1u << 16) |
+ (0x114cu >> 2);
+ in[nfin++] = 0u;
+ }
+ if (gs_ctx & 2u) {
+ in[nfin++] = 0x20000000u |
+ (1u << 16) |
+ (0x0208u >> 2);
+ in[nfin++] = 0u;
+ }
in[nfin++] = 0x20000000u | (1u << 16) |
(0x2100u >> 2);
in[nfin++] = (gs_mode & 2u) ? 0x41u :
diff --git a/kernel/gsp_phys_gpu.h b/kernel/gsp_phys_gpu.h
index d7177a6..d84cd41 100644
--- a/kernel/gsp_phys_gpu.h
+++ b/kernel/gsp_phys_gpu.h
@@ -375,6 +375,12 @@ u32 gsp_phys_rmcall_gr_sph_gs_mode_value(void);
bool gsp_phys_rmcall_gr_raster_pre_value(void);
/*
+ * SESSION 155 CONT 15: synthesized GS SPH placement/maps/context A/B.
+ */
+u32 gsp_phys_rmcall_gr_sph_gs_addr_value(void);
+u32 gsp_phys_rmcall_gr_sph_gs_ctx_value(void);
+
+/*
* r1512: the viewport state the 3D replay injects for the current launch
* (sema_gl_vp_prelude mode + its literal words). Read-only; used by the
* sema service's draw-coverage receipt.
diff --git a/kernel/gsp_sema_service.c b/kernel/gsp_sema_service.c
index 4ede0c7..6972172 100644
--- a/kernel/gsp_sema_service.c
+++ b/kernel/gsp_sema_service.c
@@ -10657,7 +10657,9 @@ static void svc_gl_flush(struct nv_vgpu_device *vgpu,
};
u32 gs_maps =
gsp_phys_rmcall_gr_sph_gs_maps_value();
- u64 dst = fam + 0x780u;
+ u64 dst = fam +
+ (gsp_phys_rmcall_gr_sph_gs_addr_value() ?
+ 0xe80u : 0x780u);
bool dup = false;
u32 pi4;
@@ -10678,6 +10680,19 @@ static void svc_gl_flush(struct nv_vgpu_device *vgpu,
gs_words[17] = 0u;
} else if (gs_maps == 3u) {
gs_words[17] = 0u;
+ } else if (gs_maps == 4u) {
+ /* IMAP = previous OMAP; OMAP =
+ * PS IMAP exactly (POSITION.W). */
+ gs_words[5] = 0xf0000000u;
+ gs_words[10] = 0x0000000fu;
+ gs_words[13] = 0x00008000u;
+ gs_words[17] = 0u;
+ } else if (gs_maps == 5u) {
+ /* mesh-dummy IMAP, OMAP POSITION.W. */
+ gs_words[5] = 0u;
+ gs_words[10] = 0u;
+ gs_words[13] = 0x00008000u;
+ gs_words[17] = 0u;
}
/* SESSION 155 CONT 13: mesh-dummy FASTGS
* form (bit24 ENABLE_FAST_G_S). */