vgsp-disp: unconditional pushbuffer receipt log + NvBool valid fix

Log every NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58)
receipt with the decoded 56-byte params struct, and always log rejected
channel registrations and SET_NOTIFIER_DMA - boot-only volume, settles
whether the kernel RM ever programs the display push buffers through
that control (r1621 follow-up).

valid is an NvBool (1 byte); the previous u32 load could read the
padding bytes and turn a PIO-channel valid=0 into a false positive.

Raise the engine log budget to 4096.

2 files changed, 32 insertions, 11 deletions

diff --git a/kernel/gsp_display_engine.c b/kernel/gsp_display_engine.c
index 01495ac..9c00a22 100644
--- a/kernel/gsp_display_engine.c
+++ b/kernel/gsp_display_engine.c
@@ -477,9 +477,14 @@ void gsp_disp_engine_channel_add(struct nv_vgpu_device *vgpu, u32 hclass,
 		return;
 
 	if (!valid || !pb_pa || !gsp_disp_ctl_offset(hclass, instance)) {
-		if (gsp_sema_dbg)
-			pr_info("channel skipped: class=0x%x inst=%u pa=0x%llx limit=0x%llx valid=%d\n",
-				hclass, instance, pb_pa, limit, valid);
+		/*
+		 * Always log a rejected registration: this is the one line
+		 * that says whether the guest programmed a channel the
+		 * engine could not take (PIO channel, zero PA, unknown
+		 * class).  It is boot-only volume.
+		 */
+		pr_info("channel skipped: class=0x%x inst=%u pa=0x%llx limit=0x%llx valid=%d\n",
+			hclass, instance, pb_pa, limit, valid);
 		return;
 	}
 
@@ -559,10 +564,9 @@ static void gsp_disp_method(struct nv_vgpu_device *vgpu,
 				ch->notifier_pa_valid = true;
 			}
 		}
-		if (gsp_disp_dbg)
-			pr_info("h=0x%x push=0x%x SET_NOTIFIER_DMA handle=0x%x -> pa=0x%llx valid=%d\n",
-				ch->hclass, push_off, value, ch->notifier_pa,
-				ch->notifier_pa_valid);
+		pr_info("h=0x%x push=0x%x SET_NOTIFIER_DMA handle=0x%x -> pa=0x%llx valid=%d\n",
+			ch->hclass, push_off, value, ch->notifier_pa,
+			ch->notifier_pa_valid);
 		return;
 	}
 	if (addr == notifier_ctrl) {
@@ -811,7 +815,7 @@ void gsp_disp_engine_pump(struct nv_vgpu_device *vgpu)
 		get = gsp_disp_bar0_read(vgpu,
 					 s->ctl_off + GSP_DISP_REG_GET);
 
-		if (gsp_disp_dbg && disp.log_budget < 2048) {
+		if (disp.log_budget < 4096) {
 			u64 age = (u64)(now - disp.boot_jiffies) *
 				  (NSEC_PER_SEC / HZ);
 
diff --git a/kernel/gsp_rm_emulation.c b/kernel/gsp_rm_emulation.c
index bb74767..3157a24 100644
--- a/kernel/gsp_rm_emulation.c
+++ b/kernel/gsp_rm_emulation.c
@@ -4401,11 +4401,28 @@ static void gsp_rm_handle_rm_control(struct gsp_emu_context *ctx,
 		const u8 *pp = req_data + GSP_RM_CTRL_HDR_SIZE;
 		u8 *rp = reply + GSP_RM_CTRL_HDR_SIZE;
 
-		if (req.paramsSize >= 52 &&
+		/*
+		 * The real struct (NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_
+		 * PUSHBUFFER_PARAMS) is 56 bytes: addressSpace@0,
+		 * physicalAddr@8, limit@16, cacheSnoop@24, hclass@28,
+		 * channelInstance@32, valid@36 (NvBool = 1 byte!),
+		 * pbTargetAperture@40, channelPBSize@44, subDeviceId@48.
+		 * Read valid as a byte: the 3 padding bytes after it are not
+		 * guaranteed zero, so a u32 load can turn valid=0 (PIO
+		 * cursor channel) into a false positive.
+		 */
+		pr_info("rm-ctl: display channel pushbuffer hObject=0x%x size=%u pa=0x%llx limit=0x%llx class=0x%x inst=%u valid=%u\n",
+			req.hObject, req.paramsSize,
+			req.paramsSize >= 24 ? *(const u64 *)(pp + 8) : 0,
+			req.paramsSize >= 24 ? *(const u64 *)(pp + 16) : 0,
+			req.paramsSize >= 32 ? *(const u32 *)(pp + 28) : 0,
+			req.paramsSize >= 36 ? *(const u32 *)(pp + 32) : 0,
+			req.paramsSize >= 37 ? pp[36] : 0);
+		if (req.paramsSize >= 40 &&
 		    req.paramsSize + GSP_RM_CTRL_HDR_SIZE <=
 				GSPRM_MAX_SINGLE_ELEM_DATA) {
 			u32 address_space = 0, hclass = 0, instance = 0;
-			u32 valid = 0;
+			u8 valid = 0;
 			u64 pa = 0, limit = 0;
 
 			memcpy(&address_space, pp + 0, 4);
@@ -4413,7 +4430,7 @@ static void gsp_rm_handle_rm_control(struct gsp_emu_context *ctx,
 			memcpy(&limit, pp + 16, 8);
 			memcpy(&hclass, pp + 28, 4);
 			memcpy(&instance, pp + 32, 4);
-			memcpy(&valid, pp + 36, 4);
+			valid = pp[36];
 			memcpy(rp, pp, req.paramsSize);
 			gsp_disp_engine_channel_add(ctx->vgpu, hclass, instance,
 						    pa, limit, address_space,